CN113191110A - DDR4 address control line mapping and Ball arrangement method for T-type topological structure - Google Patents
DDR4 address control line mapping and Ball arrangement method for T-type topological structure Download PDFInfo
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Abstract
The invention provides a DDR4 address control line mapping and Ball arrangement method aiming at a T-type topological structure, which meets the requirements of signal quality and timing sequence margin. The mapping and arranging method of the invention is characterized in that: according to the arrangement of the positions of the via holes, address/control lines adjacent to the via holes are distributed in a group when being mapped; i.e. one delay configuration is shared in the configuration of the DDR controller. The point-to-point signals correspond to the same memory and are distributed in a group. The pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to each other, so that the delay is close. The address/control signals in the same group are routed in the same inner layer. The comprehensive eye diagram has optimal quality, and the difficulty of equal length of the PCB winding can be reduced while the maximization of the time sequence margin is realized. The method has the advantages that the maximization of the address/control line time sequence margin is met while the equal-length processing of a special PCB is not needed, the PCB design is simplified, the wiring area is reduced, and meanwhile the consistency of the hardware design is ensured.
Description
Technical Field
The invention relates to the field of System On Chip (SOC) packaging arrangement and address mapping, in particular to a DDR4 address control line mapping and Ball arrangement method for a T-type topological structure.
Background
With the increase of the dominant frequency of the system, the application of the high-definition camera and more algorithm applications, such as face recognition, mobile phones and intelligent camera systems, become higher and higher. The DDR memory rate used in the system also increases and the number of memories increases. The signal integrity problem caused by the speed increase follows, the signal is extremely deteriorated by the topological structure of a plurality of memories, and two address/control topological structures commonly used in the industry have advantages and disadvantages respectively:
the T-topology, which is commonly used in two-slice memory schemes, is not suitable for multiple slices. The Fly-by structure is mainly used for a multi-chip scheme, the more chips are, the more obvious signal deterioration is, the special design needs to be made on the impedances of the branch and the main line to meet impedance matching, and meanwhile, the length of the branch obviously affects the speed. The T-topology scheme discussed herein is mostly used in a scenario where two pieces of memory are driven simultaneously, and the layout and routing area of the T-topology structure is smaller compared to the Fly-by structure. The disadvantage is that in a high-speed application scene, the delay difference from the bifurcation point of the T-shaped structure to the two memories simultaneously influences the quality of the eye diagram and the margin of establishing the holding time. In order to ensure that the design meets the requirements on signal quality and timing margin, branch delay and the like need to be controlled, delay difference of multiple signal lines in a control group is controlled, and strict requirements on PCB design can increase the wiring area. Meanwhile, what is easily overlooked is that the routing lines which look equal in length are caused by different unit-length routing delays of the outer layer and the inner layer of the PCB, the delays are not consistent in practice, and uncontrollable factors exist when the requirements of signal quality control are delivered to customers.
Disclosure of Invention
The invention provides a DDR4 address control line mapping and Ball arrangement method aiming at a T-type topological structure, which meets the requirements of signal quality and timing sequence margin.
The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a DDR4 address control line mapping and Ball arrangement method for a T-type topological structure, which is characterized in that: according to the arrangement of the positions of the via holes, address/control lines adjacent to the via holes are distributed in a group when being mapped; i.e. one delay configuration is shared in the configuration of the DDR controller.
Preferably, the point-to-point signals correspond to the same memory allocation in a group.
Preferably, the pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to each other, so as to ensure that the time delays are close.
Preferably, the address/control signals within the same group are routed within the same inner layer.
The invention has the beneficial effects that: the comprehensive eye pattern has optimal quality, the difficulty of equal length of PCB winding can be reduced while the maximization of timing sequence margin is realized, and the PCB wiring area is reduced. The method has the advantages that the maximization of the address/control line time sequence margin is met while the equal-length processing of a special PCB is not needed, the PCB design is simplified, the wiring area is reduced, and meanwhile the consistency of the hardware design is ensured.
Drawings
FIG. 1 is an application case of DDR4 address control line mapping and Ball arrangement method for T-type topology of the invention;
FIG. 2 is a T-topology targeted by the DDR4 address control line mapping and Ball arrangement method of the present invention for a T-topology.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is an application case of the DDR4 address control line mapping and Ball arrangement method for the T-type topology of the present embodiment. A, B are two address/control signals in the same group, the delay of each segment is as follows, for the sake of discussion, it is assumed that the branches after T are equal, i.e. Ta3＝ta4,tb3Tb 4. At the receiving end of any one memory, the delay of the address control line satisfies formula 1. According to the previous discussion, the delay of the network a, network B will affect the size of the sampling window for signals within the same group. For maximum timing margin, | tA-tBL should be less than the delay adjustment step of the controller, or less. To meet this requirement, it is necessary to control the calculation of count of cells on the PCB tracetA-tBL. Due to the fixed location of the memory address in the JEDEC protocol, ta3,tb3Is clear, ta2,ta3,tb2,tb3The delay offset is related to the Ball position corresponding to the DDR controller, and if the positions of the network a and the network B on the DDR controller side are relatively far, delay compensation needs to be performed on the PCB trace to meet the delay offset. This increases the routing difficulty and routing area of the PCB.
The scheme provided by the invention is a ball map arrangement and address/control signal mapping scheme, and meets the optimal timing sequence margin while no extra PCB routing compensation is needed.
Equation 1:
tA＝ta1+ta2+ta3
tB＝tb1+tb2+tb3
the Ball address locations of the DDR4 memory are fixed, except for the number of individual address signals such as RAS, CAS, BG1, which are different due to the page, bank, of the memory. When a T-shaped mechanism is used, the two memories are arranged back to back, and the fan-out mode of signals is relatively fixed.
The principles of address mapping and pin distribution and PCB routing are as follows:
the address/control lines adjacent to the vias are assigned in a group when mapped according to the arrangement of the via locations. I.e. one delay configuration is shared in the configuration of the DDR controller.
The pins of the DDR controller are arranged and arranged at adjacent positions in the same group so as to ensure that the time delay is close, and the extra routing is not needed, the equal length is satisfied, so that the time delay adjustment is realized
The address/control signals in the same group are wired in the same inner layer, and the signal delay difference in the same group caused by the fact that the lengths of the via holes are different can be avoided.
CS, ODT, CKE point-to-point signals, corresponding to a group of memory banks
According to the three principles, when the address of the controller is remapped, the pin arrangement and the PCB wiring are carried out, the maximization of address/control line time sequence margin can be met while special equal-length processing of the PCB is not needed, the PCB design is simplified, the wiring area is reduced, and meanwhile the consistency of hardware design is guaranteed.
For the timing requirement of the address signal of the DDR memory in the JESD79-4A protocol, a certain setup holding time needs to be satisfied at the receiving end of the address signal, that is, the input end of the memory. In practical applications, the address signal and the clock signal have a delay adjusting mechanism, and the delay of the clock and the address/control signal, i.e. the signal sampling point, can be adjusted within at least one UI (unit time interval). The signal integrity simulation is not concerned with a specific setup hold time, but rather with the effective sampling window of the signal, i.e., the signal eye width. Considering the signal eye width, DDR controller clock jitter, power-induced signal jitter, and latency differences for the same set of address/control lines are required in addition to the sampling window of the memory itself.
It should be noted that, the same group of address/control signals share a delay configuration in the configuration of the DDR controller, which means that the delay difference between the signal package and the PCB in the control group needs to be smaller than the step of the delay adjustment for the signal lines in the same group, so as to ensure the delay adjustment of the clock and address/control signals, and to ensure the effective setup holding time within the minimum signal eye width. To meet the timing requirement, the signals CA1, CA2 in the same group are added with an additional delay T — N × unit steps. During the adjustment, CA1 and CA2 have fixed delay difference Δ t of the PCB due to packaging, and additional sampling window requirements are added. Therefore, it is necessary to consider the delay differences of a plurality of signal lines in a group of the same delay arrangement in addition to the eye width for the address/control signal lines.
Fig. 2 is a T-type topology targeted by the DDR4 address control line mapping and Ball arrangement method for the T-type topology of the present embodiment. After the DDR address/control line routing surface layer is fanned out, the DDR address/control line routing surface layer passes through a branch point from the inner layer to the T-shaped structure and then passes through the top layer and the bottom layer to the two memories from the branch point, and the two memories are opposite in position. In order to analyze the influence of the branch, a T-type topology is modeled in simulation software, the length from the controller to the branch point is fixed to be L1-15 mm, the track length from the branch point to the first memory is L2, and the track length from the branch point to the second memory is L3. The following simulation case adjusts the length of L2, L3 to see eye changes.
Fixed L1-15 mm, L2-5 mm, L3-3 mm,4mm,5mm,6mm,7mm,8mm,9 mm. From the simulation results, it can be seen that the eye diagrams of memory 1 and memory 2 are the same when the lengths of the branches are equal. When the lengths of the branches are not equal, the memory receiving eye pattern where the branches are short is deteriorated, and the eye pattern is further deteriorated as the difference of the branch lengths becomes larger. Eye diagrams of 15mm for L1, 5mm for L3 and 12mm for L3 for L2 are fixed, and it can be seen that the eye diagram of the signal deteriorates as the absolute length of the branch becomes longer. In practical application, due to the existence of crosstalk, with the length of a side of a trace length, crosstalk signal coupling is increased, and eye diagram deterioration of a long branch is more obvious.
To analyze the delay effect of the via, the modeling is as follows: the 6-layer structure, network a, fans out from the top layer, through the vias to the fourth layer, and then from the vias to the top layer. The net B is fanned out from the top layer to the third layer through the via holes and then to the top layer net from the via holes. A and B are only the difference of via holes, the length of each section is equal, the third layer and the fourth layer are complete in routing reference layer, and the routing length and the time delay are equal. In other words, the delay difference of the two networks is only the via delay difference from the top layer to the third layer and from the top layer to the 4 th layer.
The results of the delay are as follows: the delay difference from the top layer to the third layer, and the top layer to the 4 th layer via length difference was 28.3ps depending on the stack. The adjustment of the address/control lines is stepped with respect to the delay difference of the tracks, which delay difference is not negligible. This causes a problem that when the thickness of the wiring stack, i.e. the length of the via hole, is not fixed, and in the actual wiring, the time delay per unit length of the outer microstrip line and the inner stripline is not consistent. This results in delay control that is difficult to control by the equal length of the PCB traces. Even if the traces are seen to be equal in length, the delays are not equal. Without simulation, the delay within the group cannot be known and controlled. Even if the same routing is performed, the delay introduced by the via holes of different layers is different due to different thicknesses of the PCBs, which brings inconsistency of hardware and uncontrollable design scheme of customers.
Combining the above simulations, the conclusion is as follows: layout for two memories of T-type
When the branch lengths are equal, the signal quality is optimal.
When the branch lengths are not equal, the signal eye pattern degradation is more pronounced for the short branches.
Also, in the case of equal branch lengths, the shorter the branch, the better, the length of the branch will affect the eye width.
If the branch length is too long, or if the difference in the trace lengths of the branches is large, the width of the eye pattern, and thus the speed of the address/control lines, is affected.
The via holes introduce additional delay, the same case of traces, and the signal delay difference in the same group of signals due to the different layers of the traces.
The above simulation is based on the evaluation of a single signal line, and in a practical system, the eye pattern closing will be more obvious due to the influence of crosstalk between lines.
The proposal of the pin arrangement in the invention is to adjust the address/control line mapping scheme of the controller according to the fixed address signal distribution of the DRAM, and control the interclass delay difference of the same group of address/control lines by the simplest PCB routing.
Claims (4)
1. A DDR4 address control line mapping and Ball arrangement method for a T-type topology is characterized in that: according to the arrangement of the positions of the via holes, address/control lines adjacent to the via holes are distributed in a group when being mapped; i.e. one delay configuration is shared in the configuration of the DDR controller.
2. The DDR4 address control line mapping and Ball arrangement method for T-type topology of claim 1, wherein: the point-to-point signals correspond to the same memory and are distributed in a group.
3. The DDR4 address control line mapping and Ball arrangement method for T-type topology as claimed in claim 1 or 2, wherein: the pins of the DDR controller are arranged, and the arrangement positions of the pins in the same group are adjacent to each other, so that the delay is close.
4. The DDR4 address control line mapping and Ball arrangement method for T-type topology as claimed in claim 1 or 2, wherein: the address/control signals in the same group are routed in the same inner layer.
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