CN112803959B

CN112803959B - Transceiver circuit and signal processing method applied to same

Info

Publication number: CN112803959B
Application number: CN201911108357.0A
Authority: CN
Inventors: 何轩廷; 黄亮维
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2022-05-10
Anticipated expiration: 2039-11-13
Also published as: CN112803959A

Abstract

The invention discloses a transceiver circuit and a signal processing method applied to the transceiver circuit. In operation of the transceiver circuit, the adc performs an analog-to-digital conversion operation on an analog input signal to generate a digital input signal, the steady-state circuit generates a steady-state echo response according to a transmission signal, the transient circuit generates an echo response adjustment signal generated due to a phase change of a frequency signal used by the transmission signal according to the transmission signal, and the output circuit generates an output signal according to the digital input signal, the steady-state echo response, and the echo response adjustment signal.

Description

Transceiver circuit and signal processing method applied to same

Technical Field

The present invention relates to a transceiver circuit, and more particularly, to a transceiver circuit including an echo cancellation circuit.

Background

In a full-duplex ethernet system, a master device (master) first transmits a free-run (free-run) symbol signal to a slave device (slave), which then locks the frequency of the symbol signal and uses the frequency to transmit a signal back to the master device. In addition, because of the full duplex architecture, the transmission line between the master device and the slave device has both transmission signal and reception signal, if there is impedance mismatch in the transmission line or mismatch between the receiver and the related circuit architecture, some signal components in the transmission signal will bounce back to the reception path, and these bounced signal components are generally called echo signals.

Since the oscillators in the master and slave devices are not identical, the receiver in the slave device locks the frequency of the frequency signal of the master device by changing the phase of the frequency signal, and then the transmitter in the slave device transmits a signal to the master device by using the phase-changed frequency signal. However, the above-mentioned method of changing the phase of the frequency signal in the receiver and then changing the phase of the frequency signal in the transmitter will generate an instantaneous echo response, which affects the system performance. On the other hand, the phase adjustment amount of the frequency signal is designed to be larger to reduce the complexity of the phase selector in consideration of the circuit cost, however, increasing the phase adjustment amount of the frequency signal per time makes the situation of the transient echo response worse.

Disclosure of Invention

It is therefore an object of the present invention to provide a transceiver circuit that can effectively cancel an instantaneous echo response when a phase of a frequency signal used by a transmitter is changed, so as to solve the problems described in the prior art.

In an embodiment of the present invention, a transceiver circuit is disclosed, which includes an analog-to-digital converter and an echo cancellation circuit, and the echo cancellation circuit includes a steady-state circuit, a transient circuit and an output circuit. In operation of the transceiver circuit, the adc performs an analog-to-digital conversion operation on an analog input signal to generate a digital input signal, the steady-state circuit generates a steady-state echo response according to a transmission signal, the transient circuit generates an echo response adjustment signal generated due to a phase change of a frequency signal used by the transmission signal according to the transmission signal, and the output circuit generates an output signal according to the digital input signal, the steady-state echo response, and the echo response adjustment signal.

In another embodiment of the present invention, a signal processing method applied in a transceiver circuit is disclosed, which includes the following steps: performing analog-to-digital conversion operation on an analog input signal to generate a digital input signal; generating a steady echo response according to a transmission signal; generating a echo response adjustment signal generated due to the phase change of a frequency signal used by the transmission signal according to the transmission signal; and generating an output signal according to the digital input signal, the steady state echo response and the echo response adjustment signal.

Drawings

Fig. 1 is a schematic diagram of a transceiver circuit applied in a full-duplex ethernet network according to an embodiment of the present invention.

Fig. 2A to 2D are schematic diagrams of an instantaneous echo response when the phase of a frequency signal changes.

Fig. 3 shows a schematic diagram of determining a starting point at which to start generating an echo response adjustment signal.

Fig. 4A is a diagram illustrating specific data.

Fig. 4B shows a schematic diagram of the determination of the point in time at which the first coefficient in the echo response adjustment signal is zeroed.

Fig. 5 is a flowchart of a signal processing method applied in a transceiver circuit according to an embodiment of the invention.

Detailed Description

Fig. 1 is a schematic diagram of a transceiver circuit 100 applied to a full-duplex ethernet network according to an embodiment of the present invention. As shown in fig. 1, the transceiver circuit 100 includes an analog-to-digital converter 110, an echo cancellation circuit 120, a control circuit 130, a frequency generation circuit 140, a processing circuit 150, a transmission circuit 160, a buffer 170, and a digital-to-analog converter 180, wherein the echo cancellation circuit 120 includes a steady-state circuit 122, a transient circuit 124, and an output circuit 126. In the present embodiment, the transceiver circuit 100 is disposed in a slave device, that is, the transceiver circuit 100 receives a symbol signal from a master device and locks the frequency of the symbol signal by adjusting the phase of the clock signal CLK generated by the clock signal generating circuit 140.

In the operation of the transceiver circuit 100, the adc 110 receives an analog input signal Vin from the host device and performs an analog-to-digital conversion operation on the analog input signal Vin according to the clock signal CLK to generate a digital input signal Din. Then, since the transceiver circuit 100 is applied to the full duplex ethernet network, when the transmitter circuit 160 generates a digital transmission signal D _ TX and generates an analog transmission signal V _ TX to the host device through the dac 180, the analog transmission signal V _ TX has a part of energy bounce so that the analog input signal Vin includes the echo signal. Therefore, to cancel the echo signal, the digital transmission signal D _ TX is transmitted to the steady-state circuit 122 in the echo cancellation circuit 120 through the buffer 170, and the steady-state circuit 122 includes a Finite Impulse Response (FIR) filter to generate a steady-state echo Response D _ ER, and then the output circuit 126 subtracts the steady-state echo Response D _ ER from the digital input signal Din to generate an output signal Dout. If the steady-state echo response D _ ER is not equal to the echo component included in the output signal Dout, the output signal Dout has an echo cancellation error, and the processing circuit 150 may use a least mean square (least mean square) algorithm to generate the control signal EC1 to update the tap coefficients used by the fir filter in the steady-state circuit 122, so that the steady-state echo response D _ ER is closer to the echo component included in the digital input signal Din.

On the other hand, since the oscillators in the master device and the slave device are not identical, the control circuit 130 generates the control signal Vc to the frequency generation circuit 140 to adjust the phase of the frequency signal CLK (which can also be regarded as adjusting the frequency of the frequency signal CLK) to lock the frequency of the analog input signal Vin from the master device. After the phase of the clock signal CLK is adjusted, the transfer circuit 160 also uses the phase-adjusted clock signal CLK to generate the digital transfer signal D _ TX. However, the operation of sampling the analog input signal Vin according to the adjusted frequency signal CLK and then generating the digital transmission signal D _ TX using the adjusted frequency signal CLK causes the echo signal to change, i.e. an instantaneous echo response different from the steady-state echo response D _ ER occurs. In order to solve the problem of transient echo response, the transient circuit 124 included in the echo cancellation circuit 120 generates an echo response adjustment signal D _ ERT according to the digital transmission signal D _ TX, so as to adjust the steady-state echo response D _ ER to generate a transient echo response. Referring to fig. 1, the difference between the steady-state echo response D _ ER and the echo response adjusting signal D _ ERT can be regarded as an instantaneous echo response, and the output circuit 126 subtracts the instantaneous echo response from the digital input signal Din to generate the output signal Dout. If the steady-state echo response D _ ER is not equal to the echo component contained in the output signal Dout, the output signal Dout may have an echo cancellation error, and the processing circuit 150 may use a Least Mean Square (LMS) algorithm to generate the control signal EC2 to update the tap coefficients used by the finite impulse response filter in the transient circuit 124, so that the transient echo response is closer to the echo component contained in the digital input signal Din.

As described above, by the operation of the transient circuit 124, an appropriate echo response adjustment signal D _ ERT can be generated when the phase of the frequency signal CLK changes, so that the output circuit 126 can effectively and accurately delete the echo component of the digital input signal Din. In addition, the transient circuit 124 may only need to be turned on to generate the echo response adjusting signal D _ ERT when the phase of the frequency signal CLK changes, and the transient circuit 124 may be turned off when the transient echo response condition disappears to save power consumption.

Specifically, refer to fig. 2A to 2D, which are schematic diagrams of transient echo response when the phase of the clock signal CLK changes, wherein fig. 2A to 2D assume that each time the phase of the clock signal CLK needs to change, the phase change amount is one fourth of the period of the clock signal, but this is only for convenience of illustration and is not a limitation of the present invention. Refer first to FIG. 2A, where D_-1～D_-8Respectively representing data of the digital transmission signal D _ TX at different time points, and R_-1Which represents the point in time when the frequency signal CLK is used by the analog-to-digital converter 110 to sample the analog input signal Vin. R_-1And D_-1～D_-8The

time differences

3, 7, 11, 15, 19, 23, 27, 31 between them reflect the steady-state echo response D _ ER, i.e. the tap coefficients C0-C7 used by the fir filter in the steady-state circuit 122. Ideally, in the case where neither the frequency/phase of the frequency signal CLK is changed, the tap coefficients C0-C7 would be steady states and may be fixed values.

Next, in FIG. 2B, it is assumed that the control circuit 130 generates the control signal Vc to the clock generation circuit 140 to change the phase of the clock signal CLK to compensate for the frequency offset from the host device, such as the phase of the clock signal CLK is advanced by a quarter of a cycle, at this time R₀And D₀～D_-7The time difference between the two signals becomes 2, 6, 10, 14, 18, 22, 26, 30, that is, the echo response changes globally, that is, the echo response can be regarded as the transient echo response, and the tap coefficients C0-C7 used by the fir filter in the steady-state circuit 122 cannot reflect the transient echo response.

In FIG. 2C, it is assumed that the transfer circuit 160 generates the data D1 by using the phase-changed clock signal CLK in the next cycle of the clock signal CLK₁And D₁～D_-6The time difference between them becomes 3, 6, 10, 14, 18, 22, 26, 30, i.e. the first tap coefficient C0 of the echo response is restored to the original oneNumerical values. Next, in FIG. 2D, R₂And D₂～D_-5The time difference between them becomes 3, 7, 10, 14, 18, 22, 26, 30, i.e. the first tap coefficient C0, C1 of the echo response is restored to the original value.

As described above, when the adc 110 samples the analog input signal Vin by using the phase-changed clock signal CLK, the tap coefficients C0-C7 of the echo response are changed, and then the tap coefficients C0-C7 of the echo response are sequentially restored to their original values after the transmission circuit 160 generates the digital transmission signal D _ TX by using the phase-changed clock signal CLK. The tap coefficients of the echo response can be as shown in table one, where T0-T11 represent the period of the frequency signal CLK, C1 '-C7' represent the tap coefficients of the transient echo response caused by the phase change of the frequency signal CLK, and the numbers after the brackets represent the time points (e.g., R) at which the analog-to-digital converter 110 samples the analog input signal Vin by using the frequency signal CLK in fig. 2A-2D_-1～R₂) The time difference with each data in the digital transmission signal D _ TX.

T0

C0(3)

C1(7)

C2(11)

C3(15)

C4(19)

C5(23)

C6(27)

C7(31)

T1

C0’(2)

C1’(6)

C2’(10)

C3’(14)

C4’(18)

C5’(22)

C6’(26)

C7’(30)

T2

C0’(2)

C1’(6)

C2’(10)

C3’(14)

C4’(18)

C5’(22)

C6’(26)

C7’(30)

T3

C0(3)

C1’(6)

C2’(10)

C3’(14)

C4’(18)

C5’(22)

C6’(26)

C7’(30)

T4

C0(3)

C1(7)

C2’(10)

C3’(14)

C4’(18)

C5’(22)

C6’(26)

C7’(30)

T6

C0(3)

C1(7)

C2(11)

C3’(14)

C4’(18)

C5’(22)

C6’(26)

C7’(30)

T7

C0(3)

C1(7)

C2(11)

C3(15)

C4’(18)

C5’(22)

C6’(26)

C7’(30)

T8

C0(3)

C1(7)

C2(11)

C3(15)

C4(19)

C5’(22)

C6’(26)

C7’(30)

T9

C0(3)

C1(7)

C2(11)

C3(15)

C4(19)

C5(23)

C6’(26)

C7’(30)

T10

C0(3)

C1(7)

C2(11)

C3(15)

C4(19)

C5(23)

C6(27)

C7’(30)

T11

C0(3)

C1(7)

C2(11)

C3(15)

C4(19)

C5(23)

C6(27)

C7(31)

Watch 1

Referring to the content of table one, if the tap coefficient of each period is subtracted from the tap coefficients C0-C7 of the steady-state echo response, the content of table two shown below is obtained, where the content of table two is the echo response adjusting signal D _ ERT output by the transient circuit 124.

T0	0	0	0	0	0	0	0	0
									T1	ΔC0	ΔC1	ΔC2	ΔC3	ΔC4	ΔC5	ΔC6	ΔC7
T2	ΔC0	ΔC1	ΔC2	ΔC3	ΔC4	ΔC5	ΔC6	ΔC7
									T3	0	ΔC1	ΔC2	ΔC3	ΔC4	ΔC5	ΔC6	ΔC7
T4	0	0	ΔC2	ΔC3	ΔC4	ΔC5	ΔC6	ΔC7
									T6	0	0	0	ΔC3	ΔC4	ΔC5	ΔC6	ΔC7
T7	0	0	0	0	ΔC4	ΔC5	ΔC6	ΔC7
									T8	0	0	0	0	0	ΔC5	ΔC6	ΔC7
T9	0	0	0	0	0	0	ΔC6	ΔC7
									T10	0	0	0	0	0	0	0	ΔC7
T11	0	0	0	0	0	0	0	0

In one embodiment, the processing circuit 150 first detects a pattern of the echo response adjusting signal D _ ERT by using a plurality of phase changes of the clock signal CLK, wherein the pattern includes a start point (i.e., T1 in table two) of the echo response adjusting signal D _ ERT occurring when the phase of the clock signal CLK changes, and a time point (i.e., T2 in table two) of the echo response adjusting signal D _ ERT at which the first coefficient is zero. After determining the pattern of the echo response adjusting signal D _ ERT, the processing circuit 150 can adjust the tap coefficients Δ C0- Δ C7 used by the fir filter in the transient circuit 124 according to the determined pattern each time the phase of the clock signal CLK changes, so as to generate the echo response adjusting signal D _ ERT correctly.

For example, with respect to detecting the starting point of the generation of the echo response adjusting signal D _ ERT, the transmitting circuit 160 may generate a specific data to the transient circuit 124 when the phase of the clock signal CLK changes, so that the transient circuit 124 generates the echo response adjusting signal D _ ERT (i.e., can be regarded as an error signal) at the period T0, and then repeatedly generates the echo response adjusting signal D _ ERT at the period T0 when the phase of the clock signal CLK changes, so as to generate the appropriate tap coefficients using least mean square. In the embodiment, since no error occurs during the period T0, the tap coefficients cannot be generated (i.e., the tap coefficients are all 0), so it can be determined that the period T0 is not the starting point for the generation of the echo response adjustment signal D _ ERT. Then, the transmitting circuit 160 may generate specific data to the transient circuit 124 when the phase of the clock signal CLK changes, so that the transient circuit 124 generates the echo response adjusting signal D _ ERT at the period T1, and then repeatedly generates the echo response adjusting signal D _ ERT at the period T1 when the phase of the clock signal CLK changes, so as to generate the suitable tap coefficients using least mean square. In the embodiment, since an error occurs during the period T1, the tap coefficients C0 to C7 can be obtained, and it can be determined that the period T1 is the starting point of the echo response adjustment signal D _ ERT. Fig. 3 is a schematic diagram illustrating the determination of the starting point of the generation of the echo response adjustment signal D _ ERT, wherein the processing circuit 150 may take absolute values of tap coefficients C0 to C7 generated in different periods T0, T1 and T2 and accumulate the absolute values, and the time point when the accumulated value starts to increase may be regarded as the starting point of the generation of the echo response adjustment signal D _ ERT.

Next, after the start point of the generation of the echo response adjustment signal D _ ERT begins, the transmitting circuit 160 may transmit specific data as shown in fig. 4A to the transient circuit 124 for the transient circuit 124 to generate the echo response adjustment signal D _ ERT, and for the transient circuit 124 to generate a suitable tap coefficient by using the least mean square algorithm, and accordingly obtain a time point when the first coefficient in the echo response adjustment signal D _ ERT returns to zero. Fig. 4B is a schematic diagram illustrating a determination of a time point when the first coefficient of the echo response adjustment signal D _ ERT is zeroed, wherein the processing circuit 150 may obtain absolute values of tap coefficients C0-C7 corresponding to data D0 and accumulate the absolute values, obtain absolute values of tap coefficients C0-C7 corresponding to data D1 and accumulate the absolute values of tap coefficients C0-C7 corresponding to data D2 and accumulate … …, and a time point when the accumulated values start to decrease may be regarded as a time point when the first coefficient of the echo response adjustment signal D _ ERT is zeroed.

It should be noted that the above calculation for determining the echo response adjusting signal D _ ERT mode is only an exemplary illustration and is not a limitation of the present invention. In other embodiments, the transmitting circuit 160 may generate different data, and the processing circuit 150 may also use other calculation methods to determine the echo response adjusting signal D _ ERT mode.

Fig. 5 is a flowchart of a signal processing method applied in a transceiver circuit according to an embodiment of the invention. Referring also to the disclosure of the following embodiments, the process of FIG. 5 is as follows.

Step 500: the process begins.

Step 502: an analog-to-digital conversion operation is performed on an analog input signal to generate a digital input signal.

Step 504: a steady-state echo response is generated based on a transmitted signal.

Step 506: an audio response adjustment signal generated by a phase change of a frequency signal used by the transmission signal is generated according to the transmission signal.

Step 508: an output signal is generated according to the digital input signal, the steady state echo response and the echo response adjustment signal.

Briefly summarized, in the transceiver circuit of the present invention, the transient circuit is disposed in the echo cancellation circuit to effectively cancel the transient echo response when the phase of the frequency signal used by the transmitter is changed, so that the problem of the signal quality being greatly reduced when the phase of the frequency signal is changed can be avoided.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.

[ notation ] to show

100 transceiver circuit

110A/D converter

120 echo cancellation circuit

122 steady state circuit

124 transient circuit

126 output circuit

130 control circuit

140 frequency generating circuit

150 processing circuit

160 transfer circuit

170 buffer

180D/A converter

500 to 508 steps

C0-C7 Joint coefficient

CLK frequency signal

D2～D_-7Data of

D _ ER Steady-State echo response

D _ ERT echo response adjustment signal

Din digital input signal

Dout output signal

D _ TX digital transmission signal

EC1, EC2, Vc control signals

Period of T0-T9 frequency signal

Vin analog input signal

V _ TX analog transmit signal.

Claims

1. A transceiver circuit, comprising:

an analog-to-digital converter for performing an analog-to-digital conversion operation on an analog input signal to generate a digital input signal; and

an echo cancellation circuit, wherein the echo cancellation circuit comprises:

a steady state circuit for generating a steady state echo response according to a transmission signal;

a transient circuit for generating an echo response adjustment signal generated by a phase change of a frequency signal used by the transmission signal according to the transmission signal; and

an output circuit for generating an output signal according to the digital input signal, the steady state echo response and the echo response adjustment signal, wherein the difference between the steady state echo response and the echo response adjustment signal forms an instantaneous echo response, and the output circuit subtracts the instantaneous echo response from the digital input signal to generate the output signal.

2. The transceiver circuit of claim 1, further comprising:

a processing circuit for determining a mode of the echo response adjustment signal generated due to a phase change of the frequency signal used by the transmission signal based on the output signal.

3. The transceiver circuit of claim 2, wherein the pattern comprises a start point at which the echo response adjustment signal starts to be generated when the phase of the frequency signal used for the transmission signal changes, and a time point at which a first tap coefficient in the echo response adjustment signal returns to zero.

4. The transceiver circuit of claim 2 or 3, wherein the processing circuit generates tap coefficients of a filter in the steady-state circuit for generating the echo response adjusting signal according to the pattern each time the phase of the frequency signal used for the transmission signal changes after the processing circuit determines the pattern of the echo response adjusting signal.

5. The transceiver circuit of claim 1, wherein the transient circuit is turned on to generate the echo response adjustment signal only when a phase of the frequency signal used by the transmission signal changes.

6. The transceiver circuit of claim 1, wherein the adc performs an adc operation on the analog input signal using the frequency signal to generate the digital input signal, and further comprising:

a transmission circuit for generating the transmission signal according to the frequency signal;

a frequency generating circuit for generating the frequency signal to the analog-to-digital converter and the transmitting circuit; and

a control circuit for generating a control signal to the frequency generation circuit to adjust the phase of the frequency signal.

7. The transceiver circuit of claim 6, wherein the transmitter circuit generates a specific data to the echo canceller circuit after the control circuit generates the control signal to the frequency generator circuit to adjust the phase of the frequency signal, so that the transient circuit generates the echo response adjustment signal, and the output circuit generates the output signal accordingly, and the transceiver circuit further comprises:

a processing circuit for determining a mode of the echo response adjustment signal according to the output signal.

8. A signal processing method applied in a transceiver circuit comprises:

performing analog-to-digital conversion operation on an analog input signal to generate a digital input signal;

generating a steady echo response according to a transmission signal;

generating a echo response adjustment signal generated due to the phase change of a frequency signal used by the transmission signal according to the transmission signal; and

and generating an output signal according to the digital input signal, the steady-state echo response and the echo response adjustment signal, wherein the difference between the steady-state echo response and the echo response adjustment signal forms an instantaneous echo response, and the output signal is generated after subtracting the instantaneous echo response from the digital input signal.

9. The signal processing method of claim 8, further comprising:

a mode of the echo response adjustment signal is determined according to the output signal.