CN112652610A - Adapter plate, manufacturing method thereof and electronic equipment - Google Patents
Adapter plate, manufacturing method thereof and electronic equipment Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D21/00—Measuring or testing not otherwise provided for
- G01D21/02—Measuring two or more variables by means not covered by a single other subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses an adapter plate, a manufacturing method thereof and electronic equipment, relates to the technical field of integrated circuit packaging, and aims to reduce the difficulty of obtaining the temperature and stress distribution result of the contact surface of a substrate and a chip, so that the structure and the process of three-dimensional stacking integration can be optimized conveniently according to the distribution result, and the working reliability and the service life of the chip are improved. The keysets includes: a substrate, an interconnect structure, and a temperature sensing element and a stress sensing element formed on a surface of the substrate; the interconnection structure penetrates through the substrate and is electrically connected with the corresponding chip, the temperature sensing element and the stress sensing element on two sides of the substrate; the temperature sensing element is used for measuring the temperature at the contact surface of the substrate and the chip, and the stress sensing element is used for measuring the stress at the contact surface of the substrate and the chip. The interposer is used for realizing vertical interconnection between chips. The adapter plate can be applied to electronic equipment. The invention also provides a manufacturing method of the adapter plate, which is used for manufacturing the adapter plate.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to an adapter plate, a manufacturing method thereof and electronic equipment.
Background
Before three-dimensional stacking integration or packaging, the stress field and the temperature field at the contact surface of the device structure are generally evaluated and analyzed in a theoretical calculation or simulation mode to guide the structure optimization and the process optimization of the three-dimensional stacking integration, prevent the performance of the chip from deviating from the normal working state when the temperature of the chip exceeds the normal working temperature range, prevent the connection welding points at the chip interface from being broken or failed due to the thermal expansion difference of different materials, and improve the working reliability and the service life of the chip.
However, with the development of the three-dimensional stacking integration technology, the internal structure of the chip is very complex, so that it is very difficult to establish a theoretical model of the chip structure and calculate the temperature and stress distribution thereof, and it is difficult to optimize the three-dimensional stacking integration structure and the process according to the distribution result, which finally results in poor working performance of the three-dimensional stacking integration structure.
Disclosure of Invention
The invention aims to provide an adapter plate, a manufacturing method thereof and electronic equipment, which are used for reducing the difficulty of obtaining the temperature and stress distribution result of the contact surface of a substrate and a chip, so that the structure and the process of three-dimensional stacking integration are optimized conveniently according to the distribution result, and the working reliability and the service life of the chip are improved.
To achieve the above object, the present invention provides an interposer for vertical interconnection between chips. This keysets includes: a substrate, an interconnect structure, and a temperature sensing element and a stress sensing element formed on a surface of the substrate;
the interconnection structure penetrates through the substrate and is electrically connected with the corresponding chip, the corresponding temperature sensing element and the corresponding stress sensing element on two sides of the substrate;
the temperature sensing element is used for measuring the temperature at the contact surface of the substrate and the chip, and the stress sensing element is used for measuring the stress at the contact surface of the substrate and the chip.
Compared with the prior art, in the adapter plate provided by the invention, the interconnection structure penetrates through the substrate and can be electrically connected with the corresponding chips on two sides of the substrate, so that the vertical interconnection among the chips is realized. A temperature sensing element and a stress sensing element are formed on the surface of the substrate. The temperature sensing element is capable of measuring the temperature at the interface of the substrate and the chip. The stress sensing element is capable of measuring stress at the interface of the substrate and the chip. That is to say, after a plurality of chips are packaged into a three-dimensional stacked integrated structure through the substrate and the interconnection structure, in the working process of the three-dimensional stacked integrated structure, the temperature sensing element and the stress sensing element can respectively measure the temperature and the stress at the contact surface of the substrate and the chips in real time, and the distribution result of the temperature and the stress at the contact surface is obtained, so that a complex theoretical model of the chip structure does not need to be built, and the difficulty of obtaining the distribution result of the temperature and the stress at the contact surface of the substrate and the chips is reduced without complex theoretical calculation. Meanwhile, compared with the temperature and stress distribution result of the contact surface obtained by means of analog simulation or theoretical calculation in the prior art, the temperature and stress of the contact surface are obtained by means of measurement of the temperature sensing element and the stress sensing element in the adapter plate, the measurement result is consistent with the actual situation, the precision of the temperature and stress distribution result is improved, the three-dimensional stacking integrated structure and process can be effectively optimized according to the distribution result, and the working reliability and service life of a chip are improved. In addition, the vertical interconnection between the chips can be realized by the substrate and the interconnection structure without being influenced by the temperature sensing element and the stress sensing element, so that the integration level of the adapter plate is improved.
The present invention also provides an electronic device, including: at least two chips, and at least one keysets, this keysets is the keysets that above-mentioned technical scheme provided.
Compared with the prior art, the electronic equipment provided by the invention has the same beneficial effects as the adapter plate provided by the technical scheme, and the details are not repeated herein.
The invention also provides a manufacturing method of the adapter plate, wherein the adapter plate is used for realizing vertical interconnection between chips; the manufacturing method of the adapter plate comprises the following steps:
providing a substrate;
forming a temperature sensing element and a stress sensing element on a surface of a substrate; the temperature sensing element is used for measuring the temperature at the contact surface of the substrate and the chip, and the stress sensing element is used for measuring the stress at the contact surface of the substrate and the chip;
forming an interconnection structure; the interconnect structure penetrates the substrate and is electrically connected to the respective chip, the respective temperature sensing element, and the respective stress sensing element on both sides of the substrate.
Compared with the prior art, the beneficial effects of the manufacturing method of the adapter plate provided by the invention are the same as those of the adapter plate provided by the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic cross-sectional view of a structure after forming an N-well region according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a structure after a thermal diode is formed in an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a varistor formed in accordance with an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a structure after forming a via hole in an embodiment of the invention;
FIG. 5 is a cross-sectional view of a structure after forming a first dielectric material layer according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a contact structure after formation in an embodiment of the invention;
FIG. 7 is a cross-sectional view of the structure after forming the second contact hole in the embodiment of the invention;
FIG. 8 is a schematic cross-sectional view of the structure after forming metal interconnect lines and metal leads on the first side of the substrate in an embodiment of the invention;
FIG. 9 is a schematic cross-sectional view of a thinned second side of the substrate in an embodiment of the invention;
FIG. 10 is a cross-sectional view of the second dielectric material layer formed on the second side of the substrate according to the embodiment of the present invention;
FIG. 11 is a cross-sectional view of the structure after forming the first contact hole in the embodiment of the present invention;
fig. 12 is a schematic cross-sectional view of the structure after forming the metal interconnection line on the second side of the substrate in the embodiment of the invention.
Reference numerals:
1 is a substrate, 2 is an interconnection structure, 21 is a contact structure, 22 is a metal interconnection line, 23 is a metal lead, 3 is a temperature sensing element, 31 is a thermal diode, 311 is an N well region, 312 is a P well region, 4 is a stress sensing element, 5 is a through hole, 6 is a first dielectric material layer, 61 is a first dielectric layer, 62 is a third dielectric layer, 63 is a second contact hole, 7 is a second dielectric material layer, 71 is a second dielectric layer, and 72 is a first contact hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In addition, in the present invention, directional terms such as "upper" and "lower" are defined with respect to a schematically placed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may be changed accordingly according to the change of the orientation in which the components are placed in the drawings.
In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.
With the development of integrated circuit technology, the feature size of the integrated circuit is smaller and smaller, and the integration level is higher and higher. Two-dimensional planar microelectronic devices face significant challenges in structural innovation and manufacturing processes. The three-dimensional stacking integration technology provides a new technical route for solving the above-mentioned problems, and a Through Silicon Via (TSV) based Silicon interposer is a key structure for realizing the three-dimensional stacking integration technology. In particular, the three-dimensional stacked integration technology based on the TSV is an integration technology for realizing interconnection of a plurality of chips in a vertical direction through the TSV, is an integration solution most expected to realize the strategy of "beyond mole" (More than Moore) and is one of research hotspots in the field of advanced packaging. The TSV silicon-based adapter plate can bear and connect a plurality of homogeneous or heterogeneous chips, the capacity expansion of the same type of chips or the high-density stacking integration of the chips with multiple functions is realized, the limitation of plane integration is broken through, the interconnection length between the chips is obviously shortened, the power consumption lost on interconnection lines is further reduced, and the integration level and the performance of the chips can be greatly improved.
However, with the development of three-dimensional stacked integration technology, the transistor density and integration level in the chip are increasing. Accordingly, the amount of heat generated per unit area of the chip is also rapidly increased, that is, the heat current density is rapidly increased, so that the temperature of the chip is increased, thereby causing a change in the transport performance of carriers inside the chip in the channel. When the temperature at the channel exceeds its normal operating temperature range, the performance of the chip may deviate from the normal operating state, even causing the chip to fail. Especially for high power, high frequency devices, the problem of heat generation is even greater. In addition, in case of the temperature rise of the chip, the stress concentration inside the chip can be caused by the thermal expansion difference of different materials. The increase of the stress easily causes the fracture or failure of the connection welding point at the chip interface, thereby affecting the reliability and the service life of the chip. Based on this, before stacking integration or packaging, effective evaluation and analysis of stress fields and temperature fields at the contact surfaces of the device structures are needed to guide the structure optimization and process optimization of three-dimensional stacking integration.
Existing methods for evaluating stress and temperature fields at the interface are typically implemented by theoretical calculations or simulation. However, with the development of three-dimensional stacking integration technology, the internal structure of the chip is very complex, so that it is very difficult to calculate the temperature and stress distribution by establishing a theoretical model of the chip structure. In addition, the precision of the stress and temperature distribution results obtained through simulation is poor, that is, the temperature field and the stress field which are consistent with the actual situation cannot be obtained, so that the optimization effect of the three-dimensional stacking integrated structure and process according to the distribution results is poor, and finally the working performance of the three-dimensional stacking integrated structure is poor.
In order to solve the above technical problems, embodiments of the present invention provide an interposer, a manufacturing method thereof, and an electronic device. In the interposer provided by the embodiment of the present invention, the temperature sensing element and the stress sensing element are formed on the surface of the substrate. The temperature sensing element and the stress sensing element can respectively obtain the temperature and the stress at the contact surface of the substrate and the chip in a measuring mode, so that the difficulty of obtaining the temperature and stress distribution result at the contact surface is reduced.
Referring to fig. 12, an embodiment of the present invention provides an interposer for implementing vertical interconnection between chips. The adapter plate can be any adapter plate capable of realizing vertical interconnection between chips, such as a silicon-based adapter plate, a germanium-based adapter plate or a germanium-silicon-based adapter plate. And the chip can be any chip to be integrated by three-dimensional stacking.
Referring to fig. 12, the interposer includes: a substrate 1, an interconnect structure 2, and a temperature sensing element 3 and a stress sensing element 4 formed on a surface of the substrate 1. It should be understood that the surface of the substrate 1 may be such that the temperature sensing element 3 and the stress sensing element 4 are located within the substrate 1 and the tops of both are flush with the surface of the substrate 1. Alternatively, the temperature sensing element 3 and the stress sensing element 4 may be located on the surface of the substrate 1.
Specifically, the material and structure of the substrate may be selected according to the type of the interposer. For example: when the adapter plate is a silicon-based adapter plate, the substrate is a silicon substrate.
Referring to fig. 12, the above-described interconnect structures 2 penetrate the substrate 1 and are electrically connected to the respective chips, the respective temperature sensing elements 3, and the respective stress sensing elements 4 on both sides of the substrate 1.
Specifically, the specific structure of the interconnection structure may be set according to an actual application scenario, as long as the interconnection structure can be applied to the interposer provided in the embodiment of the present invention. Illustratively, referring to fig. 12, the interconnect structure 2 may include: contact structures 21, metal interconnect lines 22, and metal leads 23. The contact structures 21 penetrate the substrate 1 along the thickness direction of the substrate 1, and are electrically connected with the corresponding metal interconnection lines 22. Metal interconnection lines 22 are laid on both sides of the substrate 1. The metal leads 23 are disposed on one side or both sides of the substrate 1 and electrically connected to the corresponding temperature sensing elements 3 or the corresponding stress sensing elements 4.
The number of the contact structures and the metal interconnection lines and the arrangement positions of the contact structures and the metal interconnection lines on the substrate can be arranged according to the structure of the chip. For the metal lead, the metal lead is used for leading out two electrodes of the temperature sensing element and the stress sensing element, so the number and the arrangement position of the metal lead can be arranged according to the number and the arrangement position of the temperature sensing element and the stress sensing element, and are not limited specifically here. As for the materials of the contact structure, the metal interconnection line and the metal lead, the materials contained in the contact structure, the metal interconnection line and the metal lead are conductive materials. Specifically, the conductive material may be one or more of titanium, titanium nitride, tungsten, aluminum, copper, and gold.
Referring to fig. 12, the temperature sensing element 3 is used to measure the temperature at the interface of the substrate 1 and the chip, and the stress sensing element 4 is used to measure the stress at the interface of the substrate 1 and the chip.
For example, the temperature sensing element and the stress sensing element may be formed on one side or both sides of the substrate and the chip interconnection, and they are spaced apart from each other. For example: the temperature sensing element and the stress sensing element may be formed on a front side of the substrate when the chip is positioned over the substrate. When the chip is located under the substrate, the temperature sensing element and the stress sensing element may be formed on the back surface side of the substrate. And when the chips are interconnected on both sides of the substrate, the temperature sensing element and the stress sensing element may be formed on the front and rear surfaces of the substrate.
Specifically, the arrangement positions of the temperature sensing elements and the stress sensing elements on one side or both sides of the substrate, and the arrangement number of the temperature sensing elements and the stress sensing elements can be set according to actual requirements. For example: referring to fig. 12, in the case where the interconnect structure 2 includes metal leads 23, when there are a plurality of temperature test points and a plurality of stress test points at the contact surface of the substrate 1 and the chip, the interposer may include a plurality of temperature sensing elements 3 and a plurality of stress sensing elements 4. The metal lead 23 is electrically connected to the corresponding temperature sensing element 3 at each temperature measurement point. The metal leads 23 are electrically connected to the corresponding stress sensing element 4 at each stress point to be measured. When one metal lead wire 23 is electrically connected to one temperature sensing element 3 at a temperature point to be measured, the metal lead wire 23 corresponds to the temperature point to be measured and the temperature sensing element 3, respectively. Similarly, when one metal lead 23 is electrically connected to one stress sensing element 4 at one stress point to be measured, the metal lead 23 corresponds to the stress point to be measured and the stress sensing element 4, respectively.
Referring to fig. 12, the temperature sensing element 3 may be any one of a thermal diode 31 or a thermistor (not shown) formed on the surface of the substrate 1, which can measure the temperature at the contact surface of the substrate 1 and the chip. As for the stress sensing element 4, it may be any one of piezoelectric structures or piezoresistors formed on the surface of the substrate 1 that can measure the stress at the above-mentioned contact surface.
In the practical application process, after a plurality of chips are packaged into a three-dimensional stacking integrated structure through a substrate and an interconnection structure, in the working process of the three-dimensional stacking integrated structure, two ends of a thermal diode have different potential differences under the action of different temperatures. And the thermistor shows different resistance values under different temperature actions. In this case, the temperature distribution result at the contact surface can be obtained by measuring the potential difference between both ends of the thermistor diode, or the resistance value at the thermistor. In addition, the piezoelectric structure generates different potential differences at two opposite ends under the action of different tensile or compressive stresses. And the piezoresistors show different resistance values under different tensile or compressive stresses. In this case, the stress distribution result at the above-mentioned contact surface can be obtained by measuring the potential difference across the piezoelectric structure, or the resistance value at the varistor.
From the above, the temperature sensing element and the stress sensing element can respectively measure the temperature and the stress at the contact surface of the substrate and the chip in real time to obtain the distribution result of the temperature and the stress at the contact surface, without constructing a complex theoretical model of the chip structure and without performing complex theoretical calculation, thereby reducing the difficulty of obtaining the distribution result of the temperature and the stress at the contact surface of the substrate and the chip. Meanwhile, compared with the temperature and stress distribution result of the contact surface obtained by means of analog simulation or theoretical calculation in the prior art, the temperature and stress of the contact surface are obtained by means of measurement of the temperature sensing element and the stress sensing element in the adapter plate, the measurement result is consistent with the actual situation, the precision of the temperature and stress distribution result is improved, the three-dimensional stacking integrated structure and process can be effectively optimized according to the distribution result, and the working reliability and service life of a chip are improved. In addition, the vertical interconnection between the chips can be realized by the substrate and the interconnection structure without being influenced by the temperature sensing element and the stress sensing element, so that the integration level of the adapter plate is improved.
In one example, referring to fig. 12, as previously described, in the case where the interconnect structure 2 includes the contact structure 21, the metal interconnect line 22, and the metal lead 23, the interposer may further include a first dielectric layer 61, a second dielectric layer 71, and a third dielectric layer 62.
Referring to fig. 12, the first dielectric layer 61 is formed on the first side of the substrate 1. A second dielectric layer 71 is formed on the second side of the substrate 1. The contact structures 21 are electrically connected to the respective metal interconnection lines 22 through the first dielectric layer 61 and the second dielectric layer 71. The metal leads 23 are electrically connected to the respective temperature sensing elements 3 or the respective stress sensing elements 4 through the first dielectric layer 61 and/or the second dielectric layer 71. A third dielectric layer 62 is formed between the contact structure 21 and the substrate 1 along the circumferential direction of the contact structure 21. It will be appreciated that the presence of the first and second dielectric layers 61, 71 may ensure that the metal interconnects 22 and the metal leads 23 may be electrically connected only to the respective contact structures 21, the respective temperature sensing elements 3 and the respective stress sensing elements 4, respectively, improving the operational stability and the degree of integration of the interposer. In addition, the contact structure 21, the metal interconnection line 22, and the metal lead 23 are made of a conductive material having relatively active ions. The first dielectric layer 61 and the second dielectric layer 71 can isolate the metal interconnection line 22 and the metal lead 23 from the substrate 1, so that active ions in the metal interconnection line 22 and the metal lead 23 are prevented from diffusing into the substrate 1 when the three-dimensional stacked integrated structure works, and the three-dimensional stacked integrated structure is ensured to have good working performance. Likewise, the third dielectric layer 62 may isolate the contact structure 21 from the substrate 1. The function of the third dielectric layer 62 can refer to the functions of the first dielectric layer 61 and the second dielectric layer 71, and will not be described herein.
Specifically, the first side of the substrate may be a front side of the substrate, or may be a back side of the substrate. The second side of the substrate is a side opposite the first side of the substrate. For example: the first side of the substrate is the front side of the substrate, and the second side of the substrate is the back side of the substrate. Another example is: the first side of the substrate is the back side of the substrate, and the second side of the substrate is the front side of the substrate.
In addition, the thicknesses of the first dielectric layer, the second dielectric layer and the third dielectric layer can be set according to actual requirements. The materials contained in the three are insulating materials. The insulating material can be high-K material such as silicon oxide, silicon nitride, aluminum oxide and the like.
The embodiment of the invention also provides a manufacturing method of the adapter plate. Wherein the manufactured interposer is used to realize vertical interconnection between chips. The adapter plate may be the adapter plate provided in the above embodiments. The manufacturing process will be described below with reference to the cross-sectional views of the operation shown in fig. 1 to 12. Specifically, the manufacturing method of the adapter plate comprises the following steps:
first, a substrate is provided. Specifically, the material and structure of the substrate can be referred to above, and are not described herein again.
Referring to fig. 1 and 2, a temperature sensing element 3 is formed on a surface of a substrate 1. The temperature sensing element 3 is used to measure the temperature at the interface of the substrate 1 and the chip. Specifically, the position of the temperature sensing element 3 on the substrate 1 can be referred to above. It should be understood that the surface of the substrate 1 may be such that the temperature sensing element 3 is located within the substrate 1 and the top of the temperature sensing element 3 is flush with the surface of the substrate 1. Alternatively, the temperature sensing element 3 may be located on the surface of the substrate 1.
Illustratively, a first mask pattern is formed on a surface of one or both sides of the substrate and chip interconnections. For example: when the temperature sensing element is disposed on the front surface side of the substrate, a first mask pattern may be formed on the front surface of the substrate. The region of the substrate exposed outside the first mask pattern is a region where the temperature sensing element is subsequently formed. The material of the first mask pattern may be set according to a manner of subsequently forming the temperature sensing element. Specifically, when the diffusion method is adopted, the material of the first mask pattern may be silicon oxide, silicon nitride, or the like. When the ion implantation is used, the first mask pattern may be made of photoresist or the like.
And forming a temperature sensing element on the surface of the substrate by diffusion or ion implantation under the mask of the first mask pattern. Specifically, the type and concentration of the diffusion or ion implantation impurities, the temperature during diffusion, the ion implantation energy, and the like can be set according to practical application scenarios. For example: when the temperature sensing element is a thermistor and the thermistor is formed by ion implantation, the ion implanted impurity may be B, BF2P or As. The concentration of the impurities may be 1e 14-1 e 16. The energy of the ion implantation may be 100KeV to 150 KeV. Example ofSuch as: when the temperature sensing element is a thermistor and the thermistor is formed by diffusion, the diffused impurities may be Mn, Au, Pt, or the like.
Another example is: when the temperature sensing element is a thermal diode, referring to fig. 1, an N well region 311 may be formed on the surface of the substrate 1 by ion implantation under the action of a mask pattern (not shown). Referring to fig. 2, a mask pattern is formed again, and a P-well region 312 is formed on one side of the N-well region 311 by ion implantation under the action of the formed mask pattern, so as to obtain the thermal diode 31.
For example, in a case where the temperature sensing element is formed on the surface of the substrate by ion implantation, after the temperature sensing element is formed on the surface of the substrate, the method for manufacturing the interposer may further include: the temperature sensing element is subjected to a first annealing process. In this case, the first annealing treatment is performed on the temperature sensing element to activate the impurities injected into the substrate, repair the damage to the substrate caused by the ion injection, and improve the working performance of the interposer. The temperature and time of the first annealing treatment can be set according to actual application scenarios. For example: the temperature of the first annealing treatment may be 950 ℃, and the time may be 30 min.
Referring to fig. 3, a stress sensing element 4 is formed on a surface of a substrate 1. The stress sensing element 4 is used to measure the stress at the interface of the substrate 1 and the chip. In particular, reference may be made to the above description for the location of the stress-sensing element 4 on the substrate 1. It should be understood that the surface of the substrate 1 may be such that the stress sensing element 4 is located within the substrate 1 and the top of the stress sensing element 4 is flush with the surface of the substrate 1. Alternatively, the stress sensing element 4 may be located on the surface of the substrate 1.
For example, when the stress sensing element is a varistor, forming the stress sensing element on the surface of the substrate may include: a second mask pattern is formed on a surface of one or both sides of the substrate and the chip interconnection. For example: when the stress sensing element is disposed on the front surface side of the substrate, a second mask pattern may be formed on the front surface of the substrate. The region of the substrate exposed outside the second mask pattern is a region where the stress sensing element is subsequently formed. The material of the second mask pattern may be set with reference to the material of the first mask pattern.
And then, under the mask of the second mask pattern, forming a stress sensing element on the surface of the substrate by adopting a diffusion or ion implantation mode. Specifically, the type and concentration of the diffusion or ion implantation impurities, the temperature during diffusion, the ion implantation energy, and the like can be set according to practical application scenarios. For example: when the stress sensing element is a piezoresistor and the piezoresistor is formed by ion implantation, the ion implanted impurity can be B or BF2. And the piezoresistor can be formed by four times of ion implantation. Specifically, taking B as an example of the impurity, the concentration of the first ion implantation may be 1e12, and the energy of the first ion implantation may be 400 KeV. The concentration of the second ion implantation may be 1e12, and the energy of the second ion implantation may be 300 KeV. The concentration of the third ion implantation may be 1.6e14, and the energy of the third ion implantation may be 200 KeV. The concentration of the fourth ion implantation may be 8e13, and the energy of the fourth ion implantation may be 100 KeV.
For example, in a case where the stress sensing element is formed on the surface of the substrate by ion implantation, after the stress sensing element is formed on the surface of the substrate, the method for manufacturing the interposer may further include: and carrying out second annealing treatment on the stress sensing element. Specifically, the effect of the second annealing treatment may refer to the effect of the first annealing treatment. The temperature and time of the second annealing treatment can be set according to actual application scenarios. For example: the temperature of the second annealing treatment may be 1050 deg.c and the time may be 30 s.
For example, when the stress sensing element is a piezoelectric structure, forming the stress sensing element on the surface of the substrate may include: a layer of piezoelectric material is formed on one or both surfaces of the substrate and chip interconnect. For example: when the stress sensing element is disposed on the front side of the substrate, a piezoelectric material layer, such as AlN or PZT, may be deposited on the front side of the substrate by using a chemical vapor deposition or physical vapor deposition process. Specifically, the thickness of the piezoelectric material layer may be set according to a practical application scenario, and is not specifically limited herein. And etching the piezoelectric material layer to obtain the stress sensing element. For example: the stress sensing element can be obtained by etching the piezoelectric material layer at a part where the stress sensing element is not required to be formed by means of photoetching and etching.
In the foregoing, the temperature sensing element is formed on the surface of the substrate, and then the stress sensing element is formed on the surface of the substrate. Of course, the stress sensing element may be formed on the surface of the substrate, and then the temperature sensing element may be formed on the surface of the substrate. Specifically, the forming sequence of the temperature sensing element and the stress sensing element may be set according to an actual application scenario, and is not limited specifically here.
Referring to fig. 4 to 12, an interconnect structure 2 is formed. The interconnect structures 2 extend through the substrate 1 and are electrically connected to respective chips, respective temperature sensing elements 3 and respective stress sensing elements 4 on both sides of the substrate 1. Specifically, the detailed structure of the interconnect structure 2 and the materials contained therein can be referred to the above, and are not described herein again.
In one example, as described above, in the case where the interconnect structure includes the contact structure, the metal interconnect line, and the metal lead 23, and the interposer further includes the first dielectric layer 61, the second dielectric layer 71, and the third dielectric layer 62, the above-described forming of the interconnect structure may include the steps of:
referring to fig. 4, a through-hole 5 is opened in the substrate 1 along the thickness direction of the substrate 1. Illustratively, a mask pattern may be first formed on one side of the substrate 1. And under the action of the mask pattern, through holes 5 are formed in the substrate 1 through a wet etching or dry etching process. The size, number and location of the through holes 5 can be set according to the relevant parameters of the contact structure 21. For example: the diameter of the through hole 5 may be 1 to 500 μm. The depth of the through holes 5 may be 10 to 600 μm.
Referring to fig. 5, a first layer of dielectric material 6 is formed covering the first side of the substrate 1, as well as the walls of the through-holes 5. Illustratively, the first dielectric material layer 6 may be formed by chemical vapor deposition or physical vapor deposition. Specifically, the layer thickness and material of the first dielectric material layer 6 may be set with reference to the first dielectric layer 61 and the third dielectric layer 62. In addition, reference may be made to the foregoing for the first side of the substrate 1, which is specifically referred to as the side of the substrate 1, and details are not repeated herein.
Referring to fig. 6, a contact structure 21 is formed within the via hole 5, and a portion of the first dielectric material layer 6 formed within the via hole 5 is located between the substrate 1 and the contact structure 21. Illustratively, the conductive material may be formed within the via 5 and on the first side of the substrate 1 by chemical vapor deposition or physical vapor deposition, or the like. The part of the conductive material on the first side of the substrate 1 is then removed by means of a chemical-mechanical polishing process, resulting in the above-mentioned contact structure 21. Specifically, reference is made to the above for the material of the contact structure 21.
In one example, in the case where the temperature sensing element and the stress sensing element are located on the first side of the substrate, after the contact structure is formed, before subsequent operations are performed, referring to fig. 7, a second patterning process is also performed on the portion of the first dielectric material layer 6 located on the first side of the substrate 1 to form a second contact hole 63 penetrating through the first dielectric material layer 6. The second contact hole 63 is formed at the opposite region of the first dielectric material layer 6 to the temperature sensing element 3 and the stress sensing element 4, so as to form the metal lead 23 electrically connected to the temperature sensing element 3 and the stress sensing element 4, respectively, later.
Specifically, the second patterning process may be performed on a portion of the first dielectric material layer on the first side of the substrate by using photolithography and etching.
Referring to fig. 8, metal interconnection lines 22 are formed on a first side of the substrate 1. The metal interconnection lines 22 are electrically connected with the respective contact structures 21. For example, the conductive material may be formed on the first dielectric material layer 6 by chemical vapor deposition or physical vapor deposition. Then, using a photolithography process, portions of the conductive material not required to form the metal interconnection lines 22 are selectively removed. The remaining conductive material forms metal interconnect lines 22.
In one example, in the case where the temperature sensing element and the stress sensing element are located at the first side of the substrate, referring to fig. 8, it is also necessary to form the metal wiring 23 at least in the second contact hole 63. The metal lead 23 is electrically connected to the temperature sensing element 3 or the corresponding stress sensing element 4. On a first side of the substrate 1, the metal leads 23 protrude from the substrate 1. Specifically, the size of the portion of the metal lead 23 protruding from the substrate 1 may be set according to actual requirements, and is not limited herein.
It should be noted that, in the case where the metal interconnection line and the metal lead are formed on the first side of the substrate, the metal interconnection line and the metal lead may be formed simultaneously, so that the manufacturing process of the interposer is more simplified. Of course, the metal interconnection lines and the metal leads may also be formed on the first side of the substrate in different steps. Specifically, the forming sequence of the metal interconnection lines and the metal leads can be set according to the actual application scenario.
Referring to fig. 9, the second side of the substrate 1 is thinned to expose the contact structure 21.
For example, a carrier wafer may be temporarily bonded to the first side of the substrate by the temporary bonding adhesive, so as to prevent the structure formed on the first side of the substrate from being damaged during the subsequent thinning process of the second side of the substrate, and improve the yield of the interposer. The second side of the substrate may then be thinned by a chemical mechanical polishing process to expose an end portion of the contact structure proximate the second side of the substrate.
It should be noted that in the case where the temperature sensing element and the stress sensing element are located on the first side of the substrate, referring to fig. 9, after the thinning process is performed on the second side of the substrate 1, the remaining first dielectric material layer 6 forms a first dielectric layer 61 and a third dielectric layer 62. The first dielectric layer 61 is formed on the first side of the substrate 1. A third dielectric layer 62 is formed between the contact structure 21 and the substrate 1 along the circumferential direction of the contact structure 21.
Referring to fig. 10, a second layer of dielectric material 7 is formed overlying the second side of the substrate 1. Illustratively, the second dielectric material layer 7 may be formed on the second side of the substrate 1 by chemical vapor deposition or physical vapor deposition, or the like. Specifically, the thickness and material of the second dielectric material layer 7 can be set by referring to the thickness and material of the second dielectric layer 71 described above.
Referring to fig. 11, the second dielectric material layer 7 is subjected to a first patterning process to form a first contact hole 72 penetrating the second dielectric material layer 7. The first contact hole 72 is formed in the region of the second dielectric material layer 7 opposite to the contact structure 21. For example, the second dielectric material layer 7 may be subjected to a first patterning process by using a photolithography and etching process, and a portion of the second dielectric material layer 7 corresponding to the contact structure 21 is removed to expose an end portion of the contact structure 21 close to the second side of the substrate 1.
Referring to fig. 12, the metal interconnection line 22 is formed at least within the first contact hole 72. The above-mentioned metal interconnection lines 22 are electrically connected to the respective contact structures 21. On the second side of the substrate 1, the metal interconnection lines 22 protrude from the substrate 1. Specifically, the operation of forming the metal interconnection line 22 on the second side of the substrate 1 may refer to the operation of forming the metal interconnection line 22 on the first side of the substrate 1. In addition, the size of the portion of the metal interconnection line 22 protruding from the substrate 1 may be set according to actual requirements, and is not specifically limited herein.
In one example, where the temperature sensing element and the stress sensing element are located on the second side of the substrate, after forming the second layer of dielectric material overlying the second side of the substrate, forming the interconnect structure may further comprise:
and carrying out third patterning treatment on the second dielectric material layer to form a third contact hole. The bottom of the third contact hole is in contact with the corresponding temperature sensing element or the corresponding stress sensing element. The remaining second dielectric material layer forms a second dielectric layer. Specifically, the third patterning process performed on the second dielectric material layer may be performed simultaneously with, before, or after the first patterning process performed on the second dielectric material layer, and the operation sequence of the first patterning process and the third patterning process may be set according to actual requirements.
Then, metal leads are formed at least in the third contact holes. The metal leads are electrically connected with the corresponding temperature sensing elements or the corresponding stress sensing elements; the metal leads protrude from the substrate on a second side of the substrate. Specifically, the operation of forming the metal leads on the second side of the substrate may be performed simultaneously with, before or after the operation of forming the metal interconnection lines on the second side of the substrate, and the operation sequence of the metal leads and the metal interconnection lines on the second side of the substrate may be set according to actual requirements.
Compared with the prior art, the beneficial effects of the manufacturing method of the adapter plate provided by the embodiment of the invention are the same as those of the adapter plate provided by the embodiment, and the details are not repeated here.
An embodiment of the present invention further provides an electronic device, including: at least two chips, and at least one keyset, this keyset is the keyset that the embodiment provided above provided.
Compared with the prior art, the electronic equipment provided by the embodiment of the invention has the same beneficial effects as the adapter plate provided by the embodiment, and the details are not repeated here.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (12)
1. The adapter plate is characterized in that the adapter plate is used for realizing vertical interconnection between chips; the keysets includes: a substrate, an interconnect structure, and a temperature sensing element and a stress sensing element formed on a surface of the substrate;
the interconnection structure penetrates through the substrate and is electrically connected with the corresponding chip, the corresponding temperature sensing element and the corresponding stress sensing element on two sides of the substrate;
the temperature sensing element is used for measuring the temperature at the contact surface of the substrate and the chip, and the stress sensing element is used for measuring the stress at the contact surface of the substrate and the chip.
2. The interposer as recited in claim 1, wherein the temperature sensing element is a thermal diode or a thermal resistor formed on the substrate surface; and/or the presence of a gas in the gas,
the stress sensing element is a piezoelectric structure or a piezoresistor formed on the surface of the substrate.
3. The interposer as recited in claim 1 or 2, wherein the interconnect structure comprises: a contact structure, a metal interconnect, and a metal lead;
the contact structure penetrates through the substrate along the thickness direction of the substrate and is electrically connected with the corresponding metal interconnection line; the metal interconnection lines are arranged on two sides of the substrate;
the metal leads are arranged on one side or two sides of the substrate and are electrically connected with the corresponding temperature sensing elements or the corresponding stress sensing elements.
4. The interposer as recited in claim 3, wherein the substrate has a plurality of temperature test points and a plurality of stress test points at the contact surface with the chip;
the adapter plate comprises a plurality of temperature sensing elements and a plurality of stress sensing elements; the metal lead is electrically connected with the corresponding temperature sensing element at each temperature point to be measured; the metal lead is electrically connected with the corresponding stress sensing element at each stress point to be tested.
5. The interposer as recited in claim 3, further comprising a first dielectric layer, a second dielectric layer, and a third dielectric layer; wherein the content of the first and second substances,
the first dielectric layer is formed on the first side of the substrate, the second dielectric layer is formed on the second side of the substrate, and the contact structure penetrates through the first dielectric layer and the second dielectric layer and is electrically connected with the corresponding metal interconnection line; the metal leads penetrate through the first dielectric layer and/or the second dielectric layer and are electrically connected with the corresponding temperature sensing elements or the corresponding stress sensing elements;
the third dielectric layer is formed between the contact structure and the substrate in a circumferential direction of the contact structure.
6. An electronic device, comprising: at least two chips, and at least one interposer as claimed in any one of claims 1 to 5.
7. The manufacturing approach of a keyset, characterized by, the said keyset is used for realizing the vertical interconnection among the chips; the manufacturing method of the adapter plate comprises the following steps:
providing a substrate;
forming a temperature sensing element and a stress sensing element on a surface of the substrate; the temperature sensing element is used for measuring the temperature at the contact surface of the substrate and the chip, and the stress sensing element is used for measuring the stress at the contact surface of the substrate and the chip;
forming an interconnection structure; the interconnect structure penetrates the substrate and is electrically connected to the corresponding chip, the corresponding temperature sensing element, and the corresponding stress sensing element on both sides of the substrate.
8. The method of manufacturing an interposer as recited in claim 7, wherein forming the temperature sensing element on the surface of the substrate comprises:
forming a first mask pattern on a surface of one or both sides of the substrate and the chip interconnection;
forming the temperature sensing element on the surface of the substrate by adopting a diffusion or ion implantation mode under the mask of the first mask pattern; and/or the presence of a gas in the gas,
in a case where the temperature sensing element is formed on the surface of the substrate by ion implantation, after the temperature sensing element is formed on the surface of the substrate, the method for manufacturing the interposer further includes:
and carrying out first annealing treatment on the temperature sensing element.
9. The interposer as recited in claim 7, wherein the stress sensing element is a varistor;
forming the stress sensing element on the surface of the substrate, including:
forming a second mask pattern on a surface of one or both sides of the substrate and the chip interconnection;
forming the stress sensing element on the surface of the substrate by adopting a diffusion or ion implantation mode under the mask of the second mask pattern; and/or the presence of a gas in the gas,
in a case where the stress sensing element is formed on the surface of the substrate by ion implantation, after the stress sensing element is formed on the surface of the substrate, the method for manufacturing the interposer further includes:
and carrying out second annealing treatment on the stress sensing element.
10. The interposer as recited in claim 7, wherein the stress sensing element is a piezoelectric structure;
forming the stress sensing element on the surface of the substrate, including:
forming a piezoelectric material layer on the surface of one side or two sides of the substrate and the chip interconnection;
and etching the piezoelectric material layer to obtain the stress sensing element.
11. The method of manufacturing an interposer as claimed in any one of claims 7 to 10, wherein the forming an interconnect structure comprises:
forming a through hole in the substrate along the thickness direction of the substrate;
forming a first dielectric material layer covering the first side of the substrate and the hole wall of the through hole;
forming a contact structure in the through hole, wherein the part of the first dielectric material layer formed in the through hole is positioned between the substrate and the contact structure;
forming a metal interconnect line on a first side of the substrate; the metal interconnection lines are electrically connected with the corresponding contact structures;
thinning the second side of the substrate to expose the contact structure; and forming a second layer of dielectric material overlying the second side of the substrate;
carrying out first patterning treatment on the second dielectric material layer to form a first contact hole penetrating through the second dielectric material layer; the first contact hole is formed at the opposite area of the second dielectric material layer and the contact structure;
forming a metal interconnection line at least in the first contact hole; the metal interconnection lines are electrically connected with the corresponding contact structures; and on the second side of the substrate, the metal interconnection line protrudes out of the substrate.
12. The method of claim 11, wherein after forming the contact structure in the via, forming the interconnect structure further comprises:
performing second patterning on the part, located on the first side of the substrate, of the first dielectric material layer to form a second contact hole penetrating through the first dielectric material layer; the second contact hole is formed in the opposite area of the first dielectric material layer and the temperature sensing element and the stress sensing element;
forming a metal lead at least in the second contact hole; the metal lead is electrically connected with the temperature sensing element or the corresponding stress sensing element; on the first side of the substrate, the metal lead protrudes out of the substrate;
after the second side of the substrate is thinned, the remaining first dielectric material layer forms a first dielectric layer and a third dielectric layer; the first dielectric layer is formed on a first side of the substrate; the third dielectric layer is formed between the contact structure and the substrate along the circumferential direction of the contact structure; and/or the presence of a gas in the gas,
after the forming a second layer of dielectric material overlying the second side of the substrate, the forming an interconnect structure further comprises:
carrying out third patterning treatment on the second dielectric material layer to form a third contact hole; forming a second dielectric layer by the remaining second dielectric material layer;
forming a metal lead at least in the third contact hole; the metal leads are electrically connected with the corresponding temperature sensing elements or the corresponding stress sensing elements; and on the second side of the substrate, the metal lead protrudes out of the substrate.
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| CN113438799A (en) * | 2021-06-28 | 2021-09-24 | 海光信息技术股份有限公司 | Aging circuit board, aging test structure and aging test method |
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| CN113438799A (en) * | 2021-06-28 | 2021-09-24 | 海光信息技术股份有限公司 | Aging circuit board, aging test structure and aging test method |
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