JP2010087273A - Electronic device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic device and a method for manufacturing the same, wherein an optimum alignment position is directly detected. <P>SOLUTION: The electronic device 100 includes a first substrate Wf1 and a second substrate Wf2 mounted with the first substrate Wf1 and electrically connected to the first substrate Wf1 in at least one predetermined area. The predetermined area includes at least two through vias 110 penetrating the first substrate Wf1 and wiring 213 provided in the second substrate Wf2, and at least two through vias 110 have at least one connection pair electrically connected through the wiring 213. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic device such as a semiconductor device and a manufacturing method thereof, and more particularly to a three-dimensional electronic device configured by stacking a plurality of semiconductor devices and the like and a manufacturing method thereof.

  In recent years, high integration and high functionality of semiconductor integrated circuits are required, and miniaturization and thinning are also required. In order to satisfy such a requirement, a three-dimensional semiconductor device with an increased semiconductor mounting density has been proposed. The three-dimensional semiconductor device is a technology that realizes high-density mounting by stacking and connecting a plurality of semiconductor chips and elements.

  Here, when a plurality of semiconductor chips are stacked, the following alignment method is generally employed. That is, positioning is performed by optically recognizing the position of a terminal (through electrode) formed on the underlying semiconductor chip. Subsequently, the positions of the stacked semiconductor chips (that is, the upper ones) are similarly recognized and positioned to join the two semiconductor chips.

  However, in this method, it is not possible to recognize a positional shift that occurs when joining. Therefore, if they are actually misaligned and joined, electrical connection between the two semiconductor chips cannot be made. Thus, it has a disadvantage that leads to a decrease in yield.

  Therefore, an alignment method as shown in Patent Document 1 has been proposed. Hereinafter, with reference to FIG. 13, a description will be given of an alignment technique in which the positional deviation in the bonding of the semiconductor chips is reduced.

  According to the method of Patent Document 1, as shown in FIG. 13, the through electrode 10 a is formed in the mounting region of the semiconductor chip on the substrate 1, and the same structure as the through electrode 10 a is formed in the non mounting region of the semiconductor chip on the substrate 1. An alignment mark 20a is formed.

Subsequently, the through electrode 15 is formed in a position corresponding to the through electrode 10 a in the substrate 1 in the semiconductor chip 30 to be stacked (upward). In this way, the alignment of each semiconductor chip stacked on the substrate 1 can be performed using the same reference (alignment mark 20a), and the position can be accurately controlled.
JP 2005-175263 A

  However, although this method seems to improve the position accuracy, this method is also an indirect alignment method. Therefore, it is not known whether the optimum alignment position is actually taken.

  In the future, it is expected that further downsizing and thinning will be required as higher integration and higher functionality of semiconductor integrated circuits are required. For this reason, it is necessary to further miniaturize and increase the density of a plurality of semiconductor chips and elements used in the three-dimensional semiconductor device, and it is assumed that the through electrode is also reduced. Both the conventional method and the method shown in Patent Document 1 are indirect alignment methods, and there is a limit to miniaturization.

  In addition, since the technique of Patent Document 1 is to form alignment marks on a substrate and to arrange chips in accordance with the alignment marks, it can cope with stacking chips on a wafer. Cannot support lamination.

  In view of the above, in the three-dimensional semiconductor device and the manufacturing method thereof, the present invention can improve the positional accuracy by directly detecting the alignment position, and can also be applied to wafer-to-wafer, chip-to-chip stacking. For the purpose.

  In order to achieve the above object, a first electronic device according to the present invention includes a first substrate, a second substrate mounted with the first substrate, and electrically connected to the first substrate in at least one predetermined region. And the predetermined region includes at least one pair of through vias penetrating the first substrate and wiring provided in the second substrate, and the at least one pair of through vias are electrically connected via the wiring. It has at least one connection pair connected.

  Since the first electronic device of the present invention is laminated by directly measuring the alignment between the first substrate and the second substrate as will be described later, the electronic device is more accurate and more reliable than the conventional one. It has become.

  As a more specific form of the first electronic device, at least two conductive portions are formed in the uppermost layer of the first substrate, and each of the at least two through vias is each of at least two conductive portions. May be electrically connected separately.

  As a more specific form of the first electronic device, at least two through vias may be formed in the outer peripheral portion in the predetermined region.

  A plurality of connection pairs may exist. By setting it as such a form, it becomes a more accurate and reliable electronic device.

  The second electronic device of the present invention includes a first substrate and a second substrate on which the first substrate is mounted and electrically connected to the first substrate in at least one predetermined region. And a first through via penetrating the first substrate and a second through via penetrating the second substrate, wherein the first through via and the second through via are electrically connected. Have a pair.

  Since the second electronic device of the present invention is laminated by directly measuring the alignment between the first substrate and the second substrate as will be described later, the electronic device is more accurate and more reliable than the conventional one. It has become.

  As a more specific form of the second electronic device, the first conductive portion is provided on the uppermost layer of the first substrate, the second conductive portion is provided on the uppermost layer of the second substrate, and the first conductive portion is provided. The first through via, the second conductive portion, and the second through via may be electrically connected.

  As a more specific form of the second electronic device, the first through via and the second through via may be formed on the outer peripheral portion in the predetermined region.

  A plurality of connection pairs may exist. By setting it as such a form, it becomes a more accurate and reliable electronic device.

  The third electronic device of the present invention includes a first substrate and a second substrate on which the first substrate is mounted and electrically connected to the first substrate in at least one predetermined region. A first through via penetrating the first substrate, an element isolation region formed in the semiconductor substrate of the second substrate, and a plug formed to connect to the semiconductor substrate of the second substrate, and the element isolation region Is formed so as to surround the position of the lower end portion of the plug, and the first through via and the plug have at least one connection pair electrically connected.

  Since the third electronic device of the present invention is laminated by directly measuring the alignment between the first substrate and the second substrate as will be described later, the electronic device is more accurate and more reliable than the conventional one. It has become.

  As a more specific form of the third electronic device, the first conductive portion is provided on the uppermost layer of the first substrate, the second conductive portion is provided on the uppermost layer of the second substrate, the first conductive portion, The first through via, the second conductive portion, and the plug may be electrically connected.

  As a more specific form of the third electronic device, the first through via and the plug may be formed on the outer peripheral portion in the predetermined region.

  Moreover, there may be a plurality of connection pairs. By setting it as such a form, it becomes a more accurate and reliable electronic device.

  In order to achieve the above object, a first electronic device manufacturing method according to the present invention includes a step (a) of forming at least one pair of through vias in a first substrate and a step of forming wirings in a second substrate. (B), and after step (a) and step (b), there is a step (c) for bonding the first substrate and the second substrate, and at least one pair of through vias are electrically connected via the wiring. Having at least one connection pair connected to each other.

  According to the manufacturing method of the first electronic device, the first substrate can be mounted on the second substrate while directly measuring the alignment, and an electronic device that is more accurately and reliably aligned than before is manufactured. Can do. For this reason, the yield of electronic device manufacture is also improved. Furthermore, the present invention can be applied to various cases such as when the first substrate and the second substrate are both chips, when both are wafers, and when they are chips and wafers.

  That is, in step (c), a current is passed through at least two through vias and the current value is observed to observe the displacement of the relative position between the first substrate and the second substrate. As a result, the alignment between the first substrate and the second substrate can be directly observed, and mounting can be performed while suppressing the positional deviation as compared with the indirect method.

  Further, the second method for manufacturing an electronic device according to the present invention includes a step (a) of forming a first through via in the first substrate, a step (b) of forming a second through via in the second substrate, After the step (a) and the step (b), the method includes a step (c) for bonding the first substrate and the second substrate, and the first through via and the second through via are at least electrically connected. It has one connection pair.

  In the step (c), it is preferable to apply a current to the first through via and the second through via and to bond them while observing the current value.

  The third electronic device manufacturing method according to the present invention includes a step (a) of forming a first through via in the first substrate and a step (b) of forming an element isolation region in the semiconductor substrate of the second substrate. And a step (c) of forming a plug so as to be connected to the semiconductor substrate of the second substrate, and a step (d) of bonding the first substrate and the second substrate after the steps (a) and (b). The element isolation region is formed so as to surround the position of the lower end portion of the plug, and the first through via and the plug have at least one connection pair electrically connected.

  In the step (c), it is preferable to apply a current to the first through via and the plug and bond them while observing the current value.

  The second electronic device manufacturing method and the third electronic device manufacturing method also achieve the same effects as the first electronic device manufacturing method, such as accurate alignment and improved manufacturing yield.

  According to the electronic device and the method for manufacturing the same according to the present invention, since it is possible to perform bonding while directly observing the optimum portion where the positional deviation is minimized, the manufacturing yield of the electronic device can be improved. Further, it is possible to cope with bonding of various elements such as a wafer and a wafer and a chip and a chip.

(First embodiment)
Hereinafter, an electronic device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. However, each of the following drawings and the shapes, materials, dimensions, and the like of various components are preferable examples, and are not limited to the contents shown. As long as it does not deviate from the gist of the invention, it can be appropriately changed without being limited to the description. In the first embodiment, the wafer-wafer bonding is mainly described. However, the same explanation holds for the wafer-chip bonding and the chip-chip bonding, and the same effect can be obtained. .

  FIG. 1 is a schematic cross-sectional view of a main part of an electronic device 100 of this embodiment. The electronic device 100 includes a first wafer Wf1 and a second wafer Wf2 on which the first wafer Wf1 is mounted. These are laminated with the first wafer Wf1 as the upper side and the second wafer Wf2 as the lower side, and are bonded to each other by the adhesive 301. In the predetermined region, the first wafer Wf1 and the second wafer Wf2 are electrically connected. More specifically, a through via 110 penetrating the semiconductor substrate 101 of the first wafer Wf1 in the predetermined region is provided, and the first wafer Wf1 and the second wafer Wf2 are provided via the through via 110. Are electrically connected.

  In each drawing in the embodiment, it is assumed that one chip area of the wafer is shown. This chip area can be considered as a predetermined area. The chip area is an area that becomes an individual chip by dividing the wafer. In each chip area, a plurality of MOS elements and the like are formed on the semiconductor substrate 101.

  Next, the planar arrangement of the wiring 213 in the second wafer Wf2 located below the electronic device 100 will be described. FIGS. 2A to 2D and FIGS. 3A to 3E are views for explaining the second wafer Wf2.

  FIG. 2A shows an example of a planar shape of a pair (two) of wirings 122 as a cross section taken along the line II-II ′ in the region I of FIG. Here, the region I in FIG. 1 indicates a region in the vicinity of the outer peripheral portion in one chip region. FIG. 2A shows the planar shape of a pair of wirings 122 in one chip region 401. Here, the wirings 119, 116, 113, 222, 219, and 216 when the region I of FIG. 1 is cut by a line parallel to the II-II ′ line have the same planar shape as the wiring 122 (not shown). . However, it is not limited to such an arrangement. Here, it is desirable that the pair of wirings 113 and 222 is in the vicinity of the outer peripheral portion of the chip region 401. Further, it is desirable that the pair of wirings 113 and 222 is positioned at the counter electrode with the center of the chip region 401 as an axis. Here, the pair of wirings 113 and 222 correspond to wirings connected to the through electrodes of the wafer.

  FIG. 2B shows an example of a planar shape of the wiring 213 as a cross section taken along line III-III ′ in the region I of FIG. Here, the region I in FIG. 1 indicates the vicinity of the outer peripheral portion in one chip region. The wiring 213 is desirably in the vicinity of the outer peripheral portion of the chip region 401.

  As can be seen from FIG. 1, FIG. 2A and FIG. 2B, the pair of wirings 122 includes vias 121, 118, 115, 221, 218, 215, wirings 119, 116, 113, 222, 219, 216, the through via 110, and the wiring 213 are electrically connected.

  This has the effect of facilitating alignment, as will be described in detail later.

  Moreover, the modification of FIG. 2 (a) and (b) was shown to FIG.2 (c) and (d), respectively.

  FIG. 2C shows an example of a planar shape of the pair of wirings 122a and the pair of wirings 122b as a section taken along the line II-II ′ in the region I of FIG. Here, the region I in FIG. 1 indicates the vicinity of the outer peripheral portion in one chip region. A pair of wirings 119a and 119b, 116a and 116b, 113a and 113b, 222a and 222b, 219a and 219b, 216a and 216b when the region I in FIG. The planar shape is the same as that of the wirings 122a and 122b (not shown). However, it is not limited to such an arrangement.

  Here, it is desirable that the pair of wirings 113a and 113b, 222a and 222b be near the outer periphery of the chip region 401, respectively. Further, it is desirable that the pair of wirings 113a and 113b, 222a and 222b be positioned at the counter electrode with the center of the chip region 401 as an axis. The pair of wirings 113a and 113b, 222a and 222b correspond to wirings connected to the through electrodes of the wafer.

  FIG. 2D shows an example of a planar shape related to the wiring 213a and the wiring 213b as a section taken along the line III-III ′ in the region I of FIG. Here, the region I in FIG. 1 indicates the vicinity of the outer peripheral portion in one chip region. Also, the wiring 213a and the wiring 213b are desirably in the vicinity of the outer peripheral portion of the chip region 401.

  As can be seen from FIGS. 1, 2 (c), and 2 (d), the pair of wirings 122 a includes vias 121, 118, 115, 221, 218, 215, wirings 119, 116, 113, 222, 219, 216, the through via 110, and the wiring 213a are electrically connected. The same can be said for the pair of wirings 122b.

  As described above, there may be a plurality of wiring pairs. There is an effect that the alignment accuracy is improved when there are a plurality.

  Moreover, the modification of FIG. 2 (a) and (b) was also shown to FIG. 3 (a) and (b), respectively.

  FIG. 3A shows an example of a planar shape of the three wirings 122 as a cross section taken along the line II-II ′ in the region I of FIG. Here, the region I in FIG. 1 indicates the vicinity of the outer peripheral portion in one chip region. Here, each of the three wirings 119, 116, 113, 222, 219, and 216 when the region I in FIG. 1 is cut by a line parallel to the II-II ′ line has the same planar shape (not shown). However, it is not limited to such an arrangement.

  Here, it is desirable that the three wirings 113 and 222 are in the vicinity of the outer periphery of the chip region 401, respectively. In addition, the wirings 113 and 222 are desirably in the vicinity of the outer peripheral portion of the chip region 401. Here, the three wirings 113 and 222 correspond to wirings connected to the through electrodes of the wafer.

  FIG. 3B shows an example of a planar shape of the wiring 213 as a cross section taken along line III-III ′ in the region I of FIG. Here, the region I in FIG. 1 indicates the vicinity of the outer peripheral portion in one chip region. Here, the wiring 213 is desirably in the vicinity of the outer peripheral portion of the chip region 401.

  As can be seen from FIGS. 1, 3A, and 3B, two of the three wirings 122 are connected to vias 121, 118, 115, 221, 218, and 215, and wirings 119 and 116, respectively. , 113, 222, 219, 216, through via 110, and wiring 213.

  As described above, there may be a plurality of through vias connected to the wiring 213. There is an effect that the alignment accuracy is improved when there are a plurality. Moreover, there is no problem that through vias that do not constitute pairs are formed.

  FIGS. 3C to 3E show modified examples of the second wafer Wf2 in the region I of FIG. In FIGS. 1, 2A to 2D, and FIGS. 3A and 3B, a pair of wirings 122 are electrically connected to each other through the wiring 213, but as shown in FIG. 3C. In addition, the wiring 122 may be electrically connected through the wiring 216. Further, as illustrated in FIG. 3D, a pair of wirings 122 may be electrically connected through the wiring 219. Further, as illustrated in FIG. 3E, a pair of wirings 122 may be electrically connected through the wiring 222.

  As shown in FIG. 3C to FIG. 3E, the lower layer space can be effectively used by electrically connecting the pair of wirings 122 using the upper layer wiring as much as possible. There is an effect that the width of.

  In addition, about each above modification, it is also possible to combine mutually suitably.

  Hereinafter, a more detailed structure and formation method of the first wafer Wf1 and the second wafer Wf2 will be described.

  FIGS. 4A and 4B and FIGS. 5A and 5B are schematic cross-sectional views for explaining the structure and forming method of the first wafer Wf1 located on the upper side in the electronic device 100. FIG. It is.

  In order to form the first wafer Wf1, first, the process of FIG. Here, for example, a semiconductor substrate 101 which is a thin plate having a substantially circular planar shape is prepared. The semiconductor substrate 101 is a substrate made of, for example, an n-type or p-type silicon single crystal.

An element isolation 102 is formed on the semiconductor substrate 101. This is formed by forming a groove on the upper surface of the semiconductor substrate 101 by lithography and dry etching, and embedding a silicon oxide film (SiO ₂ ) in the groove by, for example, CVD (Chemical Vapor Deposition).

  Next, for example, a MOS (Metal Oxide Semiconductor) element is formed in an active region surrounded by the element isolation 102 in the semiconductor substrate 101. A semiconductor region 103 for source and drain, a gate electrode 104, and the like are included.

Here, the semiconductor region 103 is formed by adding a predetermined impurity (for example, phosphorus (P) or arsenic for n-channel type, for example, boron (B) for p-channel type) to the semiconductor substrate 101. To do. Further, the gate electrode 104 is formed on the semiconductor substrate 101 as an electrode made of polysilicon through a gate insulating film made of, for example, a silicon oxide film (SiO ₂ ).

  Next, an insulating film 105 such as a silicon oxide film is deposited so as to cover the semiconductor substrate 101. Thereafter, an excess silicon oxide film deposited on the gate electrode 104 is removed by CMP (Chemical Mechanical Polishing) and planarized. Subsequently, a plug 106 is formed so as to be embedded in the insulating film 105 and connected to the semiconductor region 103 and the gate electrode 104 and electrically connected to a wiring to be formed in a later process (however, in the drawing, the gate electrode 104 is formed). The plug to connect to is not shown). The plug 106 is formed of a metal such as tungsten (W), aluminum (Al), or copper (Cu).

  Next, the process of FIG. 4B is performed. First, a liner film is deposited over the entire surface so as to cover the plug 106 and the insulating film 105 (not shown). This is formed, for example, as a silicon nitride film (SiN) having a thickness of about 30 nm by a CVD method. Further, a silicon oxide film may be used instead of the silicon nitride film.

  Thereafter, a through via hole is formed using a lithography method and a dry etching method. This is formed to a depth that penetrates the liner film and the insulating film 105 and further engraves the semiconductor substrate 101 to about 1/7 to 1/8, for example. If the thickness of the semiconductor substrate 101 is 750 μm, the depth is 100 μm.

  Next, using a sputtering method and a plating method, a barrier film made of tantalum (Ta) / tantalum nitride (TaN) and a copper (Cu) film are sequentially deposited so as to fill the via hole and cover the liner film. To do. Thereafter, the through via 110 is formed so as to fill the through via hole by removing the portion of the barrier film and the copper film that protrudes over the liner film by using the CMP method.

  Here, a laminated film of a Ta film and a TaN film is used as the barrier film, but a barrier film made of only one of a Ta film and a TaN film may be used. Moreover, although copper was used as the material of the conductive film that embeds the through via hole, silver (Ag), aluminum (Al), or an alloy thereof can also be used.

  In addition, it is preferable to form an insulating film on the side wall of the through via hole before forming the barrier film. Alternatively, instead of forming the insulating film, the through via 110 may be surrounded by an insulating material.

  Next, the wiring 113 is formed. For this purpose, first, an insulating film 107 made of, for example, a 200 nm-thickness silicon oxide film is deposited by CVD to cover the through via 110 and the liner film. Subsequently, a plurality of wiring grooves are formed at intervals from each other so as to penetrate both the insulating film 107 and the liner film by lithography and dry etching.

  Next, a barrier film made of tantalum (Ta) / tantalum nitride (TaN) and a copper (Cu) film are sequentially deposited so as to fill the wiring trench and cover the insulating film 107 by sputtering and plating.

  Thereafter, unnecessary portions of the barrier film and the copper film that protrude to the insulating film 107 are removed by CMP, thereby forming the wiring 113 made of the barrier film and the copper film that fills the wiring groove.

  Here again, the barrier film is not limited to the laminated structure of Ta film / TaN film, but may be a single Ta film or TaN film. Further, instead of the copper film, a film made of silver, aluminum, or an alloy thereof may be used.

  Next, the process of FIG. Here, a plurality of insulating films 114, 117, and 120 stacked and wiring structures (vias 115, 118, and 121 and wirings 116, 119, and 122) embedded therein are formed.

  First, an insulating film 114 made of a silicon oxide film having a thickness of 400 nm is deposited by, for example, a CVD method so as to cover the insulating film 107 including the wiring 113. Subsequently, a plurality of via holes and wiring trenches connected to the plurality of via holes are formed in the insulating film 114 by lithography and dry etching.

  Next, a barrier film made of tantalum (Ta) / tantalum nitride (TaN) and a copper (Cu) film are sequentially deposited so as to fill the via hole and the wiring groove and cover the insulating film 114 by sputtering and plating. To do.

  Thereafter, by using the CMP method, the unnecessary barrier film and copper film protruding to the top of the insulating film 114 are removed, whereby the via 115 having the structure in which the via hole and the wiring groove are embedded in the barrier film and the copper film, and A wiring 116 is formed. Note that the via 115 connected to a desired portion of the wiring 113 can be formed by setting the position of the via hole as necessary.

  Further, by repeating the same process, the insulating film 117 formed on the insulating film 114 and the via 118 and wiring 119 embedded therein, the insulating film 120 formed on the insulating film 117 and the via 121 embedded therein are provided. And the wiring 122 is formed, and a multilayer wiring structure is formed. Although the total number of wirings is four layers here, this is an example and is not particularly limited.

  In this embodiment, each of the insulating films 114, 117 and 120 has a single layer structure of a silicon oxide film. However, in addition to this, a single layer structure made of other materials may be used, or a laminated film such as a silicon oxide film / silicon nitride film may be used. Further, the barrier film is not limited to the laminated structure composed of Ta film / TaN film, and may be a single Ta film or TaN film. Furthermore, instead of the copper film, a film made of silver, aluminum, or an alloy thereof may be used.

  Next, the process of FIG. 5B is performed. Here, the semiconductor substrate 101 is thinned from the back surface, and the lower end portion of the through via 110 is exposed as the through via bottom 123 on the back surface side of the semiconductor substrate 101.

  As the thinning process, for example, the back surface of the semiconductor substrate 101 is first ground until a desired thickness is obtained, and then a polishing process having both mechanical and chemical elements such as a CMP method is performed. At this time, the through via bottom 123 is not exposed. Thereafter, the back surface of the semiconductor substrate 101 is etched by a wet etching method to expose the through via bottom 123.

  As another example of the thinning process, a CMP method and a wet etching method may be used without performing grinding. Further, the thinning process may be performed only by the CMP method or only by the wet etching method.

  As described above, the first wafer Wf1 positioned above the electronic device 100 is formed.

  Next, FIGS. 6A and 6B and FIG. 7 are schematic cross-sectional views for explaining the structure and formation method of the second wafer Wf2 located on the lower side in the electronic device 100. FIG.

  First, the structure shown in FIG. 6A is formed. This is the same as the structure shown in FIG. 5A for the first wafer Wf1, and only the reference numerals are different. That is, an active region is partitioned on the semiconductor substrate 201 by the element isolation 202, and a MOS element including the semiconductor region 203, the gate insulating film (not shown), and the gate electrode 204 is formed in the active region. An insulating film 205 is formed so as to cover the semiconductor substrate 201 including the MOS element, and a plug 206 is formed so as to penetrate the insulating film 205 and reach the semiconductor region 203 and the like. These may be formed in the same manner as described for the first wafer Wf1. However, it is not essential that the second wafer Wf2 has the same structure as that of the first wafer Wf1 as described above, and another structure may be used.

  Next, the process shown in FIG. First, an insulating film 207 made of a silicon oxide film having a thickness of 200 nm is deposited by, for example, a CVD method so as to cover the plug 206 and the insulating film 205. Subsequently, a plurality of wiring grooves are formed in the insulating film 207 at intervals from each other by lithography and dry etching.

  Thereafter, a barrier film made of tantalum (Ta) / tantalum nitride (TaN) and a copper (Cu) film are sequentially deposited so as to fill the wiring trench and cover the insulating film 207 by sputtering and plating.

  After that, by using the CMP method, unnecessary barrier film and copper film protruding to the top of the insulating film 207 are removed, thereby forming a wiring 213 made of a barrier film and a copper film filling the wiring trench. By setting the position of the wiring groove, the wiring 213 can be arranged at an arbitrary position, for example, connected to the plug 206.

  Here again, the barrier film is not limited to the laminated structure of Ta film / TaN film, but may be a single Ta film or TaN film. Further, instead of the copper film, a film made of silver, aluminum, or an alloy thereof may be used.

  In this embodiment, the insulating film 107 has a single layer structure of a silicon oxide film. However, in addition to this, a single layer structure made of other materials may be used, or a laminated film such as a silicon oxide film / silicon nitride film may be used.

  Next, the process shown in FIG. 7 is performed. Here, a plurality of insulating films 214, 217 and 220 stacked, and wiring structures (vias 215, 218 and 221 and wirings 216, 219 and 222) embedded therein are formed.

  For example, the first wafer Wf1 can be formed by the same method as described in FIG. However, another method may be used.

  Further, since the wiring 222 located in the uppermost layer needs to be connected to the through via bottom 123 in the first wafer Wf1, it is formed at a position corresponding to it. The wirings 216 and 219 of the other layers and the vias 215, 218 and 221 connecting the wirings of the respective layers can be arbitrarily arranged.

  As described above, the second wafer Wf2 positioned below the electronic device 100 is formed.

  Thereafter, the first wafer Wf1 is mounted on the second wafer Wf2 so that the two wafers are bonded together. Below, this bonding process is demonstrated.

  8 and 9 are a cross-sectional view and a plan view for explaining a method of aligning the steps of bonding the first wafer Wf1 and the second wafer Wf2.

  First, after preparing the lower second wafer Wf2, the upper first wafer Wf1 is disposed thereon so that the back surface thereof faces the main surface of the second wafer Wf2.

  Subsequently, the relative positions of the second wafer Wf2 and the first wafer Wf1 are aligned. Specifically, the uppermost layer wiring 222 in the second wafer Wf2 and the corresponding through via bottom 123 on the back surface of the first wafer Wf1 are aligned.

  Further, the opposing surfaces of both wafers are brought close to each other, and the uppermost wiring 222 of the second wafer Wf2 and the through via bottom 123 of the first wafer Wf1 are brought into contact with each other to be electrically connected. Thereby, the electrical connection between the first wafer Wf1 and the second wafer Wf2 is performed.

  After that, by injecting an insulating adhesive 301 into the gap between the first wafer Wf1 and the second wafer Wf2 (see FIG. 1), the stacked first wafer Wf1 and second wafer Wf2 To ensure mechanical strength.

  After the first wafer Wf1 and the second wafer Wf2 are bonded together in this way, both wafers are cut into chips to obtain individual chips (electronic device 100). The electronic device thus obtained has a three-dimensional structure in which a plurality of (here, two) chips are stacked. That is, the semiconductor circuits and the like provided in each of the plurality of chips are electrically connected through the through vias, so that one semiconductor integrated circuit is configured as a whole.

  Here, the alignment between the first wafer Wf1 and the second wafer Wf2 will be further described.

  First, a certain degree of alignment is performed using an optical alignment method or the like. Thereafter, as shown in FIGS. 8 and 9, terminals at both ends connected to the power source 501 are connected to connection pads 502 and 503 formed on the uppermost wiring 122 of the upper wafer Wf1, respectively. Thereafter, the power is turned on and a current 504 is applied by applying a voltage. At this time, when the through via bottom 123 electrically connected to the connection pads 502 and 503 of the upper wafer Wf1 and the uppermost layer wiring 222 of the lower wafer Wf2 are connected, the wiring 213 of the lower wafer Wf2 is connected. Current 504 flows therethrough. At this time, the current value of the current 504 can be monitored (observed) through the ammeter 505.

  Here, current does not flow unless the upper wafer Wf1 and the lower wafer Wf2 match. When the through via bottom 123 of the upper wafer Wf1 is on the uppermost layer wiring 222 of the lower wafer Wf2, but is not completely connected, the resistance increases and the current value decreases. On the other hand, when the connection is complete, the current value is the largest.

  Therefore, this current value is monitored, and the lower wafer Wf2 is moved in parallel or rotated little by little with respect to the main surface of the lower wafer Wf2. And the position where an electric current value becomes the maximum in the movement range is determined as an optimal position.

  According to such an alignment method, both wafers can be bonded while directly observing the optimum position where the alignment displacement is minimized, which is more accurate and more accurate than the prior art which was indirect alignment. Appropriate alignment can be performed. Thus, the yield of electronic device manufacturing is improved. In addition, such a method is not limited to the alignment between wafers, but can also correspond to the alignment between chips, the alignment of chips with respect to the wafer, and the like.

(Second Embodiment)
Next, an electronic device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. Also in the present embodiment, each of the following drawings and the shapes, materials, dimensions, and the like of various components are desirable examples, and are not limited to the contents shown. As long as it does not deviate from the gist of the invention, it can be appropriately changed without being limited to the description. In the second embodiment, the wafer-wafer bonding is mainly described. However, the same explanation holds for the wafer-chip bonding and the chip-chip bonding, and the same effect can be obtained. .

  Here, the electronic device 100 of the second embodiment is illustrated in FIG. Similar to the electronic device 100 of the first embodiment, the electronic device of the second embodiment has a structure in which two wafers are stacked. The first wafer Wf1 and the second wafer on the upper side thereof have the same structure as the first wafer Wf1 in the first embodiment shown in FIG. 1, and the first wafer Wf1 in the first embodiment is the same as the first wafer Wf1. What is necessary is just to manufacture as demonstrated at the time of forming.

  That is, the structure and manufacturing method of the second wafer Wf2 formed on the lower side are different between the first embodiment and the second embodiment. Here, the description of the manufacturing method of the first wafer Wf1 and the second wafer Wf2 of the second embodiment will be omitted. However, FIG. 10 shows a structure in which two wafers are stacked using the second wafer Wf2 formed by omitting the step of exposing the bottom of the through via. Two wafers Wf2 may be used.

  In FIG. 10, the uppermost layer wiring 122 of the first wafer Wf1 and the semiconductor substrate region near the lower end or near the lower end of the through via 210 of the second wafer Wf2 are wirings 119, 116, 113, 222, 219, 216, 213, vias 121, 118, 115, 221, 218 and 215, and through vias 110 and 210 are electrically connected. Thus, there is an effect that alignment is advantageous by being electrically connected.

  Next, modified examples in the region III of FIG. 10 will be described with reference to FIGS. 11 (a) to 11 (c).

  In FIG. 11A, the through via 210 is formed only at a position necessary for alignment. As shown in FIG. 10, it is advantageous in terms of cost because it is formed only at a position necessary for alignment (in the vicinity of the outer peripheral portion of the chip region) without being formed except for the position necessary for alignment.

  FIG. 11B shows an example in which the second wafer Wf2 in which the bottom of the through via is exposed by polishing the back surface of the second wafer Wf2. In order to stack a large number of semiconductor substrates, it is desirable that the through via 108 is exposed.

  FIG. 11C is a diagram showing a portion (near the outer peripheral portion of the chip region 401) necessary for alignment in the cross-sectional view along the line AA ′ in FIGS. 11A and 11B. . It can also be said that the cross-sectional view taken along line BB ′ of FIG. 11C corresponds to FIG. 11A and FIG. As shown in FIG. 11C, the through via 210 is desirably formed at a position necessary for alignment (near the outer periphery of the chip region 401), and is located at the counter electrode with the center of the chip region 401 as an axis. It is desirable that

  In FIG. 11D, a through via is not formed in the second wafer Wf2, but a plug 206 is formed at a position necessary for alignment (near the outer peripheral portion of the chip region 401), and the lower end of the plug 206 is surrounded. As described above, the element isolation 202 is formed on the semiconductor substrate 201. In this way, the uppermost layer wiring 122 of the first wafer Wf1 and the semiconductor substrate region connected to the lower end of the plug 206 are connected to the wirings 119, 116, 113, 222, 219, 216, 213, Electrical connection can be made through the vias 121, 118, 115, 221, 218, 215, the through via 110, and the plug 206. Further, as shown in FIG. 11D, when the back surface of the second wafer Wf2 is polished until the bottom surface of the element isolation is exposed, current leakage in the planar direction of the substrate can be suppressed. desirable.

  FIG. 11E is a view showing a location (near the outer peripheral portion of the chip region 401) necessary for alignment in the cross-sectional view of the AA ′ plane in FIG. It can also be said that the cross-sectional view of the BB ′ plane in FIG. 11E corresponds to FIG. As shown in FIG. 11E, the plug 206 whose bottom surface is surrounded by the element isolation 202 is desirably formed at a position necessary for alignment (near the outer periphery of the chip area 401). It is desirable to be located at the counter electrode with the center of the axis as the axis.

  Next, the process of aligning both wafers will be described. FIG. 12 is a diagram for explaining an alignment method in the present embodiment.

  First, as in the case of the first embodiment (FIGS. 8 and 9), the first wafer Wf1 is placed on the second wafer Wf2, and a certain degree of alignment is performed by an optical technique. Next, as shown in FIG. 12, terminals (not shown) at both ends of the power supply 501 are connected to the connection pads 603 and the semiconductor substrate region 602 at the lower end of the through via 210, respectively (in FIG. Shows electrical connections).

  Thereafter, the power source 501 is turned on and a voltage is applied, thereby causing a current 504 to flow. The through via bottom 110 connected to the upper layer connection pad 603 of the upper wafer Wf1 and the uppermost layer wiring 506 connected to the lower layer connection region (semiconductor substrate region) 602 in which the through via of the lower wafer Wf2 is formed are connected. Then, a current 504 flows. At this time, the current value of the current 504 can be monitored through the ammeter 505.

  Here, no current flows unless the upper wafer Wf1 and the lower wafer Wf2 are connected. Further, when the through via bottom 110 of the upper wafer Wf1 is on the uppermost layer wiring 222 of the lower wafer Wf2, but is not completely connected, the resistance increases and the current value becomes small. Furthermore, when the connection is complete, the current value is the largest.

  Therefore, this current value is monitored, and the lower wafer Wf2 is moved in parallel or rotated little by little with respect to the main surface of the lower wafer Wf2. And the position where an electric current value becomes the maximum in the movement range is determined as an optimal position.

  As in the case of the first embodiment, both wafers can be bonded while directly observing the optimum position where the misalignment is the smallest, which is more accurate than the conventional technique that was indirect alignment. In addition, appropriate alignment can be performed. Thus, the yield of electronic device manufacturing is improved. In addition, such a method is not limited to the alignment between wafers, but can also correspond to the alignment between chips, the alignment of chips with respect to the wafer, and the like.

  In the first embodiment and the second embodiment, as the electronic devices, the first wafer Wf1 and the second wafer Wf2 each provided with a MOS element, a wiring structure, and the like are bonded to each other as a semiconductor substrate. The example which manufactures an apparatus was demonstrated. However, it is not limited to this. For example, even when an insulating substrate having a conductive film is used, the present invention can be applied to the conductive film without any problem. Furthermore, the present invention can also be applied to a case where a structure having a through via 110 is mounted in alignment on a printed board.

  The electronic device and the method of manufacturing the same according to the present invention are semiconductors that are more compact and thinner to increase the mounting density in order to realize a stacked structure (three-dimensional structure) in which a plurality of substrates are accurately and reliably aligned with high yield. It is also useful as a device.

FIG. 1 is a schematic cross-sectional view illustrating the structure of an electronic device according to the first embodiment of the present invention. FIGS. 2A to 2D are diagrams showing plan views in the first embodiment of the present invention. FIGS. 3A and 3B are plan views of the first embodiment of the present invention, and FIGS. 3C to 3E illustrate modified examples of the structure of the second wafer. It is typical sectional drawing. FIGS. 4A and 4B are schematic cross-sectional views illustrating the structure and formation method of the first wafer in the first embodiment of the present invention. FIGS. 5A and 5B are schematic cross-sectional views for explaining the structure and forming method of the first wafer in the first embodiment of the present invention, following FIG. 4B. FIGS. 6A and 6B are schematic cross-sectional views illustrating the structure and formation method of the second wafer in the first embodiment of the present invention. FIG. 7 is a schematic cross-sectional view for explaining the structure and the forming method of the second wafer in the first embodiment of the present invention, following FIG. FIG. 8 is a schematic cross-sectional view for explaining the alignment method in the first embodiment of the present invention. FIG. 9 is a schematic plan view for explaining the alignment method in the first embodiment of the present invention. FIG. 10 is a schematic cross-sectional view illustrating the structure of an electronic device according to the second embodiment of the present invention. FIGS. 11A to 11E are schematic plan views for explaining a second wafer in a modification of the second embodiment of the present invention. FIG. 12 is a schematic cross-sectional view and a plan view for explaining a positioning method in the second embodiment of the present invention. FIG. 13 is a schematic cross-sectional view for explaining a conventional alignment method.

Explanation of symbols

Wf1 First wafer Wf2 Second wafer 100 Electronic device 101 Semiconductor substrate 102 Element isolation 103 Semiconductor region 104 Gate electrodes 105, 107, 114, 117, 120 Insulating film 106 Plug 110 Through-via 113, 116, 119, 122 Wiring 115 , 118, 121 Via 123 Bottom of through via 401 Chip region 201 Semiconductor substrate 202 Element isolation 203 Semiconductor region 204 Gate electrode 205, 207, 214, 217, 220 Insulating film 206 Plug 213, 216, 219, 222 Wiring 215, 218, 221 Via 301 Adhesive 501 Power supply 502 Connection pad 503 Connection pad 504 Current 505 Ammeter 602 Connection area 603 Connection pad

Claims (18)

A first substrate; and a second substrate mounted with the first substrate and electrically connected to the first substrate in at least one predetermined region;
The predetermined area is:
At least two through vias penetrating the first substrate;
Wiring provided on the second substrate,
The at least two through vias have at least one connection pair electrically connected through the wiring. In claim 1,
At least two conductive portions are formed on the uppermost layer of the first substrate;
Each of the at least two through vias is separately electrically connected to each of the at least two conductive portions. In claim 1 or 2,
The electronic device according to claim 1, wherein the at least two through vias are formed in an outer peripheral portion in the predetermined region. In any one of Claims 1-3,
An electronic device characterized in that a plurality of the connection pairs exist. A first substrate; and a second substrate mounted with the first substrate and electrically connected to the first substrate in at least one predetermined region;
The predetermined area is:
A first through via penetrating the first substrate;
A second through via penetrating the second substrate;
The electronic device, wherein the first through via and the second through via have at least one connection pair electrically connected. In claim 5,
A first conductive portion on an uppermost layer of the first substrate;
A second conductive portion on the uppermost layer of the second substrate;
The electronic device, wherein the first conductive portion, the first through via, the second conductive portion, and the second through via are electrically connected. In claim 5 or 6,
The electronic device, wherein the first through via and the second through via are formed in an outer peripheral portion in the predetermined region. In any one of Claims 5-7,
An electronic device characterized in that a plurality of the connection pairs exist. A first substrate; and a second substrate mounted with the first substrate and electrically connected to the first substrate in at least one predetermined region;
The predetermined area is:
A first through via penetrating the first substrate;
An element isolation region formed in the semiconductor substrate of the second substrate;
A plug formed to connect to the semiconductor substrate of the second substrate;
The element isolation region is formed so as to surround a position of a lower end portion of the plug,
The electronic device, wherein the first through via and the plug have at least one connection pair electrically connected. In claim 9,
A first conductive portion on an uppermost layer of the first substrate;
A second conductive portion on the uppermost layer of the second substrate;
The electronic device, wherein the first conductive portion, the first through via, the second conductive portion, and the plug are electrically connected. In claim 9 or 10,
The electronic device according to claim 1, wherein the first through via and the plug are formed in an outer peripheral portion in the predetermined region. In any one of Claims 9-11,
An electronic device characterized in that a plurality of the connection pairs exist. Forming at least two through vias in the first substrate;
Forming a wiring on the second substrate (b);
After the step (a) and the step (b), the method includes a step (c) of bonding the first substrate and the second substrate,
The method of manufacturing an electronic device, wherein the at least two through vias have at least one connection pair electrically connected through the wiring. In claim 13,
In the step (c), a current is supplied to the at least two through vias via the wiring, and the electronic device is bonded while observing the current value. Forming a first through via in the first substrate;
Forming a second through via in the second substrate;
After the step (a) and the step (b), the method includes a step (c) of bonding the first substrate and the second substrate,
The method of manufacturing an electronic device, wherein the first through via and the second through via have at least one connection pair electrically connected. In claim 15,
16. The method of manufacturing an electronic device according to claim 15, wherein, in the step (c), a current is passed through the first through via and the second through via, and the current is observed while observing the current value. Forming a first through via in the first substrate;
A step (b) of forming an element isolation region in the semiconductor substrate of the second substrate;
Forming a plug to connect to the semiconductor substrate of the second substrate;
After the step (a) and the step (b), the method includes a step (d) of bonding the first substrate and the second substrate,
The element isolation region is formed so as to surround a position of a lower end portion of the plug,
The method of manufacturing an electronic device, wherein the first through via and the plug have at least one connection pair electrically connected. In claim 17,
16. The method of manufacturing an electronic device according to claim 15, wherein in the step (d), a current is passed through the first through via and the plug, and bonding is performed while observing the current value.

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