CN112600560B - High-precision two-step successive approximation register analog-to-digital converter - Google Patents
High-precision two-step successive approximation register analog-to-digital converter Download PDFInfo
- Publication number
- CN112600560B CN112600560B CN202011509041.5A CN202011509041A CN112600560B CN 112600560 B CN112600560 B CN 112600560B CN 202011509041 A CN202011509041 A CN 202011509041A CN 112600560 B CN112600560 B CN 112600560B
- Authority
- CN
- China
- Prior art keywords
- analog
- digital converter
- stage sub
- capacitors
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005070 sampling Methods 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 97
- 239000013256 coordination polymer Substances 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 102100026533 Cytochrome P450 1A2 Human genes 0.000 description 2
- 101000855342 Homo sapiens Cytochrome P450 1A2 Proteins 0.000 description 2
- 101000949825 Homo sapiens Meiotic recombination protein DMC1/LIM15 homolog Proteins 0.000 description 2
- 101001046894 Homo sapiens Protein HID1 Proteins 0.000 description 2
- 102100022877 Protein HID1 Human genes 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 102100031476 Cytochrome P450 1A1 Human genes 0.000 description 1
- 101000941690 Homo sapiens Cytochrome P450 1A1 Proteins 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000013641 positive control Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-precision two-step successive approximation register analog-to-digital converter which comprises a sampling and holding circuit, a first-stage sub-analog-to-digital converter, a second-stage sub-analog-to-digital converter, a successive approximation register logic circuit and a parallel-to-serial interface circuit, wherein the sampling and holding circuit is connected with the first-stage sub-analog-to-digital converter, the first-stage sub-analog-to-digital converter is connected with the second-stage sub-analog-to-digital converter, the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, and a residual amplifier and a digital calibration module are further arranged on the circuit connecting the first-stage sub-analog-to-digital converter and the second-stage sub-analog-digital converter. The invention improves the overall performance of the SAR ADC while greatly improving the accuracy of the SAR ADC.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-precision two-step successive approximation register analog-to-digital converter.
Background
The successive approximation register analog-to-digital converter (successive approximation register analog to digital converter, abbreviated as SAR ADC) is an integrated circuit structure for converting analog quantity into digital quantity which can be recognized by information processing device such as computer. SAR ADCs are widely used due to their small area, low power consumption, etc.
The SAR ADC has many technical indexes including resolution, significant bit (EFFECTIVE NUMBER OF BITS, ENOB), precision, slew rate, differential nonlinear error (DIFFERENTIAL NON-linear, DNL), integral nonlinear error (INL), signal-to-noise ratio, power consumption, chip area, etc. In particular, it is difficult to make some technical indexes compatible, for example, the higher the accuracy and the chip area, the better the accuracy of the SAR ADC, and the smaller the chip area, but the higher the accuracy, the larger the chip area, which affects the overall performance of the SAR ADC. Therefore, the SAR ADC commonly used in current production and scientific research practice has the precision of 8-10 bits. The specific reasons are as follows:
The improvement of SAR ADC precision can lead to the significant increase of high-order capacitance, so that the matching degree of the capacitance is reduced or the area is enlarged. Although the size of the high-order capacitor can be reduced by constructing the capacitor array through the bridge, in the bridge capacitor array, the size of the bridge capacitor is not an integral multiple of the unit capacitor, so that the matching degree of the capacitor is reduced, and the conversion accuracy of the SAR ADC is reduced. If a conventional capacitor array is used, as the accuracy increases, the size of the capacitor increases by 2^i (i increases to the power of 2, i is the number of accuracy bits), so that the size of the capacitor with the highest bit increases significantly, which increases the area of the chip, increases the power consumption of the circuit, and the time required for sampling, thereby affecting the performance of the chip.
Disclosure of Invention
The object of the present invention is to effectively increase the accuracy and overall performance of SAR ADCs, thereby overcoming the above-mentioned drawbacks of the prior art. The aim is achieved by the following technical scheme:
The high-precision two-step successive approximation register analog-to-digital converter comprises a sampling and holding circuit, a first-stage sub analog-to-digital converter, a second-stage sub analog-to-digital converter, a successive approximation register logic circuit and a parallel-to-serial interface circuit, wherein the sampling and holding circuit is connected with the first-stage sub analog-to-digital converter, the first-stage sub analog-to-digital converter is connected with the second-stage sub analog-to-digital converter, the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter are respectively connected with a dynamic comparator, a Residual Amplifier (RA) and a digital calibration module are further arranged on the circuit connecting the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter, one end of the residual amplifier is connected with the first-stage sub analog-to-digital converter through a first switch (S DMC1), and the other end of the residual amplifier is connected with the second-stage sub analog-to-digital converter through a second switch (S DMC2).
On the basis of the technical scheme, the invention can be added with the following technical means so as to better or more pertinently realize the purpose of the invention:
The first-stage sub-analog-digital converter comprises a positive capacitor array consisting of 14 capacitors, a negative capacitor array consisting of 14 capacitors and a comparator; in the positive capacitor array and the negative capacitor array, the first 8 capacitors are divided into one group, the last five capacitors are divided into the other group, and one capacitor is used as a matched capacitor; the lower plate of the capacitor is connected to the differential input voltage (VP, VN), the upper plate is selectively connected to the reference voltage or Ground (GND) through an analog switch, and has two reference voltages (VR, VR 1), one is used as the reference Voltage (VR) of the first 8 capacitors, and the other is used as the reference voltage (VR 1) of the last five capacitors; the upper plate of the matched capacitor is connected with the reference Voltage (VR) of the first 8 capacitors; the comparator outputs a signal by comparing the magnitude of the positive capacitance array lower plate differential input Voltage (VP) with the magnitude of the negative capacitance array lower plate differential input Voltage (VN).
Further, the second-stage sub-analog-digital converter comprises a positive capacitor array formed by 8 capacitors, a negative capacitor array formed by 8 capacitors and a comparator; the lower plate of the capacitor is connected to the differential input voltage and has a reference Voltage (VR), and the upper plate is selectively connected to the reference voltage or ground through an analog switch.
The invention has the following beneficial effects:
the application uses a comparator to compare the differential input voltages VP and VN of the lower plates of the positive and negative capacitor arrays to generate output, and then uses a SAR logic circuit to generate a control signal to switch the upper plate switch of the capacitor arrays, so that the signal is connected to a reference voltage (VR or VR 1) or Ground (GND). Because of the special capacitor array structure of the first-stage sub-ADC, the maximum capacitance array is 2-7C (unit capacitance), and the capacitance in the application is not too large under the high precision of 22 bits, thereby being beneficial to reducing the chip area and the circuit power consumption. In a word, the application improves the overall performance of the SAR ADC while greatly improving the SAR ADC precision.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a schematic diagram of a first stage sub-ADC capacitor array according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a capacitor array of a second stage sub-ADC in an embodiment of the invention.
Detailed Description
The technical scheme and the working method of the invention are described in detail below through an embodiment and with reference to the accompanying drawings.
As shown in figure 1, the high-precision two-step successive approximation register analog-to-digital converter comprises a sample-hold circuit (SH), a first-stage sub-analog-to-digital converter (first-stage sub-ADC), a second-stage sub-analog-to-digital converter (second-stage sub-ADC), a successive approximation register logic circuit (SAR logic circuit) and a parallel-to-serial interface circuit, wherein the sample-hold circuit is connected with the first-stage sub-analog-to-digital converter, the first-stage sub-analog-to-digital converter is connected with the second-stage sub-analog-to-digital converter, the first-stage sub-analog-to-digital converter and the second-stage sub-analog-to-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter are also connected with the dynamic comparator respectively, a residual amplifier RA and a digital calibration module are further arranged on a circuit connecting the first-stage sub analog-to-digital converter and the second-stage sub analog-to-digital converter, one end of the residual amplifier is connected with the first-stage sub analog-to-digital converter through a first switch S DMC1, and the other end of the residual amplifier is connected with the second-stage sub analog-to-digital converter through a second switch S DMC2.
As shown in fig. 2, in the present embodiment, the first-stage sub-analog-to-digital converter has the following structure:
A forward capacitor array including 13 capacitors CP12-CP0 and 1 matching capacitor CP (black dots in the figure represent omitted capacitors CP 1-CP 3, CP 7-CP 10); wherein, the 8 capacitors CP12-CP5 are taken as a first group, and the capacitance values are sequentially reduced from CP12 to CP 5; the remaining capacitances CP4-CP0 are used as the second group, with the capacitance decreasing in sequence from CP4 to CP 0. The lower stage plate of the forward capacitor array is connected with the differential input voltage VP, and the upper stage plate is connected with one end of the forward control switch group SP12-SP 0; the other end of the control switch set SP12-SP0 will be selectively connected to either the reference voltage (VR or VR 1) or Ground (GND) as controlled by SAR logic.
A negative-going capacitor array including 13 capacitors CN12-CN0 and 1 matching capacitor CN (the black dots in the figure represent omitted capacitors CN 1-CN 3, CN 7-CN 10)); wherein, CN12-CN5 are taken as a first group, and the capacitance values are sequentially reduced from CN12 to CN 5; the remaining capacitances CN4-CN0 are taken as a second group, and the capacitance values are sequentially reduced from CN4 to CN 0; the lower plate of the negative capacitor array is connected with the differential input voltage VN, and the upper plate is connected with one end of the positive control switch group SN12-SN 0; the other end of the control switch set SN12-SN0 will be selectively connected to a reference voltage (VR or VR 1) or Ground (GND) as controlled by SAR logic.
The first-stage sub-analog-digital converter is also connected with a dynamic comparator, and the dynamic comparator is used for comparing the voltage values of the lower plates of the capacitors controlled by the SAR logic circuit, so that an output value is generated and then enters the SAR logic circuit.
In the first stage sub-ADC, the capacitance value of the first 8 capacitors CP12-CP5 (or CN12-CN 5) is CPi=2 (i-5) C, and the connected reference voltage is VR; the remaining 5 capacitors CP4-CP1 (or CN4-CN 1) have a capacitance value of cpci=2 (i-1) C, CP 0=cp 1 and are connected with a reference voltage of vr1=vr/8.
The matched capacitance CP (or CN) is 17C in size, and the steps in performing the first 14-bit conversion process include the following two phases:
the first stage, the positive and negative capacitance array lower plate is connected to the differential input voltages VP and VN, the upper plate switch is connected to VR or VR1 for sampling, so that the capacitance is charged;
In the second stage, the lower plate switch is disconnected and is in a virtual empty state, the upper plate switch is unchanged and is in a holding state, and total charges are redistributed due to different values of VR and VR1, so that the voltage calculation formula of the lower plate is as follows:
According to the above formula, the VP and VN sizes can be compared.
In the third stage, when VP > VN, the upper plate of the first capacitor CP12 in the forward capacitor array is connected to GND, the on-off state of the lower plate capacitor is kept unchanged, and at this time, the forward capacitor array will perform the capacitor distribution, and at this time, the voltage of the lower plate of the forward capacitor array changes:
The voltage of the lower plate of the negative capacitor array is unchanged, and V P-VN can be obtained Is a size relationship of (2); when (when)Comparator output 1 when/>, whenWhen the comparator outputs 0.
Fourth stage, after the third stage, V P-VN andIf the magnitude relation of (C) is when/>Next, the upper plate of the second capacitor CP11 of the forward capacitor array is connected to GND, and then:
At this time, V P-VN and V P-VN can be obtained Is a size relationship of (2);
If when it is Next, the upper plate of the second capacitor CN11 of the negative capacitor array is connected to the ground GND, and then:
At this time, V P-VN and V P-VN can be obtained Is a size relationship of (a).
The capacitances of the remaining capacitor array are cycled through the above steps until the comparator CP0 or CN0 upper plate is connected to ground GND, which results in the comparator output, at which time the first 14 bits of value conversion is complete. The upper plates of the matched capacitors CP and CN will remain connected to VR at all times during the conversion process.
As shown in fig. 3, in the present embodiment, the structure of the second-stage sub-analog-digital converter is as follows:
A forward capacitor array comprising 8 capacitors CP7-CP0; the capacitor array structure is of a traditional structure, a lower plate of the capacitor array is connected with the differential input voltage VP, and an upper plate of the capacitor array is connected with one end of the forward control switch group SP7-SP 0; the other end of the control switch group SP7-SP0 is selectively connected with a reference voltage or a ground line through the control of the SAR logic circuit.
A negative-going capacitor array comprising 8 capacitors CN7-CN0; the capacitor array structure is of a traditional structure, a lower plate of the capacitor array is connected with the differential input voltage VN, and an upper plate of the capacitor array is connected with one end of the forward control switch group SN7-SN 0; the other end of the control switch set SN7-SN0 is selectively connected to a reference voltage or ground, as controlled by SAR logic.
The second-stage sub-analog-digital converter is also connected with a dynamic comparator, and the dynamic comparator is used for comparing the voltage values of the lower plates of the capacitors controlled by the SAR logic circuit, so that an output value is generated and then enters the SAR logic circuit. The circuit operation process of the second-stage sub-analog-digital converter is similar to that of the first-stage sub-analog-digital converter, and the second-stage sub-analog-digital converter comprises sampling, holding and comparing and outputting digital codes bit by bit.
Before entering the second-stage sub-analog-digital converter, the differential output residual signals of the first-stage sub-analog-digital converter are required to be recovered in proportion through a residual amplifier, and then the recovered signals are sent into a capacitor array for comparison. And finally, combining the two-stage sub analog-digital converters to obtain a 22-bit digital code to represent the value of the input level. And then converting the parallel data into serial data through an interface circuit and outputting the serial data.
Claims (1)
1. The utility model provides a high accuracy two-step formula successive approximation register analog-to-digital converter, includes sample hold circuit, second level submodule-to-digital converter, successive approximation register logic circuit, parallel to serial interface circuit, its characterized in that: the first stage sub analog-to-digital converter is also included; the sampling hold circuit is connected with the first-stage sub-analog-digital converter, the first-stage sub-analog-digital converter is connected with the second-stage sub-analog-digital converter, the first-stage sub-analog-digital converter and the second-stage sub-analog-digital converter are respectively connected with the successive approximation register logic circuit, the successive approximation register logic circuit is connected with the parallel-to-serial interface circuit, the first-stage sub-analog-digital converter and the second-stage sub-analog-digital converter are respectively connected with the dynamic comparator, a residual amplifier and a digital calibration module are further arranged on the circuit connecting the first-stage sub-analog-digital converter and the second-stage sub-analog-digital converter, one end of the residual amplifier is connected with the first-stage sub-analog-digital converter through a first switch, and the other end of the residual amplifier is connected with the second-stage sub-analog-digital converter through a second switch;
The first-stage sub-analog-digital converter comprises a positive capacitor array consisting of 14 capacitors, a negative capacitor array consisting of 14 capacitors and a comparator; in the positive capacitor array and the negative capacitor array, the first 8 capacitors are divided into one group, the last five capacitors are divided into the other group, and one capacitor is used as a matched capacitor; the lower plate of the capacitor is connected to the differential input voltage, the upper plate of the capacitor is selectively connected to the reference voltage or the ground through an analog switch, and the capacitor has two reference voltages, one is used as the reference voltage of the first 8 capacitors, and the other is used as the reference voltage of the last five capacitors; the upper plate of the matched capacitor is connected with the reference voltages of the first 8 capacitors; the comparator outputs signals by comparing the differential input voltage of the lower plate of the positive capacitor array with the differential input voltage of the lower plate of the negative capacitor array;
The second-stage sub-analog-digital converter comprises a positive capacitor array formed by 8 capacitors, a negative capacitor array formed by 8 capacitors and a comparator; the lower plate of the capacitor is connected to the differential input voltage and has a reference voltage, and the upper plate is selectively connected to the reference voltage or ground through an analog switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011509041.5A CN112600560B (en) | 2020-12-18 | 2020-12-18 | High-precision two-step successive approximation register analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011509041.5A CN112600560B (en) | 2020-12-18 | 2020-12-18 | High-precision two-step successive approximation register analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112600560A CN112600560A (en) | 2021-04-02 |
| CN112600560B true CN112600560B (en) | 2024-04-30 |
Family
ID=75199527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011509041.5A Active CN112600560B (en) | 2020-12-18 | 2020-12-18 | High-precision two-step successive approximation register analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112600560B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113315519B (en) * | 2021-06-10 | 2024-04-02 | 裕太微电子股份有限公司 | Successive comparison type analog-to-digital converter |
| CN114499529B (en) * | 2022-04-01 | 2022-07-19 | 浙江地芯引力科技有限公司 | Analog-digital converter circuit, analog-digital converter, and electronic apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107947796A (en) * | 2017-10-24 | 2018-04-20 | 西安电子科技大学 | The two-step successive approximation analog to digital C differentiated based on threshold value |
| CN109474278A (en) * | 2018-09-19 | 2019-03-15 | 西安电子科技大学 | Super low-power consumption gradual approaching A/D converter based on Charge scaling |
| CN112019217A (en) * | 2020-10-16 | 2020-12-01 | 浙江大学 | Pipelined successive approximation analog-to-digital converter and conversion method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7405689B2 (en) * | 2005-01-05 | 2008-07-29 | Exar Corporation | Predictive analog to digital converters and methods of using |
-
2020
- 2020-12-18 CN CN202011509041.5A patent/CN112600560B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107947796A (en) * | 2017-10-24 | 2018-04-20 | 西安电子科技大学 | The two-step successive approximation analog to digital C differentiated based on threshold value |
| CN109474278A (en) * | 2018-09-19 | 2019-03-15 | 西安电子科技大学 | Super low-power consumption gradual approaching A/D converter based on Charge scaling |
| CN112019217A (en) * | 2020-10-16 | 2020-12-01 | 浙江大学 | Pipelined successive approximation analog-to-digital converter and conversion method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112600560A (en) | 2021-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108574487B (en) | Successive approximation register analog-to-digital converter | |
| US8310388B2 (en) | Subrange analog-to-digital converter and method thereof | |
| TWI467924B (en) | Successive approximation register analog to digital converter and conversion method thereof | |
| CN109120268B (en) | Dynamic comparator offset voltage calibration method | |
| CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
| CN103152049A (en) | Successive approximation register type ADC (analog-digital converter) | |
| CN112600560B (en) | High-precision two-step successive approximation register analog-to-digital converter | |
| CN107346975B (en) | SAR type ADC's high accuracy calibrating device | |
| CN111446964B (en) | Novel fourteen-bit pipeline-successive approximation type analog-to-digital converter | |
| CN109379082B (en) | Successive approximation analog-to-digital converter | |
| CN111327324B (en) | Capacitor array structure suitable for successive approximation type analog-to-digital converter | |
| CN111934689B (en) | High-precision analog-to-digital converter and conversion method | |
| CN111756380A (en) | Two-step successive approximation type analog-to-digital converter sharing bridge capacitor array | |
| KR20190071536A (en) | Successive approximation register analog digital converter and operating method thereof | |
| CN112290945B (en) | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC | |
| CN112688688B (en) | Pipeline analog-to-digital converter based on partition type and successive approximation register assistance | |
| CN109245771B (en) | Successive approximation type digital-to-analog converter | |
| CN110198167B (en) | Asymmetric SAR ADC capacitance switch sequential circuit and method | |
| CN109768800B (en) | Ultralow-power-consumption successive approximation type analog-to-digital converter based on charge redistribution | |
| CN109039338B (en) | Differential capacitor array and switch switching method thereof | |
| CN115473533B (en) | FLASH-SAR ADC conversion method and circuit | |
| TWI763525B (en) | Analog-to-digital converter and method of operating same | |
| CN107517059B (en) | Circuit and method for improving conversion speed of analog-to-digital converter | |
| CN113542642B (en) | Analog-to-digital converter for locally generating reference voltage of sub-digital-to-analog converter | |
| CN110071720B (en) | Self-calibrating full-capacitance successive approximation digital-to-analog conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |