CN113315519B - Successive comparison type analog-to-digital converter - Google Patents
Successive comparison type analog-to-digital converter Download PDFInfo
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- CN113315519B CN113315519B CN202110649907.0A CN202110649907A CN113315519B CN 113315519 B CN113315519 B CN 113315519B CN 202110649907 A CN202110649907 A CN 202110649907A CN 113315519 B CN113315519 B CN 113315519B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention discloses a successive comparison type analog-to-digital converter, which belongs to the field of integrated circuit design and comprises the following components: the first logic device comprises a first pre-stage capacitor and a first redundant capacitor, wherein one end of the first pre-stage capacitor and one end of the first redundant capacitor are switched among a positive input signal, a reference voltage and a grounding end, and the other end of the first pre-stage capacitor and one end of the first redundant capacitor are connected to a first node; each stage of second logic device comprises a second pre-stage capacitor and a second redundant capacitor, one ends of the second pre-stage capacitor and the second redundant capacitor are switched among a negative input signal, a reference voltage and a grounding end, and the other ends of the second pre-stage capacitor and the second redundant capacitor are connected to a second node; the comparator is used for comparing the voltage of the first node with the voltage of the second node. The invention has the beneficial effects that: a redundant capacitor is added to each stage of preceding-stage capacitor, and successive approximation comparison is performed based on a binary search algorithm, so that the charge quantity carried in each successive comparison period is equal to an ideal value, and the accuracy of the converter is improved.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a successive comparison type analog-to-digital converter.
Background
Analog-to-digital converters (Analog to Digital Converter, ADC) are an indispensable conversion circuit in modern electronic systems, and are the front-ends of various digital systems, whose performance is crucial. Wherein successive approximation register analog-to-digital converters (SAR ADCs) occupy a large portion of the medium to high resolution ADC market. SAR ADC is widely used in low-power consumption electronic equipment due to its simple structure, few analog modules, small area, low power consumption and benefits from small-size advanced integrated circuit process.
Successive approximation analog-to-digital converter (SAR ADC) based on binary search algorithm successively approximates input analog signal, wherein most of the inside is capacitor array as sampling stage capacitor and DAC of switchable voltage of successive comparison stage, which can be divided into sampling, zero clearing stage and successive comparison stage; due to the reference voltage V in the actual circuit r And GND is not an ideal value, and the voltage is relatively stable all the time in the sampling and zero clearing stage; however, in the successive comparison stage, since the capacitor channels are all electrified to generate strong impulse response, voltage is reduced, decision accuracy of the comparator and the number of effective bits of the whole analog-digital converter are directly reduced, binary relation is destroyed, the accuracy of the converter is reduced, and the performance of the SAR ADC is seriously deteriorated, so that the successive comparison analog-digital converter is urgently required to be designed to meet the requirement of actual use.
Disclosure of Invention
The invention aims to provide a successive comparison type analog-digital converter, wherein a redundant capacitor is added beside a front-stage capacitor of a logic device, so that the charge quantity carried in each successive comparison period is equal to an ideal value, and the accuracy of the converter is improved.
The technical problems solved by the invention can be realized by adopting the following technical scheme:
the invention provides a successive approximation analog-to-digital converter, comprising:
the first logic device comprises a first pre-stage capacitor and a first redundant capacitor, wherein the first logic device generates a first control signal under the action of a first comparison signal and is used for controlling one ends of the first pre-stage capacitor and the first redundant capacitor to be switched among a positive input signal, a reference voltage and a grounding end, and the other ends of the first pre-stage capacitor and the first redundant capacitor are connected to a first node;
the second logic device comprises a second pre-stage capacitor and a second redundant capacitor, and the second logic device generates a second control signal under the action of a second comparison signal and is used for controlling one ends of the second pre-stage capacitor and the second redundant capacitor to be switched among a negative input signal, the reference voltage and the grounding end, and the other ends of the second pre-stage capacitor and the second redundant capacitor are connected to a second node;
and the comparator is used for comparing the voltage of the first node with the voltage of the second node and outputting the first comparison signal or the second comparison signal.
Preferably, each stage of the first logic and the second logic further includes:
the control end is used for receiving the first comparison signal or the second comparison signal and generating the first control signal or the second control signal under the action of the first comparison signal or the second comparison signal.
Preferably, each stage of the first logic and the second logic further includes:
an enabling end, configured to receive an enabling signal of the first logic device or the second logic device of a previous stage;
and the output end is used for generating the enabling signal and outputting the enabling signal to the enabling end of the first logic device or the second logic device at the subsequent stage while the control end outputs the first control signal or the second comparison signal.
Preferably, the first logic device or the second logic device of the previous stage outputs a feedback signal to the first logic device or the second logic device of the previous stage while outputting the enable signal to the first logic device or the second logic device of the next stage;
the first logic device or the second logic device of the previous stage receives the feedback signal and generates the first control signal or the second control signal under the action of the feedback signal.
Preferably, after the first logic device or the second logic device receives the feedback signal, the first redundant capacitor is switched from the reference voltage to the ground terminal under the action of the first control signal or the second control signal.
Preferably, the method further comprises:
and the switching device group is connected between a common mode voltage and the comparator and used for controlling the successive comparison type analog-digital converter to alternately switch between a sampling function mode and a successive comparison mode.
Preferably, the switching device group includes:
a first main switch connected between the common mode voltage and the first node;
and a second main switch connected between the common mode voltage and the second node.
Preferably, the non-inverting input terminal of the comparator is connected to the first node, and the inverting input terminal of the comparator is connected to the second node.
Preferably, the first logic device and the second logic device are respectively SAR logic circuits.
Preferably, the comparator outputs the first comparison signal when the voltage of the first node is greater than the voltage of the second node;
when the voltage of the first node is smaller than the voltage of the second node, the comparator outputs the second comparison signal.
The technical scheme of the invention has the beneficial effects that:
in the invention, a redundant capacitor is added to the front-stage capacitor of each first-stage logic device and each second-stage logic device, the first logic device or the second logic device is determined and controlled according to the comparison signal output by the comparator based on the successive approximation comparison of the binary search algorithm, the front-stage capacitor and the redundant capacitor corresponding to the first logic device or the second logic device are controlled to be switched from the reference voltage to the grounding terminal, the next-stage logic device is enabled, and the redundant capacitor of the previous-stage logic device is controlled to be switched from the grounding terminal to the reference voltage while the next-stage logic device is enabled by the previous-stage logic device, so that the charge quantity carried in each successive comparison period is equal to the ideal value, and the precision of the converter is improved.
Drawings
Fig. 1 is a schematic circuit diagram of a successive approximation analog-to-digital converter according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention provides a successive comparison type analog-to-digital converter, which belongs to the field of integrated circuit design, as shown in figure 1, and comprises:
the first logic device comprises a first pre-stage capacitor and a first redundant capacitor, and the first logic device generates a first control signal under the action of a first comparison signal for controlling one ends of the first pre-stage capacitor and the first redundant capacitor to be in a positive input signal V inp A reference voltage V r The other ends of the first front-stage capacitor and the first redundant capacitor are connected to a first node;
the second logic device (21#, 22#, 23# …) comprises a second pre-stage capacitor and a second redundancy capacitor, and generates a second control signal under the action of a second comparison signal for controlling one ends of the second pre-stage capacitor and the second redundancy capacitor to be in a negative input signal V inn Reference voltage V r The other ends of the second pre-stage capacitor and the second redundant capacitor are connected to a second node;
and a comparator 1 for comparing the voltage of the first node with the voltage of the second node and outputting a first comparison signal or a second comparison signal.
Specifically, in the present embodiment, the successive approximation analog-to-digital converter includes:
a plurality of first pre-capacitors (C11, C12, C13, …), each having one end connected to the first node and the other end connected to the positive input signal V of the corresponding first logic inp Or reference voltage V r Or the ground GND, which controls the first pre-capacitor to the positive input signal V under the first control signal inp Reference voltage V r And a ground GND;
a plurality of second pre-capacitors (C21, C22, C23, …), each having one end connected to the second node and the other end connected to the negative input signal V of the corresponding second logic inn Or reference voltage V r Or the ground GND, which controls the second pre-capacitor to the negative input signal V under the second control signal inn Reference voltage V r And a ground GND;
further comprises: first redundant capacitors (delta C11, delta C12, delta C13 …) corresponding to each first preceding capacitor (C11, C12, C13 …) one by one, one end of each first redundant capacitor being connected to the first node, the other end of each first redundant capacitor being connected to the positive input signal V under the control of the first control signal inp Or reference voltage V r Or switch between ground GND;
second redundant capacitors (delta C21, delta C22, delta C23 …) corresponding to the second preceding capacitors (C21, C22, C23 …) one by one, one end of each second redundant capacitor being connected to the second node, the other end of each second redundant capacitor being connected to the negative input signal V under the control of the second control signal inn Or reference voltage V r Or switch between ground GND;
a redundant capacitor is added beside each first pre-capacitor and each second pre-capacitor, the voltage of the first node and the voltage of the second node are compared successively by the comparator 1 based on successive approximation comparison of a binary search algorithm, and capacitor switching is controlled according to an output comparison signal, so that the charge quantity carried in each successive comparison period is equal to an ideal value, for example: the charge amount q=c11×v= (c11+Δc11) v×0.9 in the first stage transfer.
To overcome ADC reference voltage V r Non-ideal characteristics due to current surge during successive comparisons (e.g. V during first and second stage comparisons r From ideal 1V down to 0.9V, 0.95V, and gradually back to 1V after the third and fourth stage comparisons), a redundant capacitor is added to each stage to make the total charge per transfer equal to the ideal value (i.e., an extra deltac is used to complement V r And an ideal value of 1V, such that the total amount of q=c×v remains constant).
As a preferred embodiment, each stage of the first logic and the second logic further includes:
the control end J1 is used for receiving the first comparison signal or the second comparison signal and generating a first control signal or a second control signal under the action of the first comparison signal or the second comparison signal.
Specifically, each stage of the first logic device further includes a control end J1, configured to receive the first comparison signal, and generate a first control signal under the action of the first comparison signal;
the second logic device also comprises a control end J1 respectively for receiving the second comparison signals and generating second control signals under the action of the second comparison signals.
Further, the method further comprises the following steps:
one end of each upper plate capacitance switch is correspondingly connected with the first front-stage capacitance or the first redundant capacitance, and the other end is controlled by the first control signal to be in positive input signal V inp Or reference voltage V r Or switch between ground GND;
one end of each lower-stage plate capacitance switch is correspondingly connected with a second front-stage capacitance or a second redundant capacitance, and the other end is controlled by a second control signal to be in a negative input signal V inn Or reference voltage V r Or switch between ground GND.
As a preferred embodiment, each stage of the first logic and the second logic further includes:
an enable terminal J3 for receiving an enable signal of the first logic device or the second logic device of the previous stage;
an output terminal J4 for generating an enable signal while the control terminal J1 outputs the first control signal or the second comparison signal, and outputting the enable signal to the enable terminal J3 of the first logic device or the second logic device of the subsequent stage.
As a preferred embodiment, the first logic device or the second logic device of the previous stage outputs a feedback signal to the first logic device or the second logic device of the previous stage while outputting an enable signal to the first logic device or the second logic device of the next stage;
the first logic device or the second logic device of the previous stage receives the feedback signal and generates a first control signal or a second control signal under the action of the feedback signal.
Specifically, the logic is receivingAfter comparing the signals, a control signal for controlling the capacitance switch is output, and the latter stage logic is enabled, and a feedback signal is output to the feedback terminal J2 to the former stage logic, for example, when the comparator output is 1, i.e. the first comparison signal, the logic 12# receives the first comparison signal and outputs the first control signal, and the upper stage plate capacitance switch corresponding to the capacitance C12 and the capacitance DeltaC 12 is controlled by the reference voltage V r Switching to the ground end GND, enabling the logic device 13# at the next stage, outputting the feedback signal to the logic device 11# at the previous stage, and switching the upper plate capacitance switch corresponding to the corresponding capacitor Δc11 from the ground end GND to the reference voltage V after the logic device 11# receives the feedback signal at the feedback end J2 r 。
In a preferred embodiment, the first logic or the second logic receives the feedback signal and then uses the first control signal or the second control signal to drive the first redundancy capacitor from the reference voltage V r Switch to ground GND.
As a preferred embodiment, further comprising:
and a switching device group connected between a common mode voltage and the comparator 1 for controlling the successive comparison type analog-digital converter to alternately switch between the sampling function mode and the successive comparison mode.
As a preferred embodiment, the switching device group includes:
a first main switch L1, the first main switch L1 being connected between the common-mode voltage Vcm and the first node;
and a second main switch connected between the common mode voltage Vcm and the second node.
Further, when the successive approximation type analog-to-digital converter is in the sampling function mode, the first main switch L1 and the second main switch L2 are both closed, and all the first pre-capacitors and all the first redundant capacitors are switched to the positive input signal V inp All the second pre-capacitors and all the second redundant capacitors are switched to the negative input signal V inn ；
When the successive approximation analog-to-digital converter is in the successive approximation mode, the first main switch L1 and the second main switch L2 are both turned off, and all the preceding stages are powered onThe capacitor and the redundant capacitor are switched to be connected with the reference signal, and the first control signal controls the first pre-capacitor and the first redundant capacitor to be at the reference voltage V r And a ground GND; or controlling the second pre-capacitor and the second redundant capacitor to the reference voltage V under the second control signal r And a ground GND.
As a preferred embodiment, the non-inverting input of the comparator 1 is connected to a first node and the inverting input of the comparator 1 is connected to a second node.
As a preferred embodiment, when the voltage of the first node is greater than the voltage of the second node, the comparator 1 outputs a first comparison signal;
when the voltage of the first node is smaller than the voltage of the second node, the comparator 1 outputs a second comparison signal.
As a preferred embodiment, the first logic device (11#, 12#, 13# …) and the second logic device (21#, 22#, 23# …) are SAR logic circuits, respectively.
The technical scheme of the invention has the beneficial effects that:
in the invention, a redundant capacitor is added to the front-stage capacitor of each first-stage logic device and each second-stage logic device, the first logic device or the second logic device is determined and controlled according to the comparison signal output by the comparator based on the successive approximation comparison of the binary search algorithm, the front-stage capacitor and the redundant capacitor corresponding to the first logic device or the second logic device are controlled to be switched from the reference voltage to the grounding terminal, the next-stage logic device is enabled, and the redundant capacitor of the previous-stage logic device is controlled to be switched from the grounding terminal to the reference voltage while the next-stage logic device is enabled by the previous-stage logic device, so that the charge quantity carried in each successive comparison period is equal to the ideal value, and the precision of the converter is improved.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included within the scope of the present invention.
Claims (8)
1. A successive approximation analog-to-digital converter, comprising:
the first logic device comprises a first pre-stage capacitor and a first redundant capacitor, wherein the first logic device generates a first control signal under the action of a first comparison signal and is used for controlling one ends of the first pre-stage capacitor and the first redundant capacitor to be switched among a positive input signal, a reference voltage and a grounding end, and the other ends of the first pre-stage capacitor and the first redundant capacitor are connected to a first node;
the second logic device comprises a second pre-stage capacitor and a second redundant capacitor, and the second logic device generates a second control signal under the action of a second comparison signal and is used for controlling one ends of the second pre-stage capacitor and the second redundant capacitor to be switched among a negative input signal, the reference voltage and the grounding end, and the other ends of the second pre-stage capacitor and the second redundant capacitor are connected to a second node;
a comparator for comparing the voltage of the first node with the voltage of the second node and outputting the first comparison signal or the second comparison signal;
each stage of the first logic device and the second logic device further comprises:
the control end is used for receiving the first comparison signal or the second comparison signal and generating the first control signal or the second control signal under the action of the first comparison signal or the second comparison signal;
each stage of the first logic device and the second logic device further comprises:
an enabling end, configured to receive an enabling signal of the first logic device or the second logic device of a previous stage;
and the output end is used for generating the enabling signal and outputting the enabling signal to the enabling end of the first logic device or the second logic device at the subsequent stage while the control end outputs the first control signal or the second control signal.
2. The analog-to-digital converter of claim 1, wherein said first logic or said second logic of the previous stage outputs a feedback signal to said first logic or said second logic of the previous stage while outputting said enable signal to said first logic or said second logic of the next stage;
the first logic device or the second logic device of the previous stage receives the feedback signal and generates the first control signal or the second control signal under the action of the feedback signal.
3. The analog-to-digital converter of claim 2, wherein the first logic or the second logic switches the first redundancy capacitor from the reference voltage to the ground under the action of the first control signal or the second control signal after receiving the feedback signal.
4. The successive approximation analog-to-digital converter of claim 1, further comprising:
and the switching device group is connected between a common mode voltage and the comparator and used for controlling the successive comparison type analog-digital converter to alternately switch between a sampling function mode and a successive comparison mode.
5. The successive approximation analog-to-digital converter of claim 4, wherein the switching device group comprises:
a first main switch connected between the common mode voltage and the first node;
and a second main switch connected between the common mode voltage and the second node.
6. The successive approximation analog-to-digital converter of claim 1, wherein a non-inverting input of the comparator is connected to the first node and an inverting input of the comparator is connected to the second node.
7. The analog-to-digital converter of claim 1, wherein said first logic and said second logic are SAR logic circuits, respectively.
8. The successive approximation analog-to-digital converter according to claim 1, wherein the comparator outputs the first comparison signal when the voltage at the first node is greater than the voltage at the second node;
when the voltage of the first node is smaller than the voltage of the second node, the comparator outputs the second comparison signal.
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| US9608656B2 (en) * | 2015-07-30 | 2017-03-28 | National University Of Singapore | Symmetrical capacitor arrays succesive approximation register (SAR) analog-to-digital converter (ADC) |
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