CN112540732A - Data processing method and related product - Google Patents
Data processing method and related product Download PDFInfo
- Publication number
- CN112540732A CN112540732A CN202011541455.6A CN202011541455A CN112540732A CN 112540732 A CN112540732 A CN 112540732A CN 202011541455 A CN202011541455 A CN 202011541455A CN 112540732 A CN112540732 A CN 112540732A
- Authority
- CN
- China
- Prior art keywords
- memory
- data
- state
- written
- storage area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Read Only Memory (AREA)
Abstract
The embodiment of the application discloses a data processing method and a related product, wherein the method comprises the following steps: controlling a chip selection signal corresponding to the first memory to be in a first state; writing data to the first memory at least once; and controlling a chip selection signal corresponding to the first memory to be in a second state, wherein the chip selection signal with the signal state being in the second state is used for indicating the first memory to latch the written data. The embodiment of the application is beneficial to improving the data writing efficiency.
Description
Technical Field
The present application relates to the field of data processing, and in particular, to a data processing method and related products.
Background
SPI (serial peripheral interface) is a serial interface device, and SPI flash is a flash storage device that operates through a serial interface. At present, an SPI flash is generally used for data storage or code running, and when program codes are run or data types such as audio, video, image and the like are stored using the SPI flash, since a write enable operation is performed before writing data each time, writing data is performed next time after waiting for completion of a write-once state after writing data each time, the data writing process takes a long time, and it is difficult to meet the requirements of a low-latency and high-writing-speed scene.
Disclosure of Invention
The embodiment of the application provides a data processing method and a related product, so as to improve the data writing efficiency.
In a first aspect, an embodiment of the present application provides a data processing method, which is applied to an electronic device, and the method includes:
controlling a chip selection signal corresponding to the first memory to be in a first state;
writing data to the first memory at least once;
and controlling a chip selection signal corresponding to the first memory to be in a second state, wherein the chip selection signal with the signal state being in the second state is used for indicating the first memory to latch the written data.
In a second aspect, an embodiment of the present application provides a data processing apparatus, which is applied to an electronic device, and the apparatus includes:
the first control unit is used for controlling the chip selection signal corresponding to the first memory to be in a first state;
a write unit for writing data to the first memory at least once;
and the second control unit is used for controlling a chip selection signal corresponding to the first memory to be in a second state, and the chip selection signal with the signal state being in the second state is used for indicating the first memory to latch the written data.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps in the first aspect of the embodiment of the present application.
In a fourth aspect, an embodiment of the present application provides a computer storage medium storing a computer program for electronic data exchange, where the computer program makes a computer perform some or all of the steps described in the first aspect of the present embodiment.
In a fifth aspect, embodiments of the present application provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in the first aspect of the embodiments of the present application. The computer program product may be a software installation package.
In the embodiment of the application, the electronic device first controls the chip select signal corresponding to the first memory to be in the first state, then at least once writing data into the first memory, finally controlling the chip selection signal corresponding to the first memory to be in a second state, wherein the chip select signal with the signal state of the second state is used for indicating the first memory to latch the written data, it can be seen that when the electronic device writes data into the first memory at least once, the write enable operation is not performed until the next data writing after each data writing, and the chip select signal corresponding to the first memory is controlled to be in the second state after the data is written at least once, the first memory latches the data written at least once after the data is written at least once, so that the time for enabling the data to be written and waiting for the completion of the last writing state before the data is written is reduced, and the data writing efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1A is an exemplary diagram of an application scenario provided in an embodiment of the present application;
fig. 1B is a diagram illustrating an exemplary composition of an electronic device according to an embodiment of the present disclosure;
fig. 2A is a schematic flowchart of a data processing method according to an embodiment of the present application;
FIG. 2B is a schematic flow chart diagram illustrating another data processing method according to an embodiment of the present disclosure;
fig. 3A is a block diagram of functional units of a data processing apparatus according to an embodiment of the present application;
fig. 3B is a block diagram of functional units of another data processing apparatus according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Embodiments of the present application will be described below with reference to the drawings.
Referring to fig. 1A, fig. 1A is an exemplary diagram of an application scenario provided in an embodiment of the present application, a data processing method described in the present application may be applied to an electronic device 100, and a processor inside the electronic device 100 may perform any step performed by the electronic device in the following method embodiments, where, as shown in part (a) in fig. 1A, the first memory may be a memory disposed on the electronic device 100, or, as shown in part (b) in fig. 1A, the first memory may be a memory disposed on another electronic device, such as an application device 200. Specifically, the first memory may be an SPI flash, and the processor of the electronic device 100 may communicate with and write data to the first memory.
Referring to fig. 1B, a composition structure of the electronic device 100 provided in the embodiment of the present application may be as shown in fig. 1B, where the electronic device 100 includes a processor 110, a memory 120, a communication interface 130, and one or more programs 121, where the one or more programs 121 are stored in the memory 120 and configured to be executed by the processor 110, and the one or more programs 121 include instructions for executing any step of the method embodiments described below.
The communication interface 130 is used for supporting communication between the electronic device and other devices. The Processor 110 may be, for example, a Central Processing Unit (CPU), a general purpose Processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, units, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others.
The memory 120 may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct bus RAM (DR RAM).
When the first memory is an internal memory of the electronic device 100, the first memory may be the memory 120, and specifically, may be an SPI flash.
In a specific implementation, the processor 110 is configured to perform any one of the steps performed by the electronic device in the method embodiments described below, and when performing data transmission such as sending, optionally invokes the communication interface 130 to complete the corresponding operation.
It should be noted that the structural diagram of the electronic device 100 is merely an example, and more or fewer devices may be specifically included, which is not limited herein.
Referring to fig. 2A, fig. 2A is a schematic flowchart of a data processing method according to an embodiment of the present application, where the method can be applied to the electronic device shown in fig. 1A, and as shown in fig. 2A, the data processing method includes the following steps:
s201, the electronic device controls the chip selection signal corresponding to the first memory to be in a first state.
The first memory may be an SPI flash inside the electronic device. Specifically, the chip select signal corresponding to the first memory may be controlled to be in the first state, and the chip select signal corresponding to the first memory may be pulled low. When the electronic device needs to write data into the first memory, the processor may control to pull down a signal of a CS pin, i.e., a chip select pin, of the first memory before writing the data, so that the first memory is in an operating mode.
S202, the electronic equipment writes data into the first memory at least once.
In a specific implementation, the electronic device may write data to the first memory for multiple times continuously, where each time data is written, the written data may include a data writing instruction, a data writing address, and data used for writing in a storage area in the memory, and the electronic device may write the data written each time into a buffer area in the memory.
S203, the electronic device controls the chip selection signal corresponding to the first memory to be in a second state.
Wherein the chip select signal whose signal state is the second state is used to instruct the first memory to latch the data being written.
In a specific implementation, after the processor of the electronic device completes writing data into the first memory, the chip select signal corresponding to the first memory may be controlled to be in the second state, specifically, the chip select signal corresponding to the first memory may be pulled high. After the chip select signal corresponding to the first memory is pulled high, the first memory can latch the data in the one or more write buffers into the corresponding storage area (i.e., the storage area indicated by the data write address) at the same time, and compared with latching the data into the corresponding storage area after writing the data into the buffer each time, the time for waiting for the completion of the write state of the first memory between data writes is reduced, i.e., the time for waiting for the completion of the last write state (the process for latching the data in the buffer into the corresponding storage area) when writing the data each time is not needed.
In the embodiment of the application, the electronic device first controls the chip select signal corresponding to the first memory to be in the first state, then at least once writing data into the first memory, finally controlling the chip selection signal corresponding to the first memory to be in a second state, wherein the chip select signal with the signal state of the second state is used for indicating the first memory to latch the written data, it can be seen that when the electronic device writes data into the first memory at least once, the write enable operation is not performed until the next data writing after each data writing, and the chip select signal corresponding to the first memory is controlled to be in the second state after the data is written at least once, the first memory latches the data written at least once after the data is written at least once, so that the time for enabling the data to be written and waiting for the completion of the last writing state before the data is written is reduced, and the data writing efficiency is improved.
In one possible example, the data includes data for writing to a first storage area in the first memory; the controlling the chip selection signal corresponding to the first memory to be in a second state includes: and when the written data length information of the first storage area is detected to be not less than a first preset threshold value, controlling the chip selection signal corresponding to the first storage to be in a second state.
The written data length information may be a specific value of the written data length.
In a specific implementation, the SPI flash may support data writing in a page unit, that is, page programming, so that the electronic device may write data into a corresponding page in the first memory by using a page programming method, and write byte data Wlen _ max of 256 bytes at most under a page programming instruction.
The first storage area may be a buffer area in the first memory, and the first preset threshold may be 256 bytes. That is to say, when the electronic device writes data into the first memory by using the page programming method, and detects that the written data length information in the buffer is not less than 256 (that is, the value of the written data length is greater than or equal to the maximum data length value allowed to be written), the chip select signal corresponding to the first memory may be controlled to be in the second state, the writing of data into the buffer of the first memory is finished, and the first memory latches the data written into the buffer, that is, the data written into the buffer is stored into the page corresponding to the page write address.
In this example, when detecting that the length information of the written data in the first storage area is not less than the first preset threshold, the electronic device controls the chip select signal corresponding to the first memory to be in the second state, and when the length information exceeds the first preset threshold, that is, the number of bytes allowed to be written, the electronic device does not write data into the first memory any more, and the first memory latches the written data together, which is beneficial to improving the data writing efficiency.
In one possible example, in the at least one writing of data to the first memory, each time after the writing of data to the first memory, the method further includes: and updating the written data length information of the first storage area, wherein the written data length information of the first storage area after each updating is not zero.
In a specific implementation, since the data written into the memory is data for writing into the first storage area in the first memory, the written data length information of the first storage area can be updated after the data is written into the memory each time, so as to control the chip select signal of the first memory according to the written data length information in the following. The written data length information is not zero after each update, namely data is written into the first storage area before the next data writing, and the electronic equipment can write data into the first storage area for multiple times continuously.
As can be seen, in this example, after the electronic device writes data into the first memory each time, the written data length information of the first storage area is updated, where the written data length information of the first storage area after each update is not zero, that is, data can be written into the first memory for multiple times continuously, which is beneficial to improving the data writing efficiency.
In one possible example, the controlling the chip select signal corresponding to the first memory to be in the first state includes: detecting whether the first memory is in a write enable state; and if so, controlling the chip selection signal corresponding to the first memory to be in a first state.
In a specific implementation, data can be written into the memory only when the memory is in the write enable state, that is, if the first memory is not in the write enable state, data cannot be written into the first memory even if the chip select signal corresponding to the first memory is controlled to be in the first state. Therefore, before controlling the chip select signal corresponding to the first memory to be in the first state, it is necessary to detect whether the first memory is in the write enable state, and in the write enable state, the chip select signal corresponding to the first memory is controlled to be in the first state.
As can be seen, in this example, the electronic device first detects whether the first memory is in a write enable state; if so, controlling the chip selection signal corresponding to the first memory to be in a first state, which is beneficial to ensuring the realization of data writing.
In one possible example, the data includes data for writing to a first storage area in the first memory; the detecting whether the first memory is in a write enable state includes: detecting whether the written data length information of the first storage area is zero or not; and if so, detecting whether the first memory is in a write enable state.
In a specific implementation, the first storage area may be a buffer area, and for a case where data is written into the first memory for multiple times continuously, the length of the data written into the buffer area is zero, that is, data has not been written into the first memory before, so that it is necessary to determine that the first memory is in a write enable state before the length of the data written into the buffer area is zero, that is, data is written for the first time; if the length of the written data in the first storage area, namely the buffer area, is not zero, namely the data is not written into the first memory for the first time, the data is written into the first memory before the current time, and the first memory is detected to be in the write enable state, it is not required to detect whether the first memory is in the write enable state.
Specifically, the WEL bit of the first memory is read to determine that the WEL bit is a read-only bit, and when a write enable command is executed, the WEL bit of the first memory will be set to 1, indicating that data can be written. The WEL bit is 0 when "write disabled".
As can be seen, in this example, the electronic device first detects whether the written data length information of the first storage area is zero; if so, detecting whether the first memory is in a write enable state, namely when the length of the written data is not zero, the electronic equipment does not need to detect whether the first memory is in the write enable state, and the data writing efficiency is improved.
In one possible example, after the detecting whether the first memory is in a write enable state, the method further includes: if not, outputting information for representing data writing errors.
It can be seen that, in this example, when the electronic device detects that the first memory is not in the write enable state, the electronic device may output information used for representing a data write error, and since the first memory is not in the write enable state, data cannot be written into the first memory, a corresponding prompt message may be output to prompt that the data is written incorrectly, which is beneficial to improving comprehensiveness of the information.
In one possible example, the detecting whether the written data length of the first storage area is zero includes: detecting whether the first memory is in an idle state; and if so, detecting whether the written data length of the first storage area is zero.
In specific implementation, since the data write operation is not received when the memory is not in the idle state, the electronic device may first detect whether the first memory is in the idle state, and then perform the subsequent operation when the first memory is in the idle state. Specifically, the determination may be performed by reading a BUSY bit of the first memory, the BUSY bit is a read-only bit, the BUSY bit is set to 1 when the memory performs operations such as page programming and erasing, the BUSY bit is automatically cleared after the operations are completed, and the memory does not receive a data write operation when the BUSY bit is 1.
In addition, if it is detected that the first memory is not in an idle state, information for characterizing a data write error may be output.
It can be seen that, in this example, the electronic device detects whether the written data length of the first memory is zero when detecting that the first memory is in the idle state, which is beneficial to ensuring the implementation of data writing.
The following description is made with reference to specific examples.
Taking an example of writing data into the first memory by the electronic device in a page programming manner, please refer to fig. 2B, and a specific method flow may be as shown in fig. 2B. When the electronic device performs page programming, when data is written into the first memory for the first time, whether the first memory is in an idle state may be detected first, if it is detected that the first memory is in the idle state, whether the length of the written data is zero (including that the length of the written data is detected to be smaller than a first preset threshold value) may be detected, if the length of the written data is zero, it may be determined as first-time written data, at this time, it is required to detect whether the first memory is in a write enable state, that is, the first memory needs to be write enabled before the first time writing, after it is detected that the first memory is in the write enable state, a chip select signal corresponding to the first memory may be configured to be low, that is, an operating mode of the first memory, and then a page write instruction, a page write address and page write data may be written into a buffer area in the.
After the data is written once, updating the length of the written data, then detecting whether the length of the written data is smaller than a first preset threshold value, if so, detecting whether the length of the written data is zero, if not, the written data is existed before, a page writing instruction, a page writing address and page writing data can be directly written into the buffer area, updating the length of the written data again after the data is written, until the length of the written data is detected to be not smaller than the first preset threshold value, configuring a corresponding chip selection signal of the first memory to be high, finishing writing the data into the first memory, and latching the at least once written data into a corresponding storage area by the first memory.
The buffer, i.e. the first storage area in the method embodiment, has a written data length, i.e. written data length information of the first storage area, and the chip select signal is configured to be low, i.e. corresponding to the first state, and configured to be high, i.e. corresponding to the second state.
In addition, when detecting whether the first memory is in an idle state and detecting whether the first memory is in a write enable state, if the result is no, returning information for representing data write errors.
The present application may perform the division of the functional units for the electronic device according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
Fig. 3A is a block diagram of functional units of a data processing apparatus according to an embodiment of the present application. The data processing apparatus 30 can be applied to an electronic device as shown in fig. 1A, and the data processing apparatus 30 includes:
a first control unit 301, configured to control a chip select signal corresponding to the first memory to be in a first state;
a write unit 302 for writing data to the first memory at least once;
a second control unit 303, configured to control a chip select signal corresponding to the first memory to be in a second state, where the chip select signal with the signal state in the second state is used to instruct the first memory to latch the written data.
In one possible example, the data includes data for writing to a first storage area in the first memory; the second control unit 303 is specifically configured to: and when the written data length information of the first storage area is detected to be not less than a first preset threshold value, controlling the chip selection signal corresponding to the first storage to be in a second state.
In one possible example, the writing unit 302 is further configured to: in the at least one writing of data into the first memory, the written data length information of the first storage area is updated after each writing of data into the first memory, wherein the written data length information of the first storage area after each updating is not zero.
In one possible example, the second control unit 303 is specifically configured to: detecting whether the first memory is in a write enable state; and if so, controlling the chip selection signal corresponding to the first memory to be in a first state.
In one possible example, the data includes data for writing to a first storage area in the first memory; in the aspect of detecting whether the first memory is in the write enable state, the second control unit 303 is specifically configured to: detecting whether the written data length information of the first storage area is zero or not; and if so, detecting whether the first memory is in a write enable state.
In a possible example, the second control unit 303 is further configured to, after the detecting whether the first memory is in the write enable state, if not, output information for characterizing a data write error.
In one possible example, in the aspect of detecting whether the written data length of the first storage area is zero, the second control unit 303 is specifically configured to detect whether the first storage is in an idle state; and if so, detecting whether the written data length of the first storage area is zero.
In the case of using an integrated unit, a block diagram of functional units of the data processing apparatus provided in the embodiment of the present application is shown in fig. 3B. In fig. 3B, the data processing apparatus includes: a processing module 310 and a communication module 311. The processing module 310 is used for controlling and managing actions of the data processing apparatus, for example, steps performed by the first control unit 301, the writing unit 302, the second control unit 303, and/or other processes for performing the techniques described herein. The communication module 311 is used to support interaction between the data processing apparatus and other devices. As shown in fig. 3B, the data processing apparatus may further include a storage module 312, and the storage module 312 is used for storing program codes and data of the data processing apparatus.
The Processing module 310 may be a Processor or a controller, and may be, for example, a Central Processing Unit (CPU), a general-purpose Processor, a Digital Signal Processor (DSP), an ASIC, an FPGA or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others. The communication module 311 may be a transceiver, an RF circuit or a communication interface, etc. The storage module 312 may be a memory.
All relevant contents of each scene related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again. The data processing apparatus can perform the steps performed by the electronic device in the data processing method shown in fig. 2A.
Embodiments of the present application also provide a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to execute part or all of the steps of any one of the methods described in the above method embodiments, and the computer includes an electronic device.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing detailed description has been provided for embodiments of the present application, and specific examples have been applied to illustrate the principles and implementations of the present application, which are merely used to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A data processing method is applied to an electronic device, and the method comprises the following steps:
controlling a chip selection signal corresponding to the first memory to be in a first state;
writing data to the first memory at least once;
and controlling a chip selection signal corresponding to the first memory to be in a second state, wherein the chip selection signal with the signal state being in the second state is used for indicating the first memory to latch the written data.
2. The method of claim 1, wherein the data comprises data for writing to a first storage area in the first memory; the controlling the chip selection signal corresponding to the first memory to be in a second state includes:
and when the written data length information of the first storage area is detected to be not less than a first preset threshold value, controlling the chip selection signal corresponding to the first storage to be in a second state.
3. The method of claim 2, wherein the at least one write of data to the first memory is further followed by each write of data to the first memory:
and updating the written data length information of the first storage area, wherein the written data length information of the first storage area after each updating is not zero.
4. The method according to any one of claims 1-3, wherein controlling the chip select signal corresponding to the first memory to be in the first state comprises:
detecting whether the first memory is in a write enable state; and if so, controlling the chip selection signal corresponding to the first memory to be in a first state.
5. The method of claim 4, wherein the data comprises data for writing to a first storage area in the first memory; the detecting whether the first memory is in a write enable state includes:
detecting whether the written data length information of the first storage area is zero or not;
and if so, detecting whether the first memory is in a write enable state.
6. The method of claim 5, wherein after detecting whether the first memory is in a write enabled state, the method further comprises:
if not, outputting information for representing data writing errors.
7. The method of claim 5, wherein the detecting whether the written data length of the first storage area is zero comprises:
detecting whether the first memory is in an idle state;
and if so, detecting whether the written data length of the first storage area is zero.
8. A data processing apparatus, applied to an electronic device, the apparatus comprising:
the first control unit is used for controlling the chip selection signal corresponding to the first memory to be in a first state;
a write unit for writing data to the first memory at least once;
and the second control unit is used for controlling a chip selection signal corresponding to the first memory to be in a second state, and the chip selection signal with the signal state being in the second state is used for indicating the first memory to latch the written data.
9. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-7.
10. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011541455.6A CN112540732B (en) | 2020-12-23 | 2020-12-23 | Data processing method and related product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011541455.6A CN112540732B (en) | 2020-12-23 | 2020-12-23 | Data processing method and related product |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112540732A true CN112540732A (en) | 2021-03-23 |
| CN112540732B CN112540732B (en) | 2022-11-11 |
Family
ID=75017758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011541455.6A Active CN112540732B (en) | 2020-12-23 | 2020-12-23 | Data processing method and related product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112540732B (en) |
Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5375225A (en) * | 1991-12-31 | 1994-12-20 | Sun Microsystems, Inc. | System for emulating I/O device requests through status word locations corresponding to respective device addresses having read/write locations and status information |
| US5418746A (en) * | 1993-04-08 | 1995-05-23 | Samsung Electronics Co., Ltd. | Write signal input buffer for a semiconductor memory device |
| US5493666A (en) * | 1990-03-19 | 1996-02-20 | Apple Computer, Inc. | Memory architecture using page mode writes and single level write buffering |
| KR19990025052A (en) * | 1997-09-10 | 1999-04-06 | 구본준 | Semiconductor memory |
| US5933595A (en) * | 1996-06-20 | 1999-08-03 | Sharp Kabushiki Kaisha | Computer apparatus having electrically rewritable nonvolatile memory, and nonvolatile semiconductor memory |
| US6078520A (en) * | 1993-04-08 | 2000-06-20 | Hitachi, Ltd. | Flash memory control method and information processing system therewith |
| WO2001043135A1 (en) * | 1999-12-08 | 2001-06-14 | Infineon Technologies North America Corp. | A prefetch write driver for a random access memory |
| US20020110023A1 (en) * | 2000-12-11 | 2002-08-15 | Hitachi, Ltd. | Nonvolatile memory system |
| US20050213399A1 (en) * | 2004-03-29 | 2005-09-29 | Hoover Patricia J | Method and apparatus to write data |
| US20050228962A1 (en) * | 2002-04-05 | 2005-10-13 | Yoshinori Takase | Non-volatile storage device |
| CN102591820A (en) * | 2011-12-27 | 2012-07-18 | 钜泉光电科技(上海)股份有限公司 | IDMA (interleave division multiple access) bus bridge device |
| CN102693199A (en) * | 2012-06-04 | 2012-09-26 | 钜泉光电科技(上海)股份有限公司 | IDMA (Internal Direct Memory Access) interface and control method thereof |
| US20130086301A1 (en) * | 2011-09-30 | 2013-04-04 | International Business Machines Corporation | Direct Memory Address for Solid-State Drives |
| US20160163376A1 (en) * | 2014-12-08 | 2016-06-09 | Kuljit S. Bains | Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory |
| US20180059970A1 (en) * | 2016-08-26 | 2018-03-01 | Kabushiki Kaisha Toshiba | Storage device and method of writing data into storage device |
| CN108335720A (en) * | 2018-02-02 | 2018-07-27 | 上海华虹宏力半导体制造有限公司 | The method for writing individuation data using memory test machine |
| CN108664362A (en) * | 2017-03-31 | 2018-10-16 | 龙芯中科技术有限公司 | Processing method, Memory Controller Hub and the user equipment of memory mirror |
| US20200110555A1 (en) * | 2018-10-03 | 2020-04-09 | Silicon Motion Inc. | Write control method, associated data storage device and controller thereof |
-
2020
- 2020-12-23 CN CN202011541455.6A patent/CN112540732B/en active Active
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5493666A (en) * | 1990-03-19 | 1996-02-20 | Apple Computer, Inc. | Memory architecture using page mode writes and single level write buffering |
| US5375225A (en) * | 1991-12-31 | 1994-12-20 | Sun Microsystems, Inc. | System for emulating I/O device requests through status word locations corresponding to respective device addresses having read/write locations and status information |
| US5418746A (en) * | 1993-04-08 | 1995-05-23 | Samsung Electronics Co., Ltd. | Write signal input buffer for a semiconductor memory device |
| US6078520A (en) * | 1993-04-08 | 2000-06-20 | Hitachi, Ltd. | Flash memory control method and information processing system therewith |
| US5933595A (en) * | 1996-06-20 | 1999-08-03 | Sharp Kabushiki Kaisha | Computer apparatus having electrically rewritable nonvolatile memory, and nonvolatile semiconductor memory |
| KR19990025052A (en) * | 1997-09-10 | 1999-04-06 | 구본준 | Semiconductor memory |
| WO2001043135A1 (en) * | 1999-12-08 | 2001-06-14 | Infineon Technologies North America Corp. | A prefetch write driver for a random access memory |
| US20020110023A1 (en) * | 2000-12-11 | 2002-08-15 | Hitachi, Ltd. | Nonvolatile memory system |
| US20050228962A1 (en) * | 2002-04-05 | 2005-10-13 | Yoshinori Takase | Non-volatile storage device |
| US20050213399A1 (en) * | 2004-03-29 | 2005-09-29 | Hoover Patricia J | Method and apparatus to write data |
| US20130086301A1 (en) * | 2011-09-30 | 2013-04-04 | International Business Machines Corporation | Direct Memory Address for Solid-State Drives |
| CN102591820A (en) * | 2011-12-27 | 2012-07-18 | 钜泉光电科技(上海)股份有限公司 | IDMA (interleave division multiple access) bus bridge device |
| CN102693199A (en) * | 2012-06-04 | 2012-09-26 | 钜泉光电科技(上海)股份有限公司 | IDMA (Internal Direct Memory Access) interface and control method thereof |
| US20160163376A1 (en) * | 2014-12-08 | 2016-06-09 | Kuljit S. Bains | Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory |
| US20180059970A1 (en) * | 2016-08-26 | 2018-03-01 | Kabushiki Kaisha Toshiba | Storage device and method of writing data into storage device |
| CN108664362A (en) * | 2017-03-31 | 2018-10-16 | 龙芯中科技术有限公司 | Processing method, Memory Controller Hub and the user equipment of memory mirror |
| CN108335720A (en) * | 2018-02-02 | 2018-07-27 | 上海华虹宏力半导体制造有限公司 | The method for writing individuation data using memory test machine |
| US20200110555A1 (en) * | 2018-10-03 | 2020-04-09 | Silicon Motion Inc. | Write control method, associated data storage device and controller thereof |
Non-Patent Citations (1)
| Title |
|---|
| 戚振军等: "基于AFS600的CAN核重用设计", 《机械与电子》, 31 May 2010 (2010-05-31), pages 41 - 44 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112540732B (en) | 2022-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9251065B2 (en) | Execute-in-place mode configuration for serial non-volatile memory | |
| US20090307537A1 (en) | Flash storage device with data correction function | |
| CN102543179A (en) | Concurrent read and write memory operations in a serial interface memory | |
| US10866736B2 (en) | Memory controller and data processing circuit with improved system efficiency | |
| WO2017020647A1 (en) | Novel storage-based embedded file system and realization method thereof | |
| US10475517B2 (en) | Characterizing and operating a non-volatile memory device | |
| US10839140B2 (en) | Page displaying method, apparatus based on H5 webpage, and computer readable storage medium | |
| CN110297603A (en) | Random write performance method for improving, device and computer equipment based on solid state hard disk | |
| US8914602B2 (en) | Display controller having an embedded non-volatile memory divided into a program code block and a data block and method for updating parameters of the same | |
| CN107577775B (en) | Data reading method and device, electronic equipment and readable storage medium | |
| CN112199040A (en) | Storage access method and intelligent processing device | |
| KR20070063132A (en) | Apparatus and method for manage a bad block | |
| US9934100B2 (en) | Method of controlling memory swap operation and data processing system using same | |
| CN112540732B (en) | Data processing method and related product | |
| JP2009123191A (en) | Nor-interface flash memory device and method of accessing the same | |
| KR20050076156A (en) | Data recovery device and method thereof | |
| US20070208929A1 (en) | Device information managements systems and methods | |
| CN113760195B (en) | FATFS file system based on embedded type | |
| US20040186949A1 (en) | XIP system and method for serial memory | |
| CN114626349B (en) | Non-invasive file editing method, device and medium | |
| CN111858406B (en) | Method, device, equipment and medium for making SPI master control compatible with flash chip | |
| US11947467B2 (en) | Electronic device and operation method thereof | |
| US7213142B2 (en) | System and method to initialize registers with an EEPROM stored boot sequence | |
| CN117668925B (en) | File fingerprint generation method and device, electronic equipment and storage medium | |
| US10566062B2 (en) | Memory device and method for operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |