CN111858406B - Method, device, equipment and medium for making SPI master control compatible with flash chip - Google Patents
Method, device, equipment and medium for making SPI master control compatible with flash chip Download PDFInfo
- Publication number
- CN111858406B CN111858406B CN202010569325.7A CN202010569325A CN111858406B CN 111858406 B CN111858406 B CN 111858406B CN 202010569325 A CN202010569325 A CN 202010569325A CN 111858406 B CN111858406 B CN 111858406B
- Authority
- CN
- China
- Prior art keywords
- chip
- size
- flash
- memory space
- flash chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 230000004044 response Effects 0.000 claims abstract description 17
- 238000013507 mapping Methods 0.000 claims abstract description 16
- 230000006870 function Effects 0.000 claims abstract description 14
- 238000004590 computer program Methods 0.000 claims description 13
- 238000011161 development Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a method for making SPI master control compatible with a flash chip, which comprises the following steps: in response to the BMC chip receiving an erasing instruction of the flash chip, determining the size of a memory space opened in the BMC chip through a register; in response to the fact that the size of the memory space opened up in the BMC chip is determined to be 0 through the register, the size of the flash chip in the kernel code is read, and whether the size of the flash chip is smaller than the size of the memory space opened up in the least of the BMC chip or not is judged through the device tree; responding to the fact that the size of the flash chip is smaller than the size of the minimum developed memory space of the BMC chip, and enabling the BMC chip to develop the minimum developed memory space through the equipment tree; and mapping the flash chip into a memory space, so that the drive of the SPI master control loads the relevant functions of the flash chip, and the BMC chip finishes erasing and writing the flash chip through memory mapping. The invention also discloses a device, equipment and a medium. The invention is compatible with the condition that the size of the flash chip of the SPI master control is not proper, and enhances the universality of the SPI master control.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a method, an apparatus, a device, and a medium for making an SPI master control compatible with a flash chip.
Background
The development of information technology is not independent of the support of various transmission protocols, and the SPI (SPI is a high-speed, full-duplex, synchronous communication bus) protocol is one of them. The SPI is a widely used transmission protocol, it only needs four hardware connecting lines to complete information transmission, the protocol does not need to resolve address, only CS (gating) line is used to decide whether to gate a certain device, so the speed of the SPI is faster. If one path of equipment needs to be expanded, only one more CS line is needed, and the expansion is easy. The SPI also supports three modes of single master and single slave configuration, single master and multiple slaves configuration and master-slave configuration, and is a flexibly configured protocol.
The SPI protocol is generally used in a scenario with certain requirements on speed, which can reach 10 Mbps. A small-sized mirror system, such as BIOS, u-boot, etc., is usually used to load flash (coded flash memory, which can store and erase data quickly). For a server, a management chip BMC is usually required to erase a flash in a mirror image manner, and not only the flash itself but also the flash of a chip such as a CPU need to be erased. Generally, the BMC directly supports erasing and writing of the flash of the BMC, but the flash of other chips is not necessarily as perfect as the flash of other chips. Especially, when the capacity of a certain flash is not appropriate, the flash is not supported.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a driver for an SPI master control, which can perform additional expansion configuration on the SPI master control in a device tree, and is compatible with the situation that a flash chip of the SPI master control is not appropriate in size, thereby enhancing the universality of the SPI master control.
Based on the above object, in one aspect, the present invention provides a method for making an SPI master control compatible with a flash chip, the method comprising:
in response to the BMC chip receiving an erasing instruction of the flash chip, determining the size of a memory space opened in the BMC chip through a register;
in response to the fact that the size of the memory space opened up in the BMC chip is determined to be 0 through the register, the size of the flash chip in the kernel code is read, and whether the size of the flash chip is smaller than the size of the memory space opened up in the least of the BMC chip or not is judged through the device tree;
responding to the fact that the size of the flash chip is smaller than the size of the minimum developed memory space of the BMC chip, and enabling the BMC chip to develop the minimum developed memory space through the equipment tree;
and mapping the flash chip into a memory space, so that the drive of the SPI master control loads the relevant functions of the flash chip, and completing erasing and writing of the flash chip by the BMC chip through memory mapping.
In some embodiments of the method for making the SPI master control compatible with the flash chip of the present invention, determining, by the register, the size of the memory space opened up in the BMC chip in response to the BMC chip receiving an instruction to erase the flash chip further includes:
and calculating the difference value between the ending bit and the starting bit of the flag bit of the register according to the size of the flash chip and the size of the minimum developed memory space of the BMC chip, and determining the size of the developed memory space according to the difference value between the ending bit and the starting bit of the flag bit of the register.
In some embodiments of the method for making the SPI master compatible with the flash chip of the present invention, the method further comprises:
and in response to the fact that the size of the flash chip is smaller than the size of the minimum developed memory space of the BMC chip, calculating the difference value of the ending bit and the starting bit of the flag bit of the register to be 0, and determining that the size of the memory space developed in the BMC chip is 0 according to the fact that the difference value of the ending bit and the starting bit of the flag bit of the register is 0.
In some embodiments of the method for making the SPI master compatible with the flash chip of the present invention, the method further comprises:
and outputting an error report in response to the judgment that the size of the flash chip is not smaller than the minimum developed memory space of the BMC chip through the device tree.
In some embodiments of the method for making the SPI master compatible with the flash chip of the present invention, the method further comprises:
the supported models of the flash chips are registered into an equipment list according to the kernel code, the configuration information of the flash chips in the equipment tree is searched, and the matched models of the flash chips are searched in the equipment list according to the configuration information.
In another aspect of the embodiments of the present invention, there is also provided a device for making an SPI master control compatible with a flash chip, the device including:
the erasing instruction receiving module is configured to respond to the BMC chip receiving an erasing instruction for the flash chip and determine the size of a memory space opened in the BMC chip through a register;
the method comprises the steps that an open exception judgment module is configured to respond to the fact that the size of a memory space opened in a BMC chip is determined to be 0 through a register, read the size of a flash chip in a kernel code, and judge whether the size of the flash chip is smaller than the size of the minimum opened memory space of the BMC chip or not through a device tree;
the device tree development module is configured to respond that the size of the flash chip is smaller than the minimum developed memory space of the BMC chip, and the minimum developed memory space is developed by the BMC chip through the device tree;
and the mapping erasing module is configured to map the flash chip into the memory space, so that the drive of the SPI main control loads the related functions of the flash chip, and the BMC chip finishes erasing the flash chip through memory mapping.
In some embodiments of the apparatus for making an SPI master compatible with a flash chip of the present invention, the erasure instruction receiving module is further configured to:
and calculating the difference value between the ending bit and the starting bit of the flag bit of the register according to the size of the flash chip and the size of the minimum developed memory space of the BMC chip, and determining the size of the developed memory space according to the difference value between the ending bit and the starting bit of the flag bit of the register.
In some embodiments of the apparatus for making an SPI master compatible with a flash chip of the present invention, the apparatus further comprises:
and the error judgment module is configured to respond to the judgment that the size of the flash chip is not smaller than the minimum opened memory space of the BMC chip through the device tree and output an error report.
In another aspect of the embodiments of the present invention, a computer device is further provided, where the computer device includes:
at least one processor; and
the memory is used for storing a computer program which can run on the processor, and the processor executes the method for making the SPI master control compatible with the flash chip when executing the program.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, where the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to perform the foregoing method for making an SPI master compatible with a flash chip.
The invention has at least the following beneficial technical effects: according to the invention, a flash chip size judgment mechanism is added in the SPI master control, so that the drive of the SPI master control can be adapted to more types of flash chips, and the drive adaptability is enhanced, thereby increasing the selection of system engineers during material selection and being beneficial to reducing the cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an embodiment of programming a flash chip by a BMC chip according to an embodiment of a method for making an SPI master compatible with the flash chip of the present invention;
FIG. 2 shows a schematic block diagram of an embodiment of a method of making an SPI master compatible with a flash chip in accordance with the present invention;
fig. 3 shows a flowchart of an embodiment of a method for making an SPI master compatible with a flash chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it is understood that "first" and "second" are only used for convenience of description and should not be construed as limiting the embodiments of the present invention, and the descriptions thereof in the following embodiments are omitted.
Based on the above purpose, the first aspect of the embodiments of the present invention provides an embodiment of a method for making an SPI master compatible with a flash chip. Fig. 1 is a schematic block diagram illustrating an embodiment of a method for making an SPI master compatible with a flash chip according to the present invention. In the embodiment shown in fig. 1, the method comprises at least the following steps:
s100, responding to the fact that the BMC chip receives an erasing instruction of the flash chip, and determining the size of a memory space opened in the BMC chip through a register;
s200, in response to the fact that the size of the memory space opened in the BMC chip is determined to be 0 through the register, reading the size of the flash chip in the kernel code, and judging whether the size of the flash chip is smaller than the size of the minimum opened memory space of the BMC chip or not through the equipment tree;
s300, responding to the fact that the size of the flash chip is smaller than the size of the minimum opened memory space of the BMC chip, and enabling the BMC chip to open the minimum opened memory space through the equipment tree;
s400, mapping the flash chip into a memory space, enabling the driver of the SPI master control to load the relevant functions of the flash chip, and completing erasing and writing of the flash chip through memory mapping by the BMC chip.
In some embodiments of the present invention, in an application scenario of a server, the BMC chip is often required to erase and write contents of various flash chips, and the types of the flash chips are various and have different sizes. For the BMC chip, the flash chip is mapped to the memory of the BMC chip to work, so erasing and writing of the flash chip generally includes storing the content to be erased and written in the memory by the BMC chip, and then erasing and writing of the flash chip are completed by using the memory mapping. Fig. 1 is a schematic diagram illustrating an embodiment of a method for making an SPI master compatible with a flash chip according to the present invention, in which a BMC chip writes a flash chip, and as shown in fig. 1, in an erasing process, a memory needs to open up 32M space for mapping the flash chip to complete erasing and writing the flash chip. In this scenario, the main control chip is a BMC chip, and a corresponding register is provided in the BMC chip to determine how much memory space is to be mapped to the flash chip. In some embodiments of the present invention, the flash chip size register of the BMC chip is configured by using a difference configuration method, that is, (end-start) × N determines the size of the memory space to be opened, where end is the end bit of the flag bit of the register, and start is the start bit of the flag bit of the register. This N determines the size of the minimum flash chip that the BMC chip can support, i.e., the size of the minimum memory space to be created is N. Fig. 3 is a flowchart illustrating an embodiment of a method for making an SPI master compatible with a flash chip according to the present invention, and as shown in fig. 3, a 32M flash chip is loaded in a BMC chip, and finally a 32M memory space is opened up in a memory. It should be noted that, when the BMC chip cannot open up the memory space of the flash chip, the flash chip cannot be erased and written. Under the condition, the size setting of the flash chip in the kernel code is read, whether the memory size of the flash chip is smaller than the value N or not is judged, if so, the value of end-start is forced to be 1, the driver can normally load the related functions of the flash chip, the adaptability of the BMC chip to more types of flash chips is enhanced, and the judgment can be configured in the equipment tree.
In some other embodiments of the present invention, the method may be applied to similar cases, but the writing of the specific driver code and the setting of the device tree need to be specifically set according to the specification of the specific main control chip.
According to some embodiments of the method for making the SPI master control compatible with the flash chip of the present invention, in response to the BMC chip receiving an instruction to erase the flash chip, determining the size of the memory space opened up in the BMC chip through the register further includes:
and calculating the difference value between the ending bit and the starting bit of the flag bit of the register according to the size of the flash chip and the size of the minimum developed memory space of the BMC chip, and determining the size of the developed memory space according to the difference value between the ending bit and the starting bit of the flag bit of the register.
In some embodiments of the present invention, the flash chip size register of the BMC chip is configured by using a difference configuration method, that is, (end-start) × N determines the size of the memory space to be opened, where end is the end bit of the flag bit of the register, and start is the start bit of the flag bit of the register. This N determines the size of the minimum flash chip that the BMC chip can support, i.e., the size of the minimum memory space to be created is N. For example, if N is 8M and flash is 32M, the value of (end-start) will be configured to be 4.
According to some embodiments of the method for making an SPI master compatible with a flash chip of the present invention, the method further comprises:
and in response to the fact that the size of the flash chip is smaller than the size of the minimum opened memory space of the BMC chip, calculating the difference value between the ending bit and the starting bit of the flag bit of the register to be 0, and determining that the size of the memory space opened up in the BMC chip is 0 according to the difference value between the ending bit and the starting bit of the flag bit of the register to be 0.
In some embodiments of the present invention, when a certain flash chip is smaller than 8M, the kernel code sets the flash chip to a size smaller than 8M, and the BMC chip sets the value of (end-start) to 0 because the capacity of the flash chip is smaller than 8M, which will cause the BMC chip to be unable to open up the memory space of the flash chip, so that the flash chip cannot be erased and written.
According to some embodiments of the method for making an SPI master compatible with a flash chip of the present invention, the method further comprises:
and outputting an error report in response to the judgment that the size of the flash chip is not smaller than the minimum developed memory space of the BMC chip through the device tree.
In some embodiments of the present invention, if the device tree has the determination configuration item, the driver may compare the size of the flash chip with the size of the minimum opened memory space of the BMC chip through the device tree, and if the size of the flash chip is determined not to be smaller than the size of the minimum opened memory space of the BMC chip, may output a related error report with an (end-start) value of 0.
According to some embodiments of the method for making an SPI master compatible with a flash chip of the present invention, the method further comprises:
and registering the supported models of the flash chips into an equipment list according to the kernel code, searching the configuration information of the flash chips in the equipment tree, and searching the matched models of the flash chips in the equipment list according to the configuration information.
In some embodiments of the present invention, fig. 3 is a flowchart illustrating an embodiment of a method for making an SPI master control compatible with a flash chip according to the present invention, and as shown in fig. 3, after a BMC chip receives an instruction to erase a flash chip, a configuration process requires matching of a kernel driver file and a device tree, and it is necessary to register a model of an SPI _ flash (a kernel code form of the flash chip, which represents the flash chip) in a device list from a kernel code, search for an SPI _ flash configuration of the device tree, match the model of the SPI _ flash from the device list, and determine whether matching is successful.
In another aspect of the embodiments of the present invention, an embodiment of a device for making an SPI master compatible with a flash chip is provided. The device includes:
the erasing instruction receiving module is configured to respond to the BMC chip receiving an erasing instruction for the flash chip and determine the size of a memory space opened in the BMC chip through a register;
the method comprises the steps that an open exception judgment module is configured to respond to the fact that the size of a memory space opened in a BMC chip is determined to be 0 through a register, read the size of a flash chip in a kernel code, and judge whether the size of the flash chip is smaller than the size of the minimum opened memory space of the BMC chip or not through a device tree;
the device tree development module is configured to respond that the size of the flash chip is smaller than the minimum developed memory space of the BMC chip, and the minimum developed memory space is developed by the BMC chip through the device tree;
and the mapping erasing module is configured to map the flash chip into the memory space, so that the drive of the SPI main control loads the related functions of the flash chip, and the BMC chip finishes erasing the flash chip through memory mapping.
According to some embodiments of the apparatus for making an SPI master compatible with a flash chip of the present invention, the erasure instruction receiving module is further configured to:
and calculating the difference value between the ending bit and the starting bit of the flag bit of the register according to the size of the flash chip and the size of the minimum developed memory space of the BMC chip, and determining the size of the developed memory space according to the difference value between the ending bit and the starting bit of the flag bit of the register.
According to some embodiments of the apparatus for making an SPI master compatible with a flash chip of the present invention, the apparatus further comprises:
and the error judgment module is configured to respond to the judgment that the size of the flash chip is not smaller than the minimum opened memory space of the BMC chip through the device tree and output an error report.
In view of the above object, another aspect of the embodiments of the present invention further provides a computer device, including: at least one processor; and the memory is used for storing a computer program which can run on the processor, and the processor executes the method for making the SPI master control compatible with the flash chip when executing the program.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, where the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to perform the foregoing method for making an SPI master compatible with a flash chip.
Likewise, those skilled in the art will appreciate that all of the embodiments, features and advantages set forth above with respect to the method of making an SPI master compatible with a flash chip according to the present invention apply equally well to the apparatus, computer device and medium according to the present invention. For the sake of brevity of the present disclosure, no repeated explanation is provided herein.
It should be particularly noted that, the steps in the embodiments of the method, apparatus, device and medium for making the SPI master compatible with the flash chip may be mutually intersected, replaced, added or deleted, so that these reasonable permutations and combinations are changed to make the SPI master compatible with the flash chip, and the method, apparatus, device and medium should also belong to the protection scope of the present invention, and should not limit the protection scope of the present invention to the embodiments.
Finally, it should be noted that, as one of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program to instruct related hardware, so that the program of the method for SPI master control compatible with the flash chip can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be understood that the computer-readable storage medium herein (e.g., memory) can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for making an SPI master compatible with a flash chip is characterized by comprising the following steps:
in response to the BMC chip receiving an erasing instruction of the flash chip, determining the size of a memory space opened in the BMC chip through a register;
in response to the fact that the size of the memory space opened in the BMC chip is determined to be 0 through the register, reading the size of the flash chip in a kernel code, and judging whether the size of the flash chip is smaller than the size of the minimum opened memory space of the BMC chip or not through a device tree;
responding to the size of the flash chip smaller than the minimum developed memory space of the BMC chip, and enabling the BMC chip to develop the minimum developed memory space through the equipment tree;
and mapping the flash chip into the memory space, loading the related functions of the flash chip by a driver of an SPI master control, and completing erasing and writing of the flash chip by the BMC chip through memory mapping.
2. The method as claimed in claim 1, wherein the determining, by the register, the size of the memory space opened up in the BMC chip in response to the BMC chip receiving the flash chip erase/write command further comprises:
and calculating the difference value between the ending bit and the starting bit of the flag bit of the register according to the size of the flash chip and the size of the minimum opened memory space of the BMC chip, and determining the size of the opened memory space according to the difference value between the ending bit and the starting bit of the flag bit of the register.
3. The method of claim 2, wherein the method further comprises:
and in response to that the size of the flash chip is smaller than the size of the minimum developed memory space of the BMC chip, calculating the difference value between the ending bit and the starting bit of the flag bit of the register to be 0, and determining that the size of the memory space developed in the BMC chip is 0 according to the difference value between the ending bit and the starting bit of the flag bit of the register to be 0.
4. The method of claim 1, wherein the method further comprises:
and outputting an error report in response to the judgment that the size of the flash chip is not smaller than the minimum size of the memory space opened up by the BMC chip through the equipment tree.
5. The method for making an SPI master compatible with a flash chip according to claim 1, further comprising:
registering the supported models of the flash chips into an equipment list according to the kernel code, searching the configuration information of the flash chips in the equipment tree, and searching the matched models of the flash chips in the equipment list according to the configuration information.
6. An apparatus for making an SPI master compatible with a flash chip, the apparatus comprising:
the flash instruction receiving module is configured to respond to the BMC chip receiving an instruction for performing flash on the flash chip, and determine the size of a memory space opened in the BMC chip through a register;
the boot exception judging module is configured to read the size of the flash chip in the kernel code in response to the fact that the size of the memory space which is booted up in the BMC chip is determined to be 0 through the register, and judge whether the size of the flash chip is smaller than the size of the minimum booted memory space of the BMC chip through the device tree;
the device tree development module is configured to respond that the size of the flash chip is smaller than the minimum developed memory space of the BMC chip, and the minimum developed memory space is developed by the BMC chip through the device tree;
the flash mapping module is configured to map the flash chip into the memory space, so that the drive of the SPI master control loads the related functions of the flash chip, and the BMC chip finishes erasing the flash chip through memory mapping.
7. The apparatus according to claim 6, wherein the erasure instruction receiving module is further configured to:
and calculating the difference value between the ending bit and the starting bit of the flag bit of the register according to the size of the flash chip and the size of the minimum opened memory space of the BMC chip, and determining the size of the opened memory space according to the difference value between the ending bit and the starting bit of the flag bit of the register.
8. The apparatus of claim 6, wherein the apparatus further comprises:
and the error judgment module is configured to respond to the judgment that the size of the flash chip is not smaller than the size of the minimum opened memory space of the BMC chip through the equipment tree and output an error report.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor, when executing the program, performs the method of any of claims 1-5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010569325.7A CN111858406B (en) | 2020-06-20 | 2020-06-20 | Method, device, equipment and medium for making SPI master control compatible with flash chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010569325.7A CN111858406B (en) | 2020-06-20 | 2020-06-20 | Method, device, equipment and medium for making SPI master control compatible with flash chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111858406A CN111858406A (en) | 2020-10-30 |
| CN111858406B true CN111858406B (en) | 2022-07-08 |
Family
ID=72987704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010569325.7A Active CN111858406B (en) | 2020-06-20 | 2020-06-20 | Method, device, equipment and medium for making SPI master control compatible with flash chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111858406B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110659181A (en) * | 2019-09-06 | 2020-01-07 | 苏州浪潮智能科技有限公司 | Method and device for monitoring server mainboard and readable medium |
| CN110691094A (en) * | 2019-10-10 | 2020-01-14 | 山东超越数控电子股份有限公司 | Method, equipment and medium for transmitting data based on ISCSI protocol |
| CN110764715B (en) * | 2019-11-09 | 2021-07-06 | 苏州浪潮智能科技有限公司 | Bandwidth control method, device and storage medium |
-
2020
- 2020-06-20 CN CN202010569325.7A patent/CN111858406B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111858406A (en) | 2020-10-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8006030B2 (en) | Memory controller for identifying the last valid page/segment in a physical block of a flash memory | |
| US20060064576A1 (en) | Boot systems and methods | |
| US7007140B2 (en) | Storage device, storage device controlling method, and program | |
| WO2017020647A1 (en) | Novel storage-based embedded file system and realization method thereof | |
| JPH08328762A (en) | Semiconductor disk device and memory management method therefor | |
| US8914602B2 (en) | Display controller having an embedded non-volatile memory divided into a program code block and a data block and method for updating parameters of the same | |
| CN114174973A (en) | Serial memory device I/O mode selection | |
| CN111813432A (en) | FPGA configuration upgrading method and FPGA platform | |
| US6925522B2 (en) | Device and method capable of changing codes of micro-controller | |
| JP4294894B2 (en) | Memory card | |
| CN111858406B (en) | Method, device, equipment and medium for making SPI master control compatible with flash chip | |
| TWI515558B (en) | Integration of secure data transfer applications for generic io devices | |
| US10990323B2 (en) | Flash memory controller, memory device and method for accessing flash memory module | |
| TW583582B (en) | Microcomputer and associated method for reducing memory usage of the microcomputer | |
| JP4199121B2 (en) | Method and apparatus for changing the contents of a revision identification register | |
| US6556476B1 (en) | Non-volatile memory data protection | |
| KR100737919B1 (en) | Program method of nand flash memory and program method of memory system | |
| JPH0476681A (en) | Microcomputer | |
| US20070208929A1 (en) | Device information managements systems and methods | |
| US8117427B2 (en) | Motherboard, storage device and controller thereof, and booting method | |
| US20080147966A1 (en) | Flash memory device, update method and program search method thereof | |
| US20100332731A1 (en) | Flash memory apparatus and method for operating the same and data storage system | |
| KR100479170B1 (en) | Access control device for memory and method thereof | |
| CN112540732B (en) | Data processing method and related product | |
| US10261899B2 (en) | Method, device and system for data processing using dedicated mapping between logical and physical addresses |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |