CN112486804A - Interconnection testing method, system, terminal and storage medium for different FPGA interfaces - Google Patents
Interconnection testing method, system, terminal and storage medium for different FPGA interfaces Download PDFInfo
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- CN112486804A CN112486804A CN202011266400.9A CN202011266400A CN112486804A CN 112486804 A CN112486804 A CN 112486804A CN 202011266400 A CN202011266400 A CN 202011266400A CN 112486804 A CN112486804 A CN 112486804A
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Abstract
The invention provides a method, a system, a terminal and a storage medium for testing interconnection of different FPGA interfaces, which comprises the following steps: connecting FPGA chips of different models of a control end and a client end with each other by using a direct connection cable; writing a forwarding program for forwarding the data received by the FPGA interface of the control end to a specific FPGA interface of the client end; writing a test program for detecting the consistency of the data packets sent and received by the FPGA interface of the client; and running the forwarding program on the control terminal, running the test program on the client terminal, and outputting an interconnection test result of the FPGA chip. The invention uses the direct connection cable to interconnect different FPGA interfaces, and simultaneously develops data forwarding tests aiming at the interconnection structure, including the connectivity of interconnection links and the consistency of data forwarding, thereby improving the competitiveness of server products.
Description
Technical Field
The invention belongs to the technical field of server testing, and particularly relates to a method, a system, a terminal and a storage medium for testing interconnection of different FPGA interfaces.
Background
With the rapid development of the internet industry, the demand of cloud services increases year by year, a development space is provided for the FPGA technology, and developers begin to apply FPGAs of different models and realize interconnection according to scenes in order to fully exert the FPGA efficiency.
The central FPGA interconnection method in the prior art only solves a multi-FPGA interconnection method oriented to high-performance computation, such as patent document CN 201310253545, and provides a multi-FPGA interconnection structure oriented to high-performance computation, which includes a two-stage communication interconnection network: the system comprises a local communication internet and a global communication internet, but only proposes the concept of the local communication internet and does not aim at an interconnection test method; in addition, the existing AOC cable is a universal 1:4AOC cable, and the forwarding of QSFP and SFP signals in an FPGA chip cannot be realized.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method, a system, a terminal and a storage medium for testing interconnection of different FPGA interfaces, so as to solve the technical problems.
In a first aspect, the present invention provides a method for testing interconnection of different FPGA interfaces, including:
connecting FPGA chips of different models of a control end and a client end with each other by using a direct connection cable;
writing a forwarding program for forwarding the data received by the FPGA interface of the control end to a specific FPGA interface of the client end;
writing a test program for detecting the consistency of the data packets sent and received by the FPGA interface of the client;
and running the forwarding program on the control terminal, running the test program on the client terminal, and outputting an interconnection test result of the FPGA chip.
Further, the method further comprises:
the client FPGA chip sends a data packet to the control FPGA chip, and the control FPGA chip analyzes the data packet and forwards the data packet to the FPGA chip of a specific client;
and if the client side sends and receives the data packets consistently, judging that the FPGA chip is normally connected with each other.
Further, the method further comprises: the interconnected FPGA chips are configured to support a forwarding function.
Furthermore, the FPGA chip of the control end adopts a four-channel FPGA interface.
Further, at least one client is provided.
In a second aspect, the present invention provides a different FPGA interface interconnection testing system, including:
the interconnection building unit is configured for interconnecting the control end and the FPGA chips of different models of the client by using a direct connection cable;
the forwarding programming unit is configured for compiling a forwarding program for forwarding the data received by the FPGA interface of the control terminal to a specific FPGA interface of the client terminal;
the test programming unit is configured for compiling a test program for detecting the consistency of the data packets sent and received by the FPGA interface of the client;
and the test operation unit is configured to operate the forwarding program on the control terminal, operate the test program on the client terminal and output an interconnection test result of the FPGA chip.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer-readable storage medium is provided, having stored therein instructions, which when run on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
according to the interconnection testing method, the interconnection testing system, the interconnection testing terminal and the storage medium for the different FPGA interfaces, the different FPGA interfaces are interconnected by using the direct-connection cable, and meanwhile, data forwarding tests are performed aiming at the interconnection structure, including the connectivity of the interconnection links and the consistency of data forwarding, so that the competitiveness of server products is improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
Fig. 2 is a schematic diagram of an interconnect structure according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of an interconnect structure according to an embodiment of the invention
FIG. 4 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following explains key terms appearing in the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution main body in fig. 1 may be an interconnection test system for different FPGA interfaces.
As shown in fig. 1, the method includes:
and 140, running the forwarding program on the control terminal, running the test program on the client terminal, and outputting an interconnection test result of the FPGA chip.
Optionally, as an embodiment of the present invention, the method further includes:
the client FPGA chip sends a data packet to the control FPGA chip, and the control FPGA chip analyzes the data packet and forwards the data packet to the FPGA chip of a specific client;
and if the client side sends and receives the data packets consistently, judging that the FPGA chip is normally connected with each other.
Optionally, as an embodiment of the present invention, the method further includes: the interconnected FPGA chips are configured to support a forwarding function.
Optionally, as an embodiment of the present invention, the FPGA chip of the control end adopts a four-channel FPGA interface.
Optionally, as an embodiment of the present invention, at least one of the clients is provided.
In order to facilitate understanding of the present invention, the principle of the interconnection testing method for different FPGA interfaces of the present invention is combined with two different interconnection modes for the FPGA interfaces in the embodiment to further describe the interconnection testing method for different FPGA interfaces of the present invention.
Direct attachment Cable (DAC Cable) is called DAC Cable for short, both ends of high-speed jumper are provided with optical modules, and the switch is connected to a router or a server, so that the Direct attachment Cable is widely applied to connection of a storage area network, a data center and a high-performance computer.
Specifically, the method for testing interconnection of different FPGA interfaces includes:
1. in the FPGA interface connection mode shown in fig. 2, there is only one client, and the client includes an SFP1 interface responsible for sending data packets and an SFP2 interface responsible for receiving data packets;
a. connecting one QSFP interface of the FPGA1 card to two SFP interfaces of the other FPGA2 card by using DAC cables; the QSFP interface is a four-channel SFP interface;
the FPGA1 is clamped on a control end server, and the FPGA2 is clamped on a client end server;
c. executing a forwarding program under a control end server system to realize the forwarding function of the test data packet;
d. executing a test program under a client server system to realize the transmission of a data packet from an SFP1 interface, receiving the data packet by an SFP2 interface, and checking whether the numerical values of the transmitted and received data packets are consistent or not, thereby realizing the test of an interface link between FPGA1 and an FPGA2 card;
2. in the FPGA interface connection mode shown in fig. 3, there are two clients, and the clients include SFP1&3 interfaces responsible for sending data packets and SFP2&4 interfaces responsible for receiving data packets;
a. connecting one QSFP interface of the FPGA1 card to four SFP1&2&3&4 interfaces of two other FPGA2 and FPGA3 cards respectively by using DAC cables;
the FPGA1 card is a control end server, and the FPGA2&3 card is a client end server;
c. executing a forwarding program under a control end server system to realize the forwarding function of the test data packet;
d. the test program is executed under two client server systems respectively provided with the FPGAs 2& 3:
the data packets are respectively transmitted from the SFP1&3 interface, and received by the SFP2&4 interface;
whether the numerical values of the sent data packet are consistent with the numerical values of the received data packet or not is checked, so that the FPGA link is tested;
as shown in fig. 4, the system 200 includes:
the interconnection building unit 210 is configured to use direct cables to interconnect the control end and the FPGA chips of different models of the client;
a forwarding programming unit 220 configured to write a forwarding program for forwarding the data received by the FPGA interface of the control terminal to a specific FPGA interface of the client terminal;
the test programming unit 230 is configured to write a test program for detecting the consistency of the data packets sent and received by the client FPGA interface;
and the test operation unit 240 is configured to operate the forwarding program on the control terminal, operate the test program on the client terminal, and output an interconnection test result of the FPGA chip.
Fig. 5 is a schematic structural diagram of a terminal system 300 according to an embodiment of the present invention, where the terminal system 300 may be used to execute a different FPGA interface interconnection testing method according to the embodiment of the present invention.
The terminal system 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the present invention provides a method for testing a local communication internet, which tests the data forwarding function of FPGA interconnection, and detects that the link communication of the FPGA hardware interface is normal, thereby fully playing the FPGA performance and improving the defect of server testing.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided by the present invention, it should be understood that the disclosed system, system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A different FPGA interface interconnection test method is characterized by comprising the following steps:
connecting FPGA chips of different models of a control end and a client end with each other by using a direct connection cable;
writing a forwarding program for forwarding the data received by the FPGA interface of the control end to a specific FPGA interface of the client end;
writing a test program for detecting the consistency of the data packets sent and received by the FPGA interface of the client;
and running the forwarding program on the control terminal, running the test program on the client terminal, and outputting an interconnection test result of the FPGA chip.
2. The method for testing interconnection of different FPGA interfaces according to claim 1, further comprising:
the client FPGA chip sends a data packet to the control FPGA chip, and the control FPGA chip analyzes the data packet and forwards the data packet to the FPGA chip of a specific client;
and if the client side sends and receives the data packets consistently, judging that the FPGA chip is normally connected with each other.
3. The method for testing interconnection of different FPGA interfaces according to claim 1, further comprising: the interconnected FPGA chips are configured to support a forwarding function.
4. The different FPGA interface interconnection testing method according to claim 1, wherein the FPGA chip of the control end adopts a four-channel FPGA interface, and the client end adopts a common FPGA interface.
5. The method for testing interconnection of different FPGA interfaces according to claim 1, wherein at least one client is provided.
6. The utility model provides a different FPGA interface interconnection test system which characterized in that includes:
the interconnection building unit is configured for interconnecting the control end and the FPGA chips of different models of the client by using a direct connection cable;
the forwarding programming unit is configured for compiling a forwarding program for forwarding the data received by the FPGA interface of the control terminal to a specific FPGA interface of the client terminal;
the test programming unit is configured for compiling a test program for detecting the consistency of the data packets sent and received by the FPGA interface of the client;
and the test operation unit is configured to operate the forwarding program on the control terminal, operate the test program on the client terminal and output an interconnection test result of the FPGA chip.
7. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-5.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-5.
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| CN202011266400.9A CN112486804A (en) | 2020-11-13 | 2020-11-13 | Interconnection testing method, system, terminal and storage medium for different FPGA interfaces |
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| CN202011266400.9A CN112486804A (en) | 2020-11-13 | 2020-11-13 | Interconnection testing method, system, terminal and storage medium for different FPGA interfaces |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100244848A1 (en) * | 2009-03-30 | 2010-09-30 | Infineon Technologies Ag | System for testing connections between chips |
| CN110569154A (en) * | 2019-08-16 | 2019-12-13 | 苏州浪潮智能科技有限公司 | Chip interface function testing method, system, terminal and storage medium |
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- 2020-11-13 CN CN202011266400.9A patent/CN112486804A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100244848A1 (en) * | 2009-03-30 | 2010-09-30 | Infineon Technologies Ag | System for testing connections between chips |
| CN110569154A (en) * | 2019-08-16 | 2019-12-13 | 苏州浪潮智能科技有限公司 | Chip interface function testing method, system, terminal and storage medium |
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