CN112448735B - X-band programmable integrated transceiver - Google Patents
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- CN112448735B CN112448735B CN202011441792.8A CN202011441792A CN112448735B CN 112448735 B CN112448735 B CN 112448735B CN 202011441792 A CN202011441792 A CN 202011441792A CN 112448735 B CN112448735 B CN 112448735B
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- 230000010365 information processing Effects 0.000 claims abstract description 12
- 238000009432 framing Methods 0.000 claims description 16
- 230000002457 bidirectional effect Effects 0.000 claims description 7
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
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Abstract
The invention discloses an X-band programmable integrated transceiver which comprises a receiving unit, a frequency synthesis unit, a transmitting unit, a control unit, a power supply unit and an information processing unit. The information processing unit analyzes and frames the serial port signal by receiving the external serial port signal and the external time sequence, generates an internal time sequence and transmits the internal time sequence to all units connected with the internal time sequence; the frequency synthesis unit generates a modulation signal and a second local oscillation signal according to the instruction and the internal time sequence; when the receiving unit works and the transmitting unit is closed, the received 9.3-9.4 GHz radio frequency input is subjected to down-conversion twice to form 150MHz intermediate frequency signal output, and when the transmitting unit works and the receiving unit is closed, the 150MHz intermediate frequency from the frequency synthesis module is up-converted to 9.3-9.4 GHz high frequency signal, and the signal is amplified to 60W output. The invention has high integration level, digital programming, portability and strong universality, and can be used for receiving and transmitting radar electromagnetic waves.
Description
Technical Field
The invention belongs to the technical field of communication, in particular to an X-band programmable integrated transceiver which can be used for receiving and transmitting radar electromagnetic waves.
Background
Radar transmitting modules and receiving modules are important components in radar communication systems. Modern radar signals generally comprise low-frequency signals, intermediate-frequency signals and high-frequency signals, wherein the high-frequency signals are microwave signals, and electromagnetic waves in a required frequency range are radiated to space after the high-frequency signals are generated by a radar microwave transmitting module; the radar receiving module converts the received electromagnetic echo signals into intermediate frequency signals for the signal processor after amplifying, filtering, demodulating and other processes.
The traditional radar transmitting module and the radar receiving module are two separate independent units, the width, the amplitude and the pulse repetition frequency of the radio frequency pulse signals are fixed when the traditional radar transmitting module and the radar receiving module work in a selected mode for the airborne weather radar, but the pulse width required by the modern weather radar can be automatically adjusted within the required range to realize the optimization of radar performance, and for the airborne radar, a host factory has higher requirements on the volume and the weight of the radar, the volume and the weight of the radar are increased in an intangible way for a separated radar transmitter and a separated radar receiver, and more interpolation loss is introduced in the transmission process of the signals.
In order to solve the defects of the two separation modules, the prior art provides an X-band continuous solid-state receiving and transmitting assembly, wherein a radar receiving module and a transmitting module are integrated in the same shell, a frequency vibrating circuit is added in the middle of the shell of the receiving and transmitting module, the precision adjustment of output power and the constancy of the amplitude of an output intermediate frequency signal are realized by the technical proposal, the insertion loss of the signal in the transmission process is reduced, the volume and the weight of the radar receiving and transmitting module are reduced to a certain extent, but the width, the amplitude and the pulse repetition frequency of a radio frequency pulse signal generated by the receiving and transmitting assembly are fixed, and the receiving and transmitting assembly cannot be suitable for the requirement that the pulse width can be automatically adjusted in the required range of the modern weather radar.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides an X-band programmable integrated transceiver which is used for changing the width, amplitude and pulse repetition frequency of a radio frequency pulse signal in a software programming mode, enhancing the integration characteristic and digital programmable characteristic of a transceiver module and meeting the requirement that the pulse width can be automatically adjusted within a required range required by a modern weather radar.
To achieve the above object, an X-band programmable integrated transceiver of the present invention includes:
the receiving unit 1 is used for completing the frequency conversion treatment of the received 9.3 GHz-9.4 GHz radio frequency signals for 2 times, down-converting the signals to 150MHz intermediate frequency signals and completing the amplification output of the intermediate frequency signals;
the frequency synthesis unit 2 is connected with the receiving unit 1 in a one-way through a printed board wire, generates a frequency hopping signal of 8310 MHz-8410 MHz as a second local oscillator, is used for down-conversion of the receiving unit 1, and generates a modulation signal of 150MHz + -10 MHz-150 MHz + -11 MHz for up-conversion;
the transmitting unit 3 is connected with the frequency synthesizing unit 2 in one way through a printed board wire and is used for up-converting the 150MHz modulation signal from the frequency synthesizing unit 2 to 9.3 GHz-9.4 GHz, amplifying the power to 60W and then outputting the power.
The control unit 4 takes an FPGA chip as a core, converts an externally input RS422 serial port signal into a TTL level through a serial port level conversion circuit, inputs the TTL level into the FPGA, is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 in a bidirectional manner through printed board wires, and is used for completing control signal transmission with each module;
the power supply unit 5 is connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the control unit 4 in a unidirectional way through printed board wires and is used for supplying power to the modules;
the information processing unit 6 works on an FPGA chip in the control unit 4, and works for controlling and processing signals of the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 by analyzing an external RS422 serial port control signal entering the FPGA;
these units are integrated in the same module.
Further, the information processing unit 6 includes a serial port receiving module 61, a serial port transmitting module 62, a signal dynamic range control module 63, a chirp control module 64, a frequency hopping control module 65, and an internal timing control module 66;
the serial port receiving module 61 is connected with the serial port transmitting module 62 in a bidirectional manner, and is respectively connected with the signal dynamic range control module 63, the linear frequency modulation control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 in a unidirectional manner, and is used for completing the receiving of the external RS422 control command, analyzing the external RS422 control command and then transmitting the external RS422 control command to the serial port receiving module;
the serial port sending module 62 is connected with the signal dynamic range control module 63, the chirp control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 in a unidirectional manner, and is used for framing and packaging the current working states of the serial port receiving module 61, the signal dynamic range control module 63, the chirp control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 to form BITE data, and sending the BITE data to the external RS422 receiving equipment so as to monitor the working states of the current modules;
the signal dynamic range control module 63 is used for controlling the up-conversion attenuator to realize STC control and AGC control according to the gain control word received by the RS422 serial port;
the chirp control module 64 is connected with the internal timing control module 66 in a unidirectional manner, and controls the direct digital frequency synthesizer DDS1 to realize a chirp function according to the amplitude control signal OSK and the frequency modulation starting signal DRCTL generated by the internal timing control module 66;
the frequency hopping control module 65 is connected with the internal time sequence control module 66 in a unidirectional way, and controls the direct digital frequency synthesizer DDS2 to realize a frequency hopping function according to a frequency hopping enabling signal generated by the internal time sequence control module 66 and a frequency control word command issued by the serial port receiving module 61;
the internal timing control module 66 generates a power amplifier preheating signal, a receiving enabling signal, a transmitting enabling signal, an amplitude control signal OSK, a frequency modulation starting signal DRCTL signal, a frequency hopping enabling signal and a frequency modulation triggering signal according to an external input pulse repetition frequency PRF signal and an external triggering TR signal, and realizes synchronous control of all the modules.
Compared with the prior art, the invention has the following advantages:
1. the invention integrates the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3, the control unit 4, the power supply unit 5 and the information processing unit 6 into the same module, thereby enhancing the integration level of the transceiver module, reducing the volume and weight of the module and enhancing the reliability, the anti-interference performance and the low insertion loss of the transceiver module.
2. The control unit 4 of the invention uses the xinlinux FPGA as a platform to run the information processing unit 6, realizes the control of the transceiver through programming, enhances the digital programmable characteristic, the universality and the portability of the transceiver, and can be used for radars with different pulse widths and pulse frequencies.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a block diagram of an information processing unit in the present invention;
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, the present example includes a receiving unit 1, a frequency synthesizing unit 2, a transmitting unit 3, a control unit 4, a power supply unit 5, and an information processing unit 6. Wherein: the frequency synthesis unit 2 is connected with the receiving unit 1 and the transmitting unit 3 in a unidirectional manner through printed board wires, the control unit 4 is connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 in a bidirectional manner, and the power supply unit 5 is connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the control unit 4 in a unidirectional manner and is used for supplying power to the units.
The frequency synthesis unit 2 is configured to provide a local oscillation signal and a 150MHz intermediate frequency signal for the receiving unit 1 and the transmitting unit 3, respectively, and includes a direct digital frequency synthesizer DDS1, a direct digital frequency synthesizer DDS2, and a phase-locked loop. The direct digital frequency synthesizer DDS1 outputs intermediate frequency signals of 150MHz for up-conversion, the direct digital frequency synthesizer DDS2 outputs frequency hopping signals of 159MHz to 163MHz and 500kHz intervals, the frequency hopping signals are changed into frequency hopping signals of 1590MHz to 1690MHz after 10 times of frequency multiplication, the frequency hopping signals of 5MHz intervals are mixed with 6720MHz point frequency output by a phase-locked loop, and the obtained 8310MHz to 8410MHz frequency hopping signals are used as local oscillation signals;
the receiving unit 1 sequentially filters, amplifies and down-converts the received external radio frequency signals with low noise, generates 150MHz intermediate frequency signals and outputs the 150MHz intermediate frequency signals to an external signal processor to complete signal analysis, wherein the frequency synthesizing unit 2 provides 8310 MHz-8410 MHz local oscillation signals for the external radio frequency signals, so that the receiving unit 1 performs the down-conversion on the external radio frequency signals after the low noise amplification;
the transmitting unit 3 up-converts the 150MHz intermediate frequency signal from the frequency synthesizing unit 2 to 9.3 GHz-9.4 GHz, and then forms a high-power radio frequency signal through a filter, a driving amplifier and a power amplifier to be output to an external space;
the control unit 4 takes an FPGA chip as a core, converts an externally input RS422 serial port signal into a TTL level through a serial port level conversion circuit, inputs the TTL level into the FPGA, is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 in a bidirectional manner through printed board wires, and is used for completing control signal transmission with each module;
the power supply unit 5 is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the control unit 4 through printed board wires and is respectively provided with required +28V, 5V, -5V, +3.5V, +3.3V, +2.5V and +1.2V power supply voltages.
The information processing unit 6 works on an FPGA chip inside the control unit 4, and mainly performs analysis, framing and verification on an external RS422 serial port control signal entering the FPGA to complete work control, signal processing and reporting of the current working states of the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5.
Referring to fig. 2, the information processing unit 6 includes: a serial port receiving module 61, a serial port transmitting module 62, a signal dynamic range control module 63, a chirp control module 64, a frequency hopping control module 65 and an internal timing control module 66. Wherein:
the serial port receiving module 61 is connected with the serial port transmitting module 62 in a bidirectional manner, and is connected with the signal dynamic range control module 63, the linear frequency modulation control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 in a unidirectional manner respectively, mainly completes the receiving of an external RS422 control command, analyzes the received serial data, performs framing, frame header and frame tail checking work according to a data protocol, and transmits data containing information such as a working mode, frequency control, state control and the like to a module connected with the serial port receiving module after checking is correct; the module comprises a frequency division module sub-module 611, a data analysis sub-module 612 and a data framing sub-module 613; the frequency dividing sub-module 611 is connected with the data analyzing sub-module 612 in a unidirectional manner, and is used for dividing the frequency of the system input clock by 64 and transmitting the system input clock to the data analyzing sub-module 612; the data analysis sub-module 612 is connected with the data framing sub-module 613 in a unidirectional manner, and is used for analyzing the externally input RS422 serial data, transmitting the data to the data framing sub-module 613, framing the serial data according to a data protocol, checking the frame header and the frame tail by the data framing sub-module 613, and transmitting the checked data to other modules connected with the data framing sub-module 613;
the serial port sending module 62 is connected with the signal dynamic range control module 63, the chirp control module 64, the frequency hopping control module 65 and the internal timing control module 66 in a unidirectional manner, and is configured to frame and package the current working states of the serial port receiving module 61, the signal dynamic range control module 63, the chirp control module 64, the frequency hopping control module 65 and the internal timing control module 66 to form 8Byte BITE data, where the 8Byte BITE data includes fault information such as a repetition frequency PRF fault, an external trigger TR fault, a control command fault, a transmitting channel fault and the like, and send the fault information to the external RS422 receiving device to monitor the working states of the current modules;
the signal dynamic range control module 63 is used for receiving the gain control word according to the RS422 serial port and controlling the up-conversion attenuator to realize STC control and AGC control;
the chirp control module 64 is connected with the internal time sequence control module 66 in a unidirectional way, and controls the direct digital frequency synthesizer DDS1 to realize a chirp function according to the amplitude control signal OSK and the frequency modulation starting signal DRCTL generated by the internal time sequence control module 66; the module comprises a chirp sub-module 641 and a chirp data read-write sub-module 642, wherein the chirp sub-module 641 generates frequency modulation data and direct digital frequency synthesizer DDS1 configuration data according to an externally input control command, reads the data through the chirp data read-write sub-module 642 and writes the data into the direct digital frequency synthesizer DDS1, so as to complete the configuration of the direct digital frequency synthesizer DDS1 and realize a chirp function;
the frequency hopping control module 65 is connected with the internal time sequence control module 66 in a unidirectional way, and controls the direct digital frequency synthesizer DDS2 to realize a frequency hopping function according to a frequency hopping enabling signal generated by the internal time sequence control module 66 and a frequency control word command issued by the serial port receiving module 61; the module comprises a frequency hopping ROM reading submodule 651, a frequency hopping submodule 652 and a frequency hopping data reading and writing submodule 653; the frequency hopping sub-module 652 is connected with the frequency hopping ROM reading sub-module 651 and the frequency hopping data reading and writing sub-module 653 in one way respectively, the frequency hopping ROM reading sub-module 651 reads out the frequency control word stored in the read-only register ROM according to an external RS422 control command and transmits the frequency control word to the frequency hopping sub-module 652, the frequency hopping sub-module 652 generates frequency hopping data and configuration data of the direct digital frequency synthesizer DDS2 according to the frequency control word and the frequency hopping trigger signal, and the frequency hopping data reading and writing sub-module 653 reads the data and writes the data into the direct digital frequency synthesizer DDS2 to complete the configuration of the direct digital frequency synthesizer DDS2 and realize the frequency hopping function;
the internal timing control module 66 generates a power amplifier preheating signal, a receiving enabling signal, a transmitting enabling signal, an amplitude control signal OSK, a frequency modulation starting signal DRCTL signal, a frequency hopping enabling signal and a frequency modulation triggering signal according to an external input pulse repetition frequency PRF signal and an external trigger TR signal, so as to realize synchronous control of all the modules.
The example mainly realizes the transmission and the reception of the X-band microwave signals, and the working principle is as follows:
when the control unit 4 in the transceiver receives the external RS422 signal, the control unit 4 performs data analysis and framing on the external RS422 signal to obtain a control command, and transmits the control command to the receiving unit 1, the frequency synthesis unit 2 and the transmitting unit 3, where the receiving unit 1 and the transmitting unit 3 operate according to the control command:
if the control command is to open the transmitting channel and close the receiving channel, the transmitting unit 3 in the transceiver converts the intermediate frequency signal into an X-frequency band microwave signal after up-conversion, and outputs the X-frequency band microwave signal to the external space after amplification by the power amplifier;
if the control command is to open the receiving channel and close the transmitting channel, the receiving unit 1 in the transceiver converts the received X-band microwave echo signal down to form an intermediate frequency signal, and outputs the intermediate frequency signal to the external signal processor after pre-amplifying.
The foregoing description is only one specific example of the invention and is not intended to limit the invention in any way, and it will be apparent to those skilled in the art that various modifications and changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. An X-band programmable integrated transceiver, comprising:
the receiving unit (1) is used for finishing the frequency conversion treatment of the received 9.3 GHz-9.4 GHz radio frequency signals for 2 times, down-converting the received 9.3 GHz-9.4 GHz radio frequency signals into 150MHz intermediate frequency signals and finishing the amplification output of the intermediate frequency signals;
the frequency synthesis unit (2) is connected with the receiving unit (1) in one way through a printed board wire, generates a frequency hopping signal of 8310 MHz-8410 MHz as a second local oscillator, is used for down-conversion of the receiving unit (1), and generates an intermediate frequency signal of 150MHz +/-10 MHz-150 MHz +/-11 MHz for up-conversion; the unit comprises a direct digital frequency synthesizer DDS1, a direct digital frequency synthesizer DDS2 and a phase-locked loop;
the transmitting unit (3) is connected with the frequency synthesizing unit (2) in one way through a printed board wire and is used for up-converting the 150MHz modulation signal from the frequency synthesizing unit (2) to 9.3 GHz-9.4 GHz, amplifying the power to 60W and then outputting the power;
the control unit (4) takes an FPGA chip as a core, converts an externally input RS422 serial port signal into a TTL level through a serial port level conversion circuit, inputs the TTL level into the FPGA, and is respectively connected with the receiving unit (1), the frequency synthesis unit (2), the transmitting unit (3) and the power supply unit (5) in a bidirectional manner through printed board wires, and is used for completing control signal transmission with the units;
the power supply unit (5) is connected with the receiving unit (1), the frequency synthesis unit (2), the transmitting unit (3) and the control unit (4) in a unidirectional way through printed board wires and is used for supplying power to the units;
the information processing unit (6) works on an FPGA chip in the control unit (4), and works for controlling and processing signals of the receiving unit (1), the frequency synthesis unit (2), the transmitting unit (3) and the power supply unit (5) through analyzing an external RS422 serial port control signal entering the FPGA;
these units are integrated in the same module.
2. The transceiver of claim 1, characterized in that the information processing unit (6) comprises a serial port receiving module (61), a serial port transmitting module (62), a signal dynamic range control module (63), a chirp control module (64), a frequency hopping control module (65) and an internal timing control module (66);
the serial port receiving module (61) is in bidirectional connection with the serial port transmitting module (62) and is respectively in unidirectional connection with the signal dynamic range control module (63), the linear frequency modulation control module (64), the frequency hopping control module (65) and the internal time sequence control module (66), and is used for completing the receiving of an external RS422 control command, analyzing the external RS422 control command and then transmitting the external RS422 control command to the modules;
the serial port sending module (62) is respectively connected with the signal dynamic range control module (63), the linear frequency modulation control module (64), the frequency hopping control module (65) and the internal time sequence control module (66) in a unidirectional way, and is used for framing and packaging the current working states of the serial port receiving module (61), the signal dynamic range control module (63), the linear frequency modulation control module (64), the frequency hopping control module (65) and the internal time sequence control module (66) to form serial port feedback data BITE and sending the serial port feedback data BITE to the external RS422 receiving equipment so as to monitor the working states of the current modules;
the signal dynamic range control module (63) is used for controlling the up-conversion attenuator to realize time sensitivity control (STC) and Automatic Gain Control (AGC) according to the RS422 serial port receiving gain control word;
the linear frequency modulation control module (64) is connected with the internal time sequence control module (66) in a unidirectional way, and controls the direct digital frequency synthesizer DDS1 to realize a linear frequency modulation function according to an amplitude control signal OSK and a frequency modulation starting signal DRCTL generated by the internal time sequence control module (66);
the frequency hopping control module (65) is connected with the internal time sequence control module (66) in a one-way manner, and controls the direct digital frequency synthesizer DDS2 to realize a frequency hopping function according to a frequency hopping enabling signal generated by the internal time sequence control module (66) and a frequency control word command issued by the serial port receiving module (61);
the internal time sequence control module (66) generates a power amplifier preheating signal, a receiving enabling signal, a transmitting enabling signal, an amplitude control signal OSK, a frequency modulation starting signal DRCTL signal, a frequency hopping enabling signal and a frequency modulation triggering signal according to an external input pulse repetition frequency PRF signal and an external trigger TR signal, and realizes synchronous control of all the modules.
3. The transceiver of claim 2, characterized in that the serial port receiving module (61) comprises a frequency dividing module sub-module (611), a data parsing sub-module (612) and a data framing sub-module (613);
the frequency dividing sub-module (611) is connected with the data analyzing sub-module (612) in a unidirectional way, and is used for carrying out 64 frequency division on the system input clock and then transmitting the system input clock to the data analyzing sub-module (612);
the data analysis sub-module (612) is connected with the data framing sub-module (613) in a one-way, and is used for analyzing the RS422 serial data input from the outside, transmitting the data to the data framing sub-module (613), framing the serial data according to a data protocol, checking the frame head and the frame tail by the data framing sub-module (613), and transmitting the checked data to other modules connected with the data analysis sub-module.
4. The transceiver of claim 2, wherein the chirp control module (64) includes a chirp sub-module (641) and a chirp data read-write sub-module (642), the chirp sub-module (641) generates frequency modulation data and direct digital frequency synthesizer DDS1 configuration data according to an externally input control command, and reads the data through the chirp data read-write sub-module (642) and writes the data into the direct digital frequency synthesizer DDS1 to complete the configuration of the direct digital frequency synthesizer DDS1 and realize a chirp function.
5. The transceiver according to claim 2, characterized in that the frequency hopping control module (65) comprises a frequency hopping ROM reading sub-module (651), a frequency hopping sub-module (652) and a frequency hopping frequency data reading and writing sub-module (653);
the frequency hopping sub-module (652) is respectively connected with the frequency hopping ROM reading sub-module (651) and the frequency hopping data reading and writing sub-module (653) in a unidirectional mode, the frequency hopping ROM reading sub-module (651) reads out the frequency control word stored in the read-only register ROM according to an external RS422 control command and transmits the frequency control word to the frequency hopping sub-module (652), the frequency hopping sub-module (652) generates frequency hopping data and configuration data of the direct digital frequency synthesizer DDS2 according to the frequency control word and the frequency hopping trigger signal, and the frequency hopping data reading and writing sub-module (653) reads the data and writes the data into the direct digital frequency synthesizer DDS2 to complete the configuration of the direct digital frequency synthesizer DDS2 and realize the frequency hopping function.
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| CN114389636B (en) * | 2022-01-13 | 2024-01-05 | 中国人民解放军96901部队25分队 | Multi-band high-performance signal processing platform |
| CN117375649A (en) * | 2022-06-30 | 2024-01-09 | 中兴通讯股份有限公司 | Signal transmission method, radio frequency system, unit and storage medium |
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