CN112448735A - X-waveband programmable integrated transceiver - Google Patents
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Abstract
The invention discloses an X-waveband programmable integrated transceiver, which comprises a receiving unit, a frequency synthesis unit, a transmitting unit, a control unit, a power supply unit and an information processing unit. The information processing unit receives the external serial port signal and the external time sequence, analyzes and frames the serial port signal, generates the internal time sequence and sends the internal time sequence to all units connected with the information processing unit; the frequency synthesis unit generates a modulation signal and a second local oscillation signal according to the instruction and the internal time sequence; when the receiving unit works and the transmitting unit is closed, received 9.3-9.4 GHz radio frequency input is subjected to down-conversion twice to form 150MHz intermediate frequency signal output, and when the transmitting unit works and the receiving unit is closed, the 150MHz intermediate frequency from the frequency integrated module is subjected to up-conversion to 9.3-9.4 GHz high frequency signals, and the signals are amplified to 60W through power amplification and output. The invention has high integration level, digital programming, portability and strong universality, and can be used for receiving and transmitting radar electromagnetic waves.
Description
Technical Field
The invention belongs to the technical field of communication, in particular to an X-band programmable integrated transceiver which can be used for receiving and transmitting radar electromagnetic waves.
Background
The radar transmitting module and the receiving module are important components in a radar communication system. Modern radar signals generally comprise low-frequency signals, intermediate-frequency signals and high-frequency signals, wherein the high-frequency signals are microwave signals, and electromagnetic waves in a required frequency range are radiated to a space after the high-frequency signals are generated by a radar microwave transmitting module; the radar receiving module converts the received electromagnetic echo signals into intermediate frequency signals for a signal processor to use after the processes of amplification, filtering, demodulation and the like.
The traditional radar transmitting module and the radar receiving module exist as two separated independent units, and for the airborne weather radar, the width, the amplitude and the pulse repetition frequency of a radio frequency pulse signal when the airborne weather radar works in a selected mode are all fixed and unchanged, but the modern weather radar requires that the pulse width can be automatically adjusted within a required range to realize the optimization of the radar performance, and for the airborne weather radar, a host factory has higher requirements on the volume and the weight of the radar, the separated radar transmitter and the separated radar receiver invisibly increase the volume and the weight of the radar, and more interpolation loss is introduced in the transmission process of the signal.
In order to solve the defects of the two separation modules, the prior art provides an X-waveband continuous solid-state transceiving component, the transceiving component integrates a radar receiving module and a transmitting module into the same shell, and a vibration frequency circuit is added in the middle of the shell of the transceiving module.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an X-waveband programmable integrated transceiver, which changes the width, the amplitude and the pulse repetition frequency of a radio frequency pulse signal in a software programming mode, enhances the integration characteristic and the digital programmable characteristic of a transceiver module and meets the requirement that the pulse width can be automatically adjusted within a required range required by the modern weather radar.
To achieve the above object, the present invention provides an X-band programmable integrated transceiver, comprising:
the receiving unit 1 is used for completing the frequency conversion processing of received 9.3 GHz-9.4 GHz radio frequency signals for 2 times, performing down-conversion to 150MHz intermediate frequency signals, and completing the amplification output of the intermediate frequency signals;
the frequency synthesis unit 2 is connected with the receiving unit 1 in a one-way mode through a printed board line, generates a frequency hopping signal of 8310 MHz-8410 MHz as a second local oscillator, is used for down-conversion of the receiving unit 1, and generates a modulation signal of 150MHz +/-10 MHz-150 MHz +/-11 MHz for up-conversion;
and the transmitting unit 3 is unidirectionally connected with the frequency synthesis unit 2 through a printed board line, and is used for up-converting the 150MHz modulation signal from the frequency synthesis unit 2 to 9.3 GHz-9.4 GHz, amplifying the frequency signal to 60W and outputting the amplified frequency signal.
The control unit 4 takes an FPGA chip as a core, converts an externally input RS422 serial port signal into a TTL level through a serial port level conversion circuit, inputs the TTL level into the FPGA, is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 in a bidirectional mode through printed board lines, and is used for finishing control signal transmission with each module;
the power supply unit 5 is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the control unit 4 in a one-way mode through printed circuit board lines and is used for supplying power to the modules;
the information processing unit 6 works on an FPGA chip in the control unit 4, and completes work control and signal processing of the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 by analyzing an external RS422 serial port control signal entering the FPGA;
these units are integrated in the same module.
Further, the information processing unit 6 includes a serial port receiving module 61, a serial port transmitting module 62, a signal dynamic range control module 63, a chirp control module 64, a frequency hopping control module 65, and an internal timing control module 66;
the serial port receiving module 61 is bidirectionally connected with the serial port transmitting module 62, is unidirectionally connected with the signal dynamic range control module 63, the linear frequency modulation control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 respectively, is used for receiving an external RS422 control command, and then transmits the received external RS422 control command to the modules after being analyzed;
the serial port sending module 62 is respectively connected with the signal dynamic range control module 63, the linear frequency modulation control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 in a one-way manner, and is used for framing and packaging the current working states of the serial port receiving module 61, the signal dynamic range control module 63, the linear frequency modulation control module 64, the frequency hopping control module 65 and the internal time sequence control module 66 to form BITE data, and sending the BITE data to external RS422 receiving equipment so as to monitor the current working states of the modules;
the signal dynamic range control module 63 receives the gain control word according to the RS422 serial port, and controls the up-conversion attenuator to realize STC control and AGC control;
the chirp control module 64 is connected to the internal timing control module 66 in a single direction, and controls the direct digital frequency synthesizer DDS1 to implement a chirp function according to the amplitude control signal OSK and the frequency modulation start signal DRCTL generated by the internal timing control module 66;
the frequency hopping control module 65 is connected with the internal timing control module 66 in a unidirectional manner, and controls the direct digital frequency synthesizer DDS2 to realize a frequency hopping function according to a frequency hopping enable signal generated by the internal timing control module 66 and a frequency control word command issued by the serial port receiving module 61;
the internal timing control module 66 generates a power amplifier preheating signal, a reception enable signal, a transmission enable signal, an amplitude control signal OSK, a frequency modulation start signal DRCTL signal, a frequency hopping enable signal, and a frequency modulation trigger signal according to an externally input pulse repetition frequency PRF signal and an externally triggered TR signal, thereby realizing synchronous control of the modules.
Compared with the prior art, the invention has the following advantages:
1. according to the invention, the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3, the control unit 4, the power supply unit 5 and the information processing unit 6 are integrated in the same module, so that the integration level of the receiving and transmitting module is enhanced, the size and the weight of the module are reduced, and the reliability, the anti-interference performance and the low insertion loss of the receiving and transmitting module are enhanced.
2. The control unit 4 of the invention uses the Xinlinx FPGA as a platform to operate the information processing unit 6, and realizes the control of the transceiver through programming, thereby enhancing the digital programmable characteristic, the universality and the portability of the transceiver, and being applicable to radars with different pulse widths and pulse frequencies.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a block diagram of an information processing unit in the present invention;
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, the present example includes a receiving unit 1, a frequency synthesizing unit 2, a transmitting unit 3, a control unit 4, a power supply unit 5, and an information processing unit 6. Wherein: the frequency synthesis unit 2 is respectively connected with the receiving unit 1 and the transmitting unit 3 in a one-way mode through printed board lines, the control unit 4 is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 in a two-way mode, and the power supply unit 5 is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the control unit 4 in a one-way mode and used for supplying power to the units.
The frequency synthesis unit 2 is configured to provide the local oscillator signal and the 150MHz intermediate frequency signal for the receiving unit 1 and the transmitting unit 3, respectively, and includes a direct digital frequency synthesizer DDS1, a direct digital frequency synthesizer DDS2, and a phase-locked loop. The direct digital frequency synthesizer DDS1 outputs 150MHz intermediate frequency signals for up-conversion, the direct digital frequency synthesizer DDS2 outputs frequency hopping signals with the frequency of 159 MHz-163 MHz and the interval of 500kHz, the frequency of the frequency hopping signals is changed into 1590 MHz-1690 MHz after 10 frequency doubling, the interval of the frequency hopping signals is 5MHz, and 8310 MHz-8410 MHz frequency hopping signals obtained after frequency mixing with 6720MHz dot frequency output by a phase-locked loop are used as local oscillation signals;
the receiving unit 1 sequentially filters, amplifies low noise and performs secondary down-conversion on the received external radio frequency signal to generate a 150MHz intermediate frequency signal, and outputs the 150MHz intermediate frequency signal to an external signal processor to complete signal analysis, and in the process, the frequency synthesis unit 2 provides a local oscillation signal of 8310 MHz-8410 MHz for the local oscillation signal, so that the receiving unit 1 performs secondary down-conversion on the external radio frequency signal after low noise amplification is completed;
the transmitting unit 3 performs up-conversion on the 150MHz intermediate frequency signal from the frequency synthesis unit 2 to 9.3 GHz-9.4 GHz, and then the signal passes through a filter, a driving amplifier and a power amplifier to form a high-power radio frequency signal and output the high-power radio frequency signal to an external space;
the control unit 4 takes an FPGA chip as a core, converts an externally input RS422 serial port signal into a TTL level through a serial port level conversion circuit, inputs the TTL level into the FPGA, is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 in a bidirectional mode through printed board lines, and is used for completing control signal transmission between each module;
the power supply unit 5 is respectively connected with the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the control unit 4 through printed board lines, and provides required +28V, 5V, -5V, +3.5V, +3.3V, +2.5V and +1.2V power supply voltages for the power supply unit;
the information processing unit 6 works on the FPGA chip inside the control unit 4, and completes work control, signal processing and current work state reporting of the receiving unit 1, the frequency synthesis unit 2, the transmitting unit 3 and the power supply unit 5 mainly by analyzing, framing and verifying an external RS422 serial port control signal entering the FPGA.
Referring to fig. 2, the information processing unit 6 includes: the device comprises a serial port receiving module 61, a serial port sending module 62, a signal dynamic range control module 63, a linear frequency modulation control module 64, a frequency hopping control module 65 and an internal timing control module 66. Wherein:
the serial port receiving module 61 is bidirectionally connected with the serial port sending module 62, is respectively unidirectionally connected with the signal dynamic range control module 63, the linear frequency modulation control module 64, the frequency hopping control module 65 and the internal time sequence control module 66, mainly completes the receiving of an external RS422 control command, analyzes the received serial data, performs framing and frame header and frame tail checking work according to a data protocol, and sends data containing information such as a working mode, frequency control, state control and the like to a module connected with the serial port receiving module after checking is correct; the module comprises a frequency division module submodule 611, a data analysis submodule 612 and a data framing submodule 613; the frequency division submodule 611 is unidirectionally connected with the data analysis submodule 612, and is used for performing frequency division on a system input clock by 64 and transmitting the frequency-divided system input clock to the data analysis submodule 612; the data parsing sub-module 612 is unidirectionally connected with the data framing sub-module 613, and is configured to parse externally input RS422 serial port data and transmit the parsed serial port data to the data framing sub-module 613, and the data framing sub-module 613 frames the serial port data according to a data protocol, checks a frame header and a frame tail, and sends the checked data to other modules connected to the data framing sub-module 613;
the serial port sending module 62 is respectively connected with the signal dynamic range control module 63, the chirp control module 64, the frequency hopping control module 65 and the internal timing control module 66 in a one-way manner, and is used for framing and packaging the current working states of the serial port receiving module 61, the signal dynamic range control module 63, the chirp control module 64, the frequency hopping control module 65 and the internal timing control module 66 to form 8Byte BITE data, wherein the 8Byte BITE data comprises fault information such as a repetition frequency PRF fault, an external trigger TR fault, a control command fault and a transmitting channel fault and the like, and is sent to external RS422 receiving equipment to monitor the current working states of the modules;
the signal dynamic range control module 63 receives the gain control word according to the RS422 serial port and controls the up-conversion attenuator to realize STC control and AGC control;
the linear frequency modulation control module 64 is connected with the internal timing control module 66 in a unidirectional manner, and controls the direct digital frequency synthesizer DDS1 to realize a linear frequency modulation function according to the amplitude control signal OSK and the frequency modulation starting signal DRCTL generated by the internal timing control module 66; the module comprises a chirp submodule 641 and a chirp data read-write submodule 642, wherein the chirp submodule 641 generates frequency modulation data and configuration data of a direct digital frequency synthesizer DDS1 according to an externally input control command, reads the data through the chirp data read-write submodule 642 and writes the data into the direct digital frequency synthesizer DDS1, so that the configuration of the direct digital frequency synthesizer DDS1 is completed, and a chirp function is realized;
the frequency hopping control module 65 is connected with the internal timing control module 66 in a unidirectional manner, and controls the direct digital frequency synthesizer DDS2 to realize a frequency hopping function according to a frequency hopping enable signal generated by the internal timing control module 66 and a frequency control word command issued by the serial port receiving module 61; the module comprises a frequency hopping ROM reading sub-module 651, a frequency hopping sub-module 652 and a frequency hopping data reading and writing sub-module 653; the frequency hopping submodule 652 is respectively connected with a frequency hopping ROM reading submodule 651 and a frequency hopping data reading and writing submodule 653 in a one-way mode, the frequency hopping ROM reading submodule 651 reads out frequency control words stored in a read-only register ROM according to an external RS422 control command and transmits the frequency control words to the frequency hopping submodule 652, the frequency hopping submodule 652 generates frequency hopping data and configuration data of a direct digital frequency synthesizer DDS2 according to the frequency control words and a frequency hopping trigger signal, and the data are read by the frequency hopping data reading and writing submodule 653 and written into a direct digital frequency synthesizer DDS2, so that the configuration of the direct digital frequency synthesizer DDS2 is completed, and the frequency hopping function is realized;
the internal timing control module 66 generates a power amplifier preheating signal, a receiving enabling signal, a transmitting enabling signal, an amplitude control signal OSK, a frequency modulation starting signal DRCTL signal, a frequency hopping enabling signal and a frequency modulation trigger signal according to an externally input pulse repetition frequency PRF signal and an externally triggered TR signal, thereby realizing synchronous control of the modules.
The example mainly realizes the transmission and the reception of the microwave signals of the X wave band, and the working principle is as follows:
when the control unit 4 in the transceiver receives the external RS422 signal, the control unit 4 performs data analysis and framing on the external RS422 signal to obtain a control command, and transmits the control command to the receiving unit 1, the frequency synthesizing unit 2 and the transmitting unit 3, and the receiving unit 1 and the transmitting unit 3 operate according to the control command:
if the control command is to open the transmitting channel and close the receiving channel, the transmitting unit 3 in the transceiver converts the intermediate frequency signal into an X frequency band microwave signal after up-conversion, and outputs the microwave signal to the external space after being amplified by the power amplifier;
if the control command is to open the receiving channel and close the transmitting channel, the receiving unit 1 in the transceiver forms an intermediate frequency signal after down-conversion of the received X-band microwave echo signal, and outputs the intermediate frequency signal to an external signal processor after pre-amplification.
The foregoing description is only an example of the present invention and should not be construed as limiting the invention, as it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the invention after understanding the present disclosure and the principles, but such modifications and variations are considered to be within the scope of the appended claims.
Claims (5)
1. An X-band programmable integrated transceiver, comprising:
the receiving unit (1) is used for completing the frequency conversion processing of received 9.3 GHz-9.4 GHz radio frequency signals for 2 times, performing down-conversion to 150MHz intermediate frequency signals, and completing the amplification output of the intermediate frequency signals;
the frequency synthesis unit (2) is connected with the receiving unit (1) in a one-way mode through a printed board line, generates a frequency hopping signal of 8310 MHz-8410 MHz as a second local oscillator, is used for down-conversion of the receiving unit (1), and generates an intermediate frequency signal of 150MHz +/-10 MHz-150 MHz +/-11 MHz for up-conversion;
and the transmitting unit (3) is unidirectionally connected with the frequency synthesis unit (2) through a printed board line, and is used for up-converting the 150MHz modulation signal from the frequency synthesis module (2) to 9.3 GHz-9.4 GHz, amplifying the power to 60W and outputting the signal.
The control unit (4) takes an FPGA chip as a core, converts an externally input RS422 serial port signal into a TTL level through a serial port level conversion circuit, inputs the TTL level into the FPGA, is respectively connected with the receiving unit (1), the frequency synthesis unit (2), the transmitting unit (3) and the power supply unit (5) in a bidirectional mode through printed board lines, and is used for finishing control signal transmission between each module;
the power supply unit (5) is respectively connected with the receiving unit (1), the frequency synthesis unit (2), the transmitting unit (3) and the control unit (4) in a one-way mode through printed circuit board lines and is used for supplying power to the modules;
the information processing unit (6) works on an FPGA chip in the control unit (4), and finishes work control and signal processing of the receiving unit (1), the frequency synthesis unit (2), the transmitting unit (3) and the power supply unit (5) by analyzing an external RS422 serial port control signal entering the FPGA;
these units are integrated in the same module.
2. The transceiver according to claim 1, wherein the information processing unit (6) comprises a serial port receiving module (61), a serial port transmitting module (62), a signal dynamic range control module (63), a chirp control module (64), a frequency hopping control module (65), and an internal timing control module (66);
the serial port receiving module (61) is connected with the serial port sending module (62) in a bidirectional mode, is respectively connected with the signal dynamic range control module (63), the linear frequency modulation control module (64), the frequency hopping control module (65) and the internal time sequence control module (66) in a unidirectional mode, is used for receiving an external RS422 control command, analyzes the received external RS422 control command and then sends the analyzed external RS422 control command to the modules;
the serial port sending module (62) is respectively connected with the signal dynamic range control module (63), the linear frequency modulation control module (64), the frequency hopping control module (65) and the internal time sequence control module (66) in a one-way mode and is used for framing and packaging the current working states of the serial port receiving module (61), the signal dynamic range control module (63), the linear frequency modulation control module (64), the frequency hopping control module (65) and the internal time sequence control module (66) to form BITE data which is sent to external RS422 receiving equipment so as to monitor the current working states of the modules;
the signal dynamic range control module (63) receives the gain control word according to the RS422 serial port and controls the up-conversion attenuator to realize STC control and AGC control;
the linear frequency modulation control module (64) is connected with the internal time sequence control module (66) in a one-way mode, and controls the direct digital frequency synthesizer DDS1 to realize a linear frequency modulation function according to an amplitude control signal OSK and a frequency modulation starting signal DRCTL generated by the internal time sequence control module (66);
the frequency hopping control module (65) is connected with the internal time sequence control module (66) in a one-way mode, and controls the direct digital frequency synthesizer DDS2 to realize the frequency hopping function according to a frequency hopping enabling signal generated by the internal time sequence control module (66) and a frequency control word command issued by the serial port receiving module (61);
the internal time sequence control module (66) generates a power amplifier preheating signal, a receiving enabling signal, a transmitting enabling signal, an amplitude control signal OSK, a frequency modulation starting signal DRCTL signal, a frequency hopping enabling signal and a frequency modulation trigger signal according to an externally input pulse repetition frequency PRF signal and an externally triggered TR signal, and realizes synchronous control of all modules.
3. The transceiver of claim 2, wherein the serial port receiving module (61) comprises a frequency division module submodule (611), a data parsing submodule (612) and a data framing submodule (613);
the frequency division submodule (611) is connected with the data analysis submodule (612) in a one-way mode and is used for carrying out frequency division on a system input clock by 64 and transmitting the frequency-divided system input clock to the data analysis submodule (612);
the data analysis submodule (612) is unidirectionally connected with the data framing submodule (613), and is used for analyzing externally input RS422 serial port data and transmitting the data to the data framing submodule (613), and the data framing submodule (613) frames the serial port data according to a data protocol, checks a frame head and a frame tail, and transmits the checked data to other modules connected with the data framing submodule.
4. The transceiver of claim 2, wherein the chirp control module (64) comprises a chirp sub-module (641) and a chirp data read-write sub-module (642), the chirp sub-module (641) generates the chirp data and the configuration data of the direct digital frequency synthesizer DDS1 according to an externally input control command, and reads the data through the chirp data read-write sub-module (642) and writes the data into the direct digital frequency synthesizer DDS1, thereby completing the configuration of the direct digital frequency synthesizer DDS1 and realizing the chirp function.
5. The transceiver of claim 2, wherein the frequency hopping control module (65) comprises a frequency hopping ROM read sub-module (651), a frequency hopping sub-module (652) and a frequency hopping data read-write sub-module (653);
the frequency hopping submodule (652) is respectively connected with a frequency hopping ROM reading submodule (651) and a frequency hopping data reading and writing submodule (653) in a one-way mode, the frequency hopping ROM reading submodule (651) reads out frequency control words stored in a read-only register ROM according to an external RS422 control command and transmits the frequency control words to the frequency hopping submodule (652), the frequency hopping submodule (652) generates frequency hopping data and configuration data of a direct digital frequency synthesizer DDS2 according to the frequency control words and a frequency hopping trigger signal, and the frequency hopping data are read by the frequency hopping data reading and writing submodule (653) and written into a direct digital frequency synthesizer DDS2, so that the configuration of the direct digital synthesizer DDS2 is completed, and the frequency hopping function is realized.
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| CN113225022A (en) * | 2021-04-30 | 2021-08-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Ultra-wideband up-converter |
| CN114389636A (en) * | 2022-01-13 | 2022-04-22 | 中国人民解放军96901部队25分队 | Multi-band high-performance signal processing platform |
| WO2024001419A1 (en) * | 2022-06-30 | 2024-01-04 | 中兴通讯股份有限公司 | Signal transmission method, radio frequency system, unit, and storage medium |
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