CN112434324B - Data processing equipment - Google Patents

Data processing equipment Download PDF

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Publication number
CN112434324B
CN112434324B CN202011496844.1A CN202011496844A CN112434324B CN 112434324 B CN112434324 B CN 112434324B CN 202011496844 A CN202011496844 A CN 202011496844A CN 112434324 B CN112434324 B CN 112434324B
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Prior art keywords
encryption device
encryption
data processing
processor
data
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CN202011496844.1A
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CN112434324A (en
Inventor
王京阳
李磊
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Hefei Datang Storage Technology Co ltd
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Hefei Datang Storage Technology Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60Protecting data
    • G06F21/602Providing cryptographic facilities or services
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/44Program or device authentication

Abstract

The application provides a data processing apparatus comprising: a processor, two or more encryption devices; a processor configured to send a generation instruction to generate a key to a default encryption device, and send a first synchronization instruction to the default encryption device; the encryption device is arranged to receive a generation instruction from the processor when the encryption device is a default encryption device, generate a key and store the generated key; receiving a first synchronization instruction from a processor, and sending the generated secret key to each encryption device except the secret key; encrypting the received data according to the generated secret key; when the device is an encryption device except a default encryption device, receiving and storing a key from the default encryption device; and encrypting the received data according to the obtained secret key. According to the technical scheme, when part of the encryption device fails, normal operation of the data processing equipment is still ensured.

Description

Data processing equipment
Technical Field
The present application relates to the field of information security, but is not limited to, and in particular to data processing apparatus.
Background
As the size of the enterprise information center is continuously enlarged, the information security problem is gradually paid attention to. Currently, two types of encryption mechanisms exist, one is software encryption and the other is hardware encryption. The software encryption is simple to realize, the investment is small, but the secret key and the algorithm are easy to leak, and the security level is low. The hardware encryption adopts a hardware encryption machine to carry out encryption and decryption calculation, equipment investment is required to be increased, but the protection of keys and algorithms is more sufficient.
When the existing encryption equipment fails, data processing is needed to be carried out through other encryption equipment, so that the equipment cost is high.
Disclosure of Invention
The technology to be solved by the application is to provide the data processing equipment, which can still ensure the normal operation of the data processing equipment when a part of encryption devices fail.
In order to solve the above technical problem, the present application provides a data processing apparatus, including: a processor, two or more encryption devices;
the processor is configured to send a generation instruction for generating a key to a default encryption device, and send a first synchronization instruction to the default encryption device, where the first synchronization instruction is used to instruct to send the generated key to each encryption device except the default encryption device in synchronization;
the encryption device is arranged to receive a generation instruction from the processor when the encryption device is a default encryption device, generate a key and store the generated key; receiving a first synchronization instruction from a processor, and sending the generated key to each encryption device except the encryption device; encrypting the received data according to the generated secret key; when the device is an encryption device except a default encryption device, receiving and storing a key from the default encryption device; and encrypting the received data according to the obtained secret key.
In an exemplary embodiment, the processor is further configured to send the received data to a selected encryption device;
the encryption device is further configured to encrypt the data according to the key stored by the encryption device when the data sent by the processor is received, and store the encrypted data.
In an exemplary embodiment, the system further comprises at least two expansion interfaces, and each encryption device is connected with one expansion interface in a hot plug manner.
In an exemplary embodiment, the number of encryption devices is less than or equal to the number of expansion interfaces.
In one illustrative example, each encryption device includes a secure memory chip;
the encryption chip is configured to store encrypted data, and includes: and storing the encrypted data in a self secure memory chip.
In an exemplary embodiment, the processor is further configured to send the received data to a selected encryption device, including:
selecting a target encryption device from all encryption devices according to the load information of each encryption device, and sending the received data to the encryption device as a first target.
In an exemplary embodiment, the selecting an encryption device as a first target from all encryption devices according to the load information of each encryption device, and transmitting the received data to the encryption device as the target includes:
and selecting the encryption device with the lowest load according to the load of each encryption device, and sending the received data to the encryption device with the lowest load.
In an exemplary embodiment, the processor is further configured to perform a trust verification on each encryption device when the data processing apparatus is powered on, and to set the data processing apparatus to an unavailable state when the trust verification of any encryption device fails.
In an exemplary embodiment, the processor is further configured to perform a trust verification on the newly inserted encryption device when a new encryption device is detected to be inserted during operation of the data processing apparatus, and to set the newly inserted encryption device to an unavailable state when the trust verification on the newly inserted encryption device is not passed.
In an exemplary embodiment, the processor is further configured to send a second synchronization instruction to any encryption device, where the second synchronization instruction is used to instruct the decryption device to backup the stored data to the encryption device that is the second target, and the second synchronization instruction carries identification information of the encryption device that is the target;
the encryption device is further configured to send the data stored in the encryption device to the encryption device as the second target after receiving the second synchronization instruction.
The application provides a data processing apparatus comprising: a processor, two or more encryption devices; the processor is configured to send a generation instruction for generating a key to a default encryption device, and send a first synchronization instruction to the default encryption device, where the first synchronization instruction is used to instruct to send the generated key to each encryption device except the default encryption device in synchronization; the encryption device is arranged to receive a generation instruction from the processor when the encryption device is a default encryption device, generate a key and store the generated key; receiving a first synchronization instruction from a processor, and sending the generated key to each encryption device except the encryption device; encrypting the received data according to the generated secret key; when the device is an encryption device except a default encryption device, receiving and storing a key from the default encryption device; and encrypting the received data according to the obtained secret key. According to the technical scheme, the plurality of encryption devices are arranged, the secret keys are synchronously stored in the plurality of encryption devices, and when part of encryption devices fail, other encryption devices can be used for data processing, so that the normal operation of the data processing equipment is ensured.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a schematic diagram of a data processing apparatus according to a first embodiment of the present application;
fig. 2 is a schematic diagram of a data processing apparatus according to an example one of the present application.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Example 1
As shown in fig. 1, the present embodiment provides a data processing apparatus including: a processor 10, two or more encryption devices 11;
the processor 10 is configured to send a generation instruction for generating a key to a default encryption device, and send a first synchronization instruction to the default encryption device, the first synchronization instruction being configured to instruct to send the generated key to each encryption device other than the default encryption device in synchronization;
the encryption device 11 is configured to receive a generation instruction from the processor, generate a key, and store the generated key when the encryption device is a default encryption device; receiving a first synchronization instruction from a processor, and sending the generated key to each encryption device except the encryption device; encrypting the received data according to the generated secret key; when the device is an encryption device except a default encryption device, receiving and storing a key from the default encryption device; and encrypting the received data according to the obtained secret key.
In this embodiment, one of all the expansion interfaces may be set as a default expansion interface, and the encryption device connected to the default expansion interface is a default encryption device (for example, may be named as a number 0 encryption device, and will be described below as a number 0 encryption device). The key is typically generated by the number 0 encryption device, and then the number 0 encryption device securely transmits the generated key to each of the other encryption devices. It should be noted that, the physical device corresponding to the No. 0 encryption device may be not fixed, for example, there are currently an encryption device a and an encryption device b, if the encryption device a is connected to the default expansion interface, the encryption device a is the No. 0 encryption device, and if the encryption device b is connected to the default expansion interface, the encryption device b is the No. 0 encryption device.
After the key is synchronized to each encryption device, each encryption device encrypts data using the key, for example, using the SM4 encryption algorithm. Meanwhile, since each encryption device stores the same secret key, when one or more encryption devices fail (such as software and hardware failure, secret key loss and the like), since other normal encryption devices without failure store the secret key, the other normal encryption devices without failure can still be used for data encryption processing and storage, thereby ensuring the normal operation of the data processing equipment.
According to the technical scheme, the plurality of encryption devices are arranged, the secret keys are synchronously stored in the plurality of encryption devices, and when part of encryption devices fail, other encryption devices can be used for data processing, so that the normal operation of the data processing equipment is ensured.
In an exemplary embodiment, the processor is further configured to send the received data to a selected encryption device;
the encryption device is further configured to encrypt the data according to the key stored by the encryption device when the data sent by the processor is received, and store the encrypted data.
In an exemplary embodiment, the system further comprises at least two expansion interfaces, and each encryption device is connected with one expansion interface in a hot plug manner.
In an exemplary embodiment, the number of encryption devices is less than or equal to the number of expansion interfaces.
In this embodiment, each data processing apparatus may be configured with a plurality of encryption devices and a plurality of expansion interfaces, and a certain number of expansion interfaces not connected to the encryption devices are reserved in an initial state of the data processing apparatus, so that in a subsequent use, the encryption devices may be dynamically increased according to data throughput. For example, a data processing apparatus may be provided with 64 expansion interfaces, wherein 32 expansion interfaces are respectively connected to one encryption device, that is, 32 encryption devices. If the current user's computing power demand exceeds the current data processing apparatus' computing power, one or more new encryption devices may be inserted in an un-powered state to increase the computing power of the data processing apparatus.
In one illustrative example, each encryption device includes a secure memory chip;
the encryption chip is configured to store encrypted data, and includes: and storing the encrypted data in a self secure memory chip.
The secure memory chip of this embodiment may be a Nand flash memory chip.
The encrypted data can be directly stored in the self-safe storage chip through the technology, so that the risk of data leakage can be reduced, and the safety of the data is ensured.
In an exemplary embodiment, the processor is further configured to send the received data to a selected encryption device, including:
selecting a target encryption device from all encryption devices according to the load information of each encryption device, and sending the received data to the encryption device as a first target.
In an exemplary embodiment, the selecting an encryption device as a first target from all encryption devices according to the load information of each encryption device, and transmitting the received data to the encryption device as the target includes:
and selecting the encryption device with the lowest load according to the load of each encryption device, and sending the received data to the encryption device with the lowest load.
In an exemplary embodiment, the processor is further configured to perform a trust verification on each encryption device when the data processing apparatus is powered on, and to set the data processing apparatus to an unavailable state when the trust verification of any encryption device fails.
In an exemplary embodiment, the processor is further configured to perform a trust verification on the newly inserted encryption device when a new encryption device is detected to be inserted during operation of the data processing apparatus, and to set the newly inserted encryption device to an unavailable state when the trust verification on the newly inserted encryption device is not passed.
In an exemplary embodiment, the processor is further configured to send a second synchronization instruction to any encryption device, where the second synchronization instruction is used to instruct the decryption device to backup the stored data to the encryption device that is the second target, and the second synchronization instruction carries identification information of the encryption device that is the second target;
the encryption device is further configured to send the data stored by itself to the targeted encryption device after receiving the second synchronization instruction.
By the technical scheme, the data of the encryption device can be backed up, and the reliability of data storage is improved.
In an illustrative example, the type of the encryption device may be SSD (Solid State Disk or Solid State Drive, solid State Disk), and the type of the expansion interface may include an interface compatible with SSD, such as SATA (Serial ATA), SATAe, U.2, mdata, m.2, PCIe (Peripheral Component Interconnect express, a high-speed Serial computer expansion bus standard), SAS (Serial Attached SCSI, serial SCSI), and the like.
Example one
The data processing device of the present application is further illustrated by a specific example below.
As shown in fig. 2, the data processing apparatus of the present example may include: at least one processor 101 (i.e. the aforementioned processor), at least one network interface 102, at least one secure storage expansion interface 103 (i.e. the aforementioned expansion interface), at least one security module 105 (i.e. the aforementioned encryption device), at least one memory 106, at least one communication bus 104.
Wherein each data processing device can load a plurality of security modules 105 through the security module extension interface 103. The memory 106 stores security module mutual trust software for mutual authentication between each security module and load balancing software for task allocation to each security module 105.
Each of the security modules 105 may include a security memory chip 1051, a Nand flash memory chip 1052, and an interface unit 1053. The secure memory chip 1051 is a main controller chip in the secure module, and is used for encrypting data, the Nand flash memory chip 1052 is a memory granule, and is used for storing the data encrypted by the secure memory chip, and the interface unit 1053 is used for receiving the data sent by the processor 101.
Assume that scenario one is: the data acquisition end transmits the video data acquired by the camera to the data processing equipment of the example for processing through a network channel, and the working principle of the data processing equipment is as follows by taking scene one as an example:
step one, after the data processing equipment is started, loading load balancing software and security module mutual trust software in a memory into a processor;
step two, the processor carries out security verification on all the security modules through security module mutual trust software, and if all the security modules are trusted, the step three is executed; if any of the security modules is not authentic, the buzzer alarms and sets the data processing apparatus to an unavailable state.
Loading a safety module by the processor;
step four, the security module number 0 generates a secret key and synchronously sends the secret key to each other security module;
step five, loading all security modules into available states by the processor;
step six, after receiving the video data, the network interface sends the video data to the processor;
step seven, the processor determines the safety module with the lowest current load;
step eight, the processor sends data to an interface unit of the security module with the lowest load through a security module expansion interface connected with the security module with the lowest load;
step nine, the interface unit of the security module sends the received video data to the security memory chip;
step ten, the security memory chip encrypts the video data according to the stored secret key, and then sends the encrypted video data to the Nand flash memory chip;
and step eleven, storing the received encrypted video data by the Nand flash memory chip.
The data processing apparatus of the present example has the following advantages:
the first security module of the example has a storage function, so that encrypted data can be stored safely without falling to the ground, the defect that data ciphertext is transmitted outside is avoided, and user data is stored inside the security module without falling to the ground;
secondly, the disaster recovery operation cannot be realized by the existing single encryption machine, and when the disaster recovery operation is realized by the two encryption machines, the disaster recovery operation is required. The data processing device in the example comprises a plurality of security modules, disaster recovery of the secret key can be automatically realized among the plurality of security modules, and the data processing device can still continue to operate after a certain security module fails, so that additional hardware devices are not required to be added, and the cost of a user can be reduced;
third, the present example may dynamically adjust the number of security modules based on the computing power, and may increase computing power without having to insert a new security module when the user's current computing power demand exceeds the computing power of the current data processing apparatus. Compared with the scheme of adding an encryption machine when the current calculation force is insufficient, the scheme has lower cost and simpler operation.
Fourth, this example can select which security module to send the received data to for processing according to the load condition of the security module, so that resources can be more reasonably used.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (9)

1. A data processing apparatus, characterized in that: comprising the following steps: the system comprises a processor, more than two encryption devices and at least two expansion interfaces, wherein each encryption device is connected with one expansion interface in a hot plug manner;
the processor is configured to send a generation instruction for generating a key to a default encryption device, and send a first synchronization instruction to the default encryption device, where the first synchronization instruction is used to instruct to send the generated key to each encryption device except the default encryption device in synchronization;
the encryption device is arranged to receive a generation instruction from the processor when the encryption device is a default encryption device, generate a key and store the generated key; receiving a first synchronization instruction from a processor, and sending the generated key to each encryption device except the encryption device; encrypting the received data according to the generated secret key; when the device is an encryption device except a default encryption device, receiving and storing a key from the default encryption device; and encrypting the received data according to the obtained secret key.
2. The data processing apparatus of claim 1, wherein,
the processor is further configured to send the received data to the selected encryption device;
the encryption device is further configured to encrypt the data according to the key stored by the encryption device when the data sent by the processor is received, and store the encrypted data.
3. The data processing apparatus of claim 1, wherein,
the number of the encryption devices is smaller than or equal to the number of the expansion interfaces.
4. The data processing apparatus of claim 2, wherein:
each encryption device comprises a secure memory chip;
the secure memory chip is configured to store encrypted data, and includes: and storing the encrypted data in a self secure memory chip.
5. The data processing apparatus of claim 2, wherein:
the processor is further configured to send the received data to a selected encryption device, including:
and selecting the encryption device as the first target from all the encryption devices according to the load information of each encryption device, and sending the received data to the encryption device as the first target.
6. The data processing apparatus of claim 5, wherein:
the selecting an encryption device as a first target from all encryption devices according to the load information of each encryption device, and sending the received data to the encryption device as the first target, including:
and selecting the encryption device with the lowest load according to the load of each encryption device, and sending the received data to the encryption device with the lowest load.
7. The data processing apparatus of claim 1, wherein:
the processor is further configured to perform reliability verification on each encryption device when the data processing apparatus is powered on, and set the data processing apparatus to an unavailable state when the reliability verification of any encryption device fails.
8. The data processing apparatus of claim 1, wherein:
the processor is further configured to perform reliability verification on the newly inserted encryption device when it is detected that a new encryption device is inserted in the operation process of the data processing apparatus, and set the newly inserted encryption device to an unavailable state when the reliability verification on the newly inserted encryption device fails.
9. The data processing apparatus of claim 2, wherein:
the processor is further configured to send a second synchronization instruction to any encryption device, where the second synchronization instruction is used to instruct the stored data to be backed up to the encryption device serving as the second target, and the second synchronization instruction carries identification information of the encryption device serving as the second target;
the encryption device is further configured to send the data stored in the encryption device to the encryption device as the second target after receiving the second synchronization instruction.
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CN115314269A (en) * 2022-07-29 2022-11-08 北京国领科技有限公司 Method for realizing high-performance network encryption by serial task division

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