CN112421719B - Double-charging control circuit and double-charging control method - Google Patents
Double-charging control circuit and double-charging control method Download PDFInfo
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- CN112421719B CN112421719B CN202011247553.9A CN202011247553A CN112421719B CN 112421719 B CN112421719 B CN 112421719B CN 202011247553 A CN202011247553 A CN 202011247553A CN 112421719 B CN112421719 B CN 112421719B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/40—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries adapted for charging from various sources, e.g. AC, DC or multivoltage
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- General Physics & Mathematics (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
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Abstract
The application relates to the technical field of charging control, and provides a double-charging control circuit and a double-charging control method. The circuit comprises a power adapter charging circuit and a type-c adapter charging circuit; when the charging circuit of the power adapter or the charging circuit of the type-c adapter is independently accessed, the power is supplied to the mainboard system and the battery; when inserting power adapter charging circuit and type-c adapter charging circuit simultaneously, power adapter charging circuit supplies power to the mainboard system, and type-c adapter charging circuit charges to the battery. The embodiment of the application can satisfy the system power demand when the computer system runs the heavy load, can charge to the battery again, does not have because adapter output voltage is inconsistent to lead to the electric current to produce the circulation problem between two adapters, can effectively solve the computer battery because the adapter consumption is not enough and lead to the problem that can't charge.
Description
Technical Field
The present disclosure relates to the field of charging management technologies, and in particular, to a dual charging control circuit and a dual charging control method.
Background
With the continuous improvement of computer configuration, the power consumption of the mainboard system is also increasing. Because the power adapter of the computer has rated working wattage, when the load of the computer is not large, the power adapter can meet the normal work of system equipment, and partial electric quantity can charge the battery; however, when the CPU or GPU of the computer is overloaded and the power consumed by the system during operation reaches a certain amount of data, the battery management chip may terminate the power adapter to charge the battery, or even require the battery to assist the power adapter to supply power, so that the problem of computer application is solved, but the charging efficiency of the battery is extremely low, the power supply time of the battery is reduced when the battery is subsequently required to supply power, and the user's requirements cannot be met.
Therefore, it is desirable to provide a new dual charging control circuit to solve the above problems.
Disclosure of Invention
Based on this, the present application provides a dual charging control circuit and a dual charging control method to avoid the above-described problems.
The embodiment of the application provides a pair of control circuit that charges, pair of control circuit that charges includes:
the charging circuit of the power adapter is used for supplying power to a mainboard system and a battery when the power adapter connected with the charging circuit of the power adapter is independently connected, and supplying power to the mainboard system when the charging circuit of the type-c adapter is connected to the type-c adapter;
the type-c adapter charging circuit is used for supplying power to the mainboard system and the battery when the type-c adapter connected with the type-c adapter charging circuit is independently connected, and supplying power to the battery when the power adapter charging circuit is connected with the power adapter.
In one embodiment, the dual charging control circuit further comprises a first switch circuit, a second switch circuit, a third switch circuit;
the first switch circuit is connected with the type-c adapter charging circuit and a mainboard system, and the first switch circuit is used for controlling the type-c adapter charging circuit to supply power to the mainboard system;
the second switch circuit is connected with the mainboard system and the battery, and is used for isolating the output of the power adapter charging circuit and the type-c adapter charging circuit when the power adapter charging circuit and the type-c adapter charging circuit are simultaneously connected, and controlling the power adapter charging circuit or the type-c adapter charging circuit to simultaneously supply power to the mainboard system and the battery when the power adapter charging circuit or the type-c adapter charging circuit is separately connected;
the third switch circuit is connected with the type-c adapter charging circuit and the battery, and the third switch circuit is used for controlling the type-c adapter charging circuit to charge the battery when the power adapter charging circuit and the type-c adapter charging circuit are simultaneously connected.
In one embodiment, the dual charge control circuit further comprises a first nand gate, a second nand gate, a first nor gate;
the first NAND gate circuit is connected with the first switch circuit and used for controlling the connection and disconnection of the first switch circuit;
the first NOR gate circuit is connected with the second switch circuit and used for controlling the on and off of the second switch circuit;
and the second NAND gate circuit is connected with the third switch circuit and is used for controlling the on and off of the third switch circuit.
In one embodiment, the power adapter charging circuit comprises a first enable signal output port for outputting a first enable signal, a second enable signal output port for outputting a second enable signal;
the type-c adapter charging circuit comprises a third enable signal output port, and the third enable signal output port is used for outputting a third enable signal;
the first enable signal after logical negation and the third enable signal after logical negation are output to the first NAND gate circuit;
the second enable signal after logical negation and a third enable signal after logical negation are output to the second NAND gate circuit;
and the second enabling signal and the third enabling signal are output to the first exclusive-OR gate circuit.
In one embodiment, the first switch circuit, the second switch circuit, and the third switch circuit each comprise a KTS1677 chip.
In one embodiment, the first switch circuit, the second switch circuit, and the third switch circuit are active at a low level.
The embodiment of the application provides a dual-charging control method, which is applied to a dual-charging control circuit for charging a mainboard system and a battery, wherein the dual-charging control circuit comprises a power adapter charging circuit and a type-c adapter charging circuit, and the dual-charging control method comprises the following steps:
when the power adapter connected with the power adapter charging circuit is independently accessed, the power adapter charging circuit supplies power to the mainboard system and the battery;
when a type-c adapter connected with a type-c adapter charging circuit is independently accessed, the type-c adapter charging circuit supplies power to a mainboard system and a battery;
when the power adapter charging circuit and the type-c adapter charging circuit are connected simultaneously, the power adapter charging circuit supplies power to the mainboard system, and the type-c adapter charging circuit charges the battery.
In one embodiment, when a power adapter connected to a power adapter charging circuit is separately accessed, the power adapter charging circuit supplies power to a motherboard system and a battery, and the method comprises the following steps:
a second enabling signal output by the power adapter charging circuit is at a low level, and a third enabling signal of the type-c adapter charging circuit is at a high level;
the second enabling signal and the third enabling signal are output to the first exclusive OR gate circuit, the output of the first exclusive OR gate circuit is enabled to be at a low level, and the first exclusive OR gate circuit drives the second switch circuit to be conducted so as to supply power to the mainboard system and the battery at the same time;
the third enabling signal after the logical negation is output to the first NAND gate circuit and the second NAND gate circuit, so that the output of the first NAND gate circuit and the second NAND gate circuit is high level, the first switch circuit and the third switch circuit are driven to be disconnected, and the third enabling signal is used for disconnecting the connection between the type-c adapter charging circuit and the mainboard system and the battery;
the power adapter charging circuit supplies power to the mainboard system and the battery.
In one embodiment, when the type-c adapter connected with the type-c adapter charging circuit is separately accessed, the type-c adapter charging circuit supplies power to the mainboard system and the battery, and comprises the following steps:
the third enabling signal of the type-c adapter charging circuit is at a low level, the first enabling signal output by the power adapter charging circuit is at a low level, and the second enabling signal is at a high level;
the second enable signal after the logical negation and the third enable signal after the logical negation are output to the second NAND gate circuit, so that the output of the second NAND gate circuit is in a high level, the third switch circuit is controlled to be disconnected, and the connection between the type-c adapter charging circuit and the battery is disconnected;
the first enable signal after the logical negation and the third enable signal after the logical negation are output to the first NAND gate circuit, so that the first NAND gate circuit outputs a low level, and the first switch circuit is controlled to be conducted, so that the connection between the type-c adapter charging circuit and the mainboard system is realized;
the second enabling signal and the third enabling signal are output to the first NOR gate circuit to enable the first NOR gate circuit to output low level, and the second NOR gate circuit is controlled to be conducted to supply power to the mainboard system and the battery at the same time;
the type-c adapter charging circuit supplies power to the mainboard system and the battery through the first switch circuit.
In one embodiment, when the power adapter charging circuit and the type-c adapter charging circuit are simultaneously connected, the power adapter charging circuit supplies power to the mainboard system, and the type-c adapter charging circuit charges a battery, and the method includes the following steps:
the third enabling signal of the type-c adapter charging circuit is at a low level, the first enabling signal output by the power adapter charging circuit is at a high level, and the second enabling signal is at a low level;
the first enable signal after the logical negation and the third enable signal after the logical negation are output to the first NAND gate circuit, so that the first NAND gate circuit outputs a high level, the first switch circuit is controlled to be disconnected, the connection between the type-c adapter charging circuit and the mainboard system is disconnected, and the power adapter charging circuit supplies power to the mainboard system;
the second enabling signal and the third enabling signal are output to the first exclusive-nor circuit to enable the first exclusive-nor circuit to output high level, and the second switching circuit is controlled to be disconnected and used for disconnecting the mainboard system from the battery;
and the second enabling signal after the logical negation and the third enabling signal after the logical negation are output to the second NAND gate circuit, so that the output of the second NAND gate circuit is low level, and the third switching circuit is controlled to be conducted, so that the type-c adapter charging circuit can supply power to the battery through the third switching circuit.
According to the double-charging control circuit and the double-charging control method, through two power supply modes of the power adapter and the type-c adapter, when a computer system runs with heavy load, the power utilization requirement of the system can be met, the battery can be charged, the problem that current generates circulation between the two adapters due to inconsistent output voltages of the adapters does not exist, the output currents of the adapters are safe and reliable, and the problem that the computer battery cannot be charged due to insufficient power consumption of the adapters can be effectively solved.
Drawings
FIG. 1 is a block diagram of a dual charge control circuit in one embodiment;
FIG. 2 is a block diagram of a dual charging control circuit in another embodiment;
FIG. 3 is a block diagram showing a structure of a dual charging control circuit in another embodiment;
FIG. 4 is a block diagram showing a structure of a dual charging control circuit in still another embodiment;
FIG. 5 is a block diagram showing a structure of a dual charging control circuit in still another embodiment;
FIG. 6 is a block diagram showing a structure of a dual charging control circuit in another embodiment;
FIG. 7 is a block diagram of a dual charging control circuit in yet another embodiment;
FIG. 8 is a block diagram of a dual charging control circuit in yet another embodiment;
FIG. 9 is a circuit diagram of an embodiment of a power adapter charging circuit when connected alone;
FIG. 10 is a circuit diagram of an embodiment when a type-c adapter charging circuit is separately accessed;
FIG. 11 is a circuit diagram of a dual charge control circuit in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In order to solve the problems in the background art, the following methods are generally adopted, namely, the output power of the power adapter is increased, and the design of parallel power supply of the dual-power adapter is adopted. Although the method for increasing the output power of the power adapter can meet the requirement, the size of the power adapter is increased, and the portability of a computer is influenced; the method of adopting the design of the dual power adapter for parallel power supply requires that the voltages of the two power adapters must be completely consistent, otherwise, the damage of the power adapters can be caused.
The present application proposes a new charge control circuit in view of the above problems.
As shown in fig. 1, the dual charging control circuit includes:
a power adapter charging circuit 101 and a type-c adapter charging circuit 102;
the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are connected to the motherboard system 103 and the battery 104, respectively.
As shown in fig. 2, the power adapter charging circuit 101 is configured to supply power to the motherboard system 103 and the battery 104 when a power adapter connected to the power adapter charging circuit 101 is separately connected, and to supply power to the motherboard system 103 when the type-c adapter charging circuit 102 is connected to a type-c adapter.
The power adapter charging circuit 101 is used for supplying power to the motherboard system 103 when the type-c adapter charging circuit 102 is connected to the type-c adapter after the power adapter connected with the power adapter charging circuit 101 is connected to the power adapter alone.
As shown in fig. 3, the type-c adapter charging circuit 102 is configured to supply power to the motherboard system 103 and the battery 104 when a type-c adapter connected to the type-c adapter charging circuit 102 is separately connected, and to supply power to the battery 104 when the power adapter charging circuit 101 is connected to a power adapter.
Specifically, in practical applications, regardless of whether the type-c adapter charging circuit 102 or the power adapter charging circuit 101 is connected separately, although both are connected to the motherboard system 103 and the battery 104, power is supplied to the motherboard system 103 first, and the battery 104 is charged only when the load of the motherboard system 103 is light, that is, when there is a margin in the power output from the type-c adapter charging circuit 102 or the power adapter charging circuit 101 to the motherboard system 103.
Specifically, the type-c adapter charging circuit 102 is configured to, after a type-c adapter connected to the type-c adapter charging circuit 102 is separately connected, when the power adapter charging circuit 101 is connected to a power adapter again, the type-c adapter charging circuit 102 separately supplies power to the battery 104.
In one embodiment, as shown in fig. 4, the dual charging control circuit further includes a first switch circuit 201, a second switch circuit 202, and a third switch circuit 203.
The first switch circuit 201 is respectively connected to the type-c adapter charging circuit 102, the motherboard system 103, and the battery 104, and the first switch circuit 201 is configured to control the type-c adapter charging circuit 102 to supply power to the motherboard system 103 and the battery 104.
Specifically, when the first switch circuit 201 is turned on, the type-c adapter charging circuit 102 is turned on to connect with the motherboard system 103 and the battery 104, the type-c adapter charging circuit 102 supplies power to the motherboard system 103, and when there is a margin in the power output from the type-c adapter charging circuit 102 to the motherboard system 103, the battery 104 is charged, and it is emphasized that the on and off conditions of the first switch circuit 201 are controlled by the type-c adapter charging circuit 102 and the power adapter charging circuit 101. The second switch circuit 202 is connected to the motherboard system 103 and the battery 104, and the second switch circuit 202 is configured to isolate outputs of the power adapter charging circuit 101 and the type-c adapter charging circuit 102 when the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected, and control the power adapter charging circuit 101 or the type-c adapter charging circuit 102 to simultaneously supply power to the motherboard system 103 and the battery 104 when the power adapter charging circuit 101 or the type-c adapter charging circuit 102 is separately connected.
Specifically, the second switch circuit 202 is disposed between the motherboard system 103 and the battery 104, and if the power adapter charging circuit 101 supplies power to the motherboard system 103, the second switch circuit 202 is turned on, that is, the battery 104 is allowed to be charged when the remaining power supplied to the motherboard system 103 by the power adapter charging circuit 101 exceeds a set threshold. Similarly, if the type-c adapter charging circuit 102 supplies power to the motherboard system 103 through the first switch circuit 201, the second switch circuit 202 is turned on, which allows the battery 104 to be charged simultaneously when the remaining power of the type-c adapter charging circuit 102 to the motherboard system 103 exceeds a predetermined threshold.
When the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are connected simultaneously, in order to ensure system safety, the first switch circuit 201 needs to be disconnected first, and at this time, the main board system 103 only receives power supplied by the power adapter charging circuit 101. The first switch circuit 201 is turned off, the type-c adapter charging circuit 102 cannot supply power to the motherboard system 103, however, the type-c adapter charging circuit 102 supplies power to the battery 104, and the motherboard system 103 and the battery 104 are connected through the second switch circuit 202, so that the second switch circuit 202 must be turned off at this time to prevent the current between the motherboard system 103 and the battery 104 from being inconsistent and damaging the equipment, that is, the outputs of the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are isolated by turning off the second switch circuit 202.
It is emphasized that the on and off conditions of the second switch circuit 202 are controlled by the type-c adapter charging circuit 102 and the power adapter charging circuit 101.
The third switch circuit 203 is connected to the type-c adapter charging circuit 102 and the battery 104, and the third switch circuit 203 is configured to control the type-c adapter charging circuit 102 to charge the battery 104 when the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected.
Specifically, when the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are separately connected, and the third switch circuit 203 is both in an off state, the power adapter charging circuit 101 is directly connected to the motherboard system 103 when the power adapter charging circuit 101 is separately connected.
In one embodiment, as shown in fig. 5, the dual charge control circuit further includes a first nand gate 301, a second nand gate 303, and a first nor gate 302.
The first nand gate circuit 301 is connected to the first switch circuit 201, and is configured to control on and off of the first switch circuit 201, specifically, when the first nand gate circuit 301 outputs a low level, the first switch circuit 201 is on, and when the first nand gate circuit 301 outputs a high level, the first switch circuit 201 is off.
The first exclusive nor circuit 302 is connected to the second switch circuit 202, and is configured to control on and off of the second switch circuit 202, specifically, when the first exclusive nor circuit 302 outputs a low level, the second switch circuit 202 is turned on, and when the first exclusive nor circuit 302 outputs a high level, the second switch circuit 202 is turned off.
The second nand gate circuit 303 is connected to the third switch circuit 203, and is configured to control on and off of the third switch circuit 203, specifically, when the second nand gate circuit 303 outputs a low level, the third switch circuit 203 is turned on, and when the second nand gate circuit 303 outputs a high level, the third switch circuit 203 is turned off.
Specifically, the power adapter charging circuit 101 further includes a first enable signal output port and a second enable signal output port, the type-c adapter charging circuit 102 includes a third enable signal output port, the first enable signal output port and the second enable signal output port respectively output a first enable signal and a second enable signal, and the third enable signal output port outputs a third enable signal.
The first enable signal after logical negation and the third enable signal after logical negation are output to the first nand gate circuit 301;
the second enable signal after logical negation and the third enable signal after logical negation are output to the second nand gate circuit 302;
the second and third enable signals are output to the first and-or gate 302.
In one embodiment, as shown in fig. 6, the first nand gate circuit 301 inputs the first enable signal and the third enable signal after being logically negated, and is configured to output a low level or a high level to drive the first switch circuit 201 to be turned on or off under the control of the first enable signal and the third enable signal.
Specifically, when the power adapter charging circuit 101 is separately connected, the second enable signal output by the power adapter charging circuit 101 is at a low level, and the third enable signal of the type-c adapter charging circuit 102 is at a high level; the third enable signal after the logical negation is output to the first nand gate circuit 301, and at this time, the output of the first nand gate circuit 301 is at a high level regardless of whether the first enable signal is at a high level or a low level, and the first switch circuit 201 and the third switch circuit 203 are driven to be turned off.
When the type-c adapter charging circuit 102 is connected separately, the third enable signal of the type-c adapter charging circuit 102 is at a low level, the first enable signal output by the power adapter charging circuit 101 is at a low level, and the second enable signal is at a high level; the first enable signal and the third enable signal after the logical negation are output to the first nand gate circuit 301, so that the first nand gate circuit outputs a low level to control the first switch circuit 201 to be turned on, and the first nand gate circuit and the first switch circuit are used for realizing connection between the type-c adapter charging circuit 102 and the motherboard system 103.
When the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected, a third enable signal of the type-c adapter charging circuit 102 is at a low level, a first enable signal output by the power adapter charging circuit 101 is at a high level, and a second enable signal is at a low level; the first enable signal and the third enable signal after the logical negation are output to the first nand gate circuit 301, so that the first nand gate circuit outputs a high level, the first switch circuit 201 is controlled to be disconnected, the connection between the type-c adapter charging circuit 102 and the motherboard system 103 is disconnected, and the power adapter charging circuit 101 supplies power to the motherboard system 103.
In one embodiment, as shown in fig. 7, the second nand gate circuit 302 inputs the second enable signal after being logically negated and a third enable signal after being logically negated, and is configured to output a low level or a high level under the control of the second enable signal and the third enable signal, so as to drive the third switch circuit 203 to be turned on or turned off.
Specifically, when the power adapter charging circuit 101 is separately connected, the second enable signal output by the power adapter charging circuit 101 is at a low level, and the third enable signal of the type-c adapter charging circuit 102 is at a high level; the third enable signal after the logical negation is output to the second nand gate circuit 303, so that the output of the second nand gate circuit is at a high level, and the third switch circuit 203 is driven to be turned off, thereby disconnecting the type-c adapter charging circuit 102 from the battery 104.
When the type-c adapter charging circuit 102 is connected separately, the third enable signal of the type-c adapter charging circuit 102 is at a low level, the first enable signal output by the power adapter charging circuit 101 is at a low level, and the second enable signal is at a high level; the second enable signal after the logical negation and the third enable signal after the logical negation are output to the second nand gate circuit 303, so that the output of the second nand gate circuit 303 becomes a high level, the third switch circuit 203 is controlled to be turned off, and the connection between the type-c adapter charging circuit 102 and the battery 104 is disconnected.
When the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected, a third enable signal of the type-c adapter charging circuit 102 is at a low level, a first enable signal output by the power adapter charging circuit 101 is at a high level, and a second enable signal is at a low level; the second enable signal after the logical negation and the third enable signal after the logical negation are output to the second nand gate circuit 303, so that the output of the second nand gate circuit is at a low level, and the third switch circuit 203 is controlled to be turned on, so that the type-c adapter charging circuit 102 supplies power to the battery 104 through the third switch circuit 203.
In one embodiment, as shown in fig. 8, the first exclusive-nor circuit 302 inputs a second enable signal and a third enable signal, and is configured to output a low level or a high level to drive the second switch circuit 202 to be turned on or off under the control of the second enable signal and the third enable signal.
Specifically, when the power adapter charging circuit 101 is separately connected, the second enable signal output by the power adapter charging circuit 101 is at a low level, and the third enable signal of the type-c adapter charging circuit 102 is at a high level; the second enable signal and the third enable signal are output to the first exclusive nor circuit 302, so that the output of the first exclusive nor circuit 302 is at a low level, and the first exclusive nor circuit 302 drives the second switch circuit 202 to be turned on, so as to enable the power adapter charging circuit 101 to simultaneously supply power to the motherboard system 103 and the battery 104.
When the type-c adapter charging circuit 102 is connected separately, the third enable signal of the type-c adapter charging circuit 102 is at a low level, the first enable signal output by the power adapter charging circuit 101 is at a low level, and the second enable signal is at a high level; the second enable signal and the third enable signal are output to the first exclusive nor circuit 302, so that the first exclusive nor circuit outputs a low level, and controls the second switch circuit 202 to be turned on, so as to enable the type-c adapter charging circuit 102 to simultaneously supply power to the motherboard system 103 and the battery 104.
When the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected, a third enable signal of the type-c adapter charging circuit 102 is at a low level, a first enable signal output by the power adapter charging circuit 101 is at a high level, and a second enable signal is at a low level; the second enable signal and the third enable signal are output to the first exclusive nor circuit 302, so that the first exclusive nor circuit 302 outputs a high level, and controls the second switch circuit 202 to be switched off, so as to disconnect the electrical connection between the motherboard system 103 and the battery 104, thereby supplying power to the motherboard system 103 by the power adapter charging circuit 101 and supplying power to the battery 104 by the type-c adapter charging circuit 102.
An embodiment of the present application provides a dual charging control method, where a dual charging control circuit described in any of the above embodiments of the present application is applied to charge a motherboard system and a battery, where the dual charging control circuit includes a power adapter charging circuit and a type-c adapter charging circuit, and the dual charging control method includes:
when a power adapter connected with the power adapter charging circuit 101 is accessed separately, the power adapter charging circuit 101 supplies power to the mainboard system 103 and the battery 104;
when a type-c adapter connected to the type-c adapter charging circuit 102 is separately accessed, the type-c adapter charging circuit 102 supplies power to the motherboard system 103 and the battery 104;
when the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected, the power adapter charging circuit 101 supplies power to the motherboard system 103, and the type-c adapter charging circuit 102 charges the battery 104.
In one embodiment, when the power adapter connected to the power adapter charging circuit 101 is separately accessed, the power adapter charging circuit 101 supplies power to the motherboard system 103 and the battery 104, and includes:
the second enable signal output by the power adapter charging circuit 101 is at a low level, and the third enable signal of the type-c adapter charging circuit 102 is at a high level;
the second enable signal and the third enable signal are output to the first exclusive nor circuit 302, so that the output of the first exclusive nor circuit 302 is at a low level, and the first exclusive nor circuit 302 drives the second switch circuit 202 to be turned on, so as to supply power to the motherboard system 103 and the battery 104 at the same time;
the first nand gate circuit 301 and the second nand gate circuit 303 output high level, drive the first switch circuit 201 and the third switch circuit 203 to be disconnected, and are used for disconnecting the type-c adapter charging circuit 102 from the motherboard system 103 and the battery 104;
the power adapter charging circuit 101 supplies power to the motherboard system 103 and the battery 104.
In one embodiment, when the type-c adapter connected to the type-c adapter charging circuit 102 is separately accessed, the type-c adapter charging circuit 102 supplies power to the motherboard system 103 and the battery 104, and includes:
the third enable signal of the type-c adapter charging circuit 102 is at a low level, the first enable signal output by the power adapter charging circuit 101 is at a low level, and the second enable signal is at a high level;
the second enable signal after the logical negation and the third enable signal after the logical negation are output to the second nand gate circuit 303, so that the output of the second nand gate circuit 303 is at a high level, the third switch circuit 203 is controlled to be disconnected, and the connection between the type-c adapter charging circuit 102 and the battery 104 is disconnected;
the first enable signal after logical negation and the third enable signal after logical negation are output to the first nand gate circuit 301, so that the first nand gate circuit outputs a low level to control the first switch circuit 201 to be conducted, and the first nand gate circuit and the first switch circuit are used for realizing connection between the type-c adapter charging circuit 102 and the mainboard system 103;
the second enable signal and the third enable signal are output to the first exclusive-nor circuit 302, so that the first exclusive-nor circuit 302 outputs a low level to control the second switch circuit 202 to be turned on, and the second enable signal and the third enable signal are used for supplying power to the mainboard system 103 and the battery 104 at the same time;
the type-c adapter charging circuit 102 supplies power to the motherboard system 103 and the battery 104 through the first switch circuit 201.
In one embodiment, when the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are simultaneously connected, the power adapter charging circuit 101 supplies power to the motherboard system 103, and the type-c adapter charging circuit 102 charges the battery 104, including:
the third enable signal of the type-c adapter charging circuit 102 is at a low level, the first enable signal output by the power adapter charging circuit 101 is at a high level, and the second enable signal is at a low level;
the first enable signal after the logical negation and the third enable signal after the logical negation are output to the first nand gate circuit 301, so that the first nand gate circuit outputs a high level, the first switch circuit 201 is controlled to be disconnected, the connection between the type-c adapter charging circuit 102 and the motherboard system 103 is disconnected, and the power adapter charging circuit 101 supplies power to the motherboard system 103;
the second enable signal and the third enable signal are output to the first exclusive nor circuit 302, so that the first exclusive nor circuit 302 outputs a high level to control the second switch circuit 202 to be switched off, and the second switch circuit is used for disconnecting the electrical connection between the mainboard system 103 and the battery 104;
the second enable signal after the logical negation and the third enable signal after the logical negation are output to the second nand gate circuit 303, so that the output of the second nand gate circuit is at a low level, and the third switch circuit 203 is controlled to be turned on, so that the type-c adapter charging circuit 102 supplies power to the battery 104 through the third switch circuit 203.
It should be emphasized that the first switch circuit, the second switch circuit, and the third switch circuit described in the above embodiments of the present application each include a KTS1677 chip.
In a specific embodiment, fig. 9 is a circuit diagram of the power adaptor circuit 101 when it is connected separately, as shown in fig. 9, the power adaptor circuit 101 is connected through the + VADAP port, the power adaptor circuit is divided by the resistors R6 and R7, the MOS transistor Q8, the MOS transistor Q9, and the MOS transistor Q10 are turned on, the output of EN1 is at a low level, when the voltage of + VADAP rises to be higher than 11V, the MOS transistor Q6 and the MOS transistor Q7 are turned on, the voltage of + VADAP enters V _ adapter _ in, when the voltage of V _ adapter _ in rises to 17.8V, the voltage of the ACDET reference point reaches 2.4V, the battery management chip U1 will turn on the MOS transistor Q1 and the MOS transistor Q2, the input voltage of the main board system 103 is equal to the voltage input at the V _ adapter _ in port, and the main board system 103 will receive the voltage output by the power adaptor charging circuit 101 as the input voltage. Since the type-c adapter charging circuit 102 is not accessed at this time, PD _ SINK # is "1". When EN1 and PD _ SINK # are input to Y1, EN3 is pulled low to "0", U2 is turned on, and U3 and U4 are turned off (indicated by dotted lines in the figure). If the power output by the power adapter circuit 101 has a margin, the power adapter charging circuit 101 not only supplies power to the motherboard system 103, but also charges the battery 104 through a BUCK circuit composed of the MOS transistor Q3, the MOS transistor Q4, and the inductor L1. At this time, the MOS transistor Q5 is in an off state. When the power consumption of the motherboard system 103 increases to a set percentage of the rated power consumption of the power adapter circuit 101, the battery management chip U1 reduces the charging current for the battery 104 to meet the power consumption requirement of the motherboard system 103, if the power consumption of the motherboard system 103 continues to increase, the charging current for the battery 104 also continues to decrease until the charging current is reduced to 0, and the battery management chip U1 supplies all the power consumption output by the power adapter charging circuit 101 to the motherboard system 103, thereby ensuring the operating performance of the motherboard system 103.
In a specific embodiment, fig. 10 is a circuit diagram of a case where the type-c adapter charging circuit 102 is connected alone, as shown in fig. 10, when the type-c adapter charging circuit 102 is connected, PD _ SINK # is "0", since the power adapter charging circuit 101 is not connected, EN1 is "1", EN2 is "0", so that the output of Y2 is high, and U4 is disconnected (indicated by a dotted line in the figure); the output of Y3 is low, U3 will be turned on; the output voltage of the type-c adapter charging circuit 102 is connected to the V _ adapter _ in port through U3. When the voltage of the V _ adapter _ in port rises to 17.8V, the voltage of the ACDET reference point reaches 2.4V, the battery management chip U1 will turn on the MOS transistor Q1 and the MOS transistor Q2, and at this time, the input voltage of the motherboard system 103 is equal to the output voltage of the type-c adapter charging circuit 102. Meanwhile, since the input terminal PD _ SINK # is "0" and EN1 is "1", the output EN3 of Y1 is "0", and U2 is turned on. If the power output by the type-c adapter charging circuit 102 has a margin, the type-c adapter charging circuit 102 not only supplies power to the motherboard system 103, but also charges the battery 104 through a BUCK line composed of the MOS transistor Q3, the MOS transistor Q4 and the inductor L1. At this time, the MOS transistor Q5 is in an off state. When the power consumption of the motherboard system 103 increases to the set percentage of the rated power consumption of the type-c adapter charging circuit 102, the battery management chip U1 reduces the charging current for the battery 104 to meet the power consumption requirement of the motherboard system 103, if the power consumption of the motherboard system 103 continues to increase, the charging current for the battery 104 also continues to decrease until the charging current is reduced to 0, and the battery management chip U1 supplies all the power consumption output by the type-c adapter charging circuit 102 to the motherboard system 103, thereby ensuring the operation performance of the motherboard system 103.
In a specific embodiment, fig. 11 is a circuit diagram of the power adapter charging circuit 101 and the type-c adapter charging circuit 102 being connected simultaneously, and as shown in fig. 11, when the power adapter charging circuit 101 and the type-c adapter charging circuit 102 are connected simultaneously, the power adapter circuit 101 is connected through the + VADAP port, and after voltage division by the resistors R6 and R7, the MOS transistor Q8, the MOS transistor Q9, and the MOS transistor Q10 are turned on, at this time, EN1 is "0" and EN2 is "1", and since the type-c adapter charging circuit 102 is connected simultaneously, PD _ SINK # is "0", Y1 output is high, Y2 output is low, Y3 output is high, U2 is off (indicated by a dotted line in the figure), U3 is off (indicated by a dotted line in the figure), and U4 is on. When the voltage of + VADAP reaches 11V or more, the MOS transistor Q6 and the MOS transistor Q7 are turned on, and the voltage of + VADAP enters V _ adapter _ in. When the voltage of the V _ adapter _ in rises to 17.8V, the voltage of the ACDET reference point reaches 2.4V, the battery management chip U1 will turn on the MOS transistor Q1 and the MOS transistor Q2, the input voltage of the motherboard system 103 is equal to the voltage of the V _ adapter _ in terminal, and the motherboard system 103 is connected to the power adapter charging circuit 101 as an input. Because U2 is off, the power adapter circuit 101 will no longer charge the battery 104 at this time;
since U4 is conducted, the type-c adapter charging circuit 102 is connected to the power access port VBUS _ IN through U4, and then charges the battery 104 through the BUCK line composed of the MOS tube Q3, the MOS tube Q4 and the inductor L1, meanwhile, because U3 is disconnected, the type-c adapter charging circuit 102 can not be connected to the V _ adapter _ IN port through U3, because U2 is disconnected, the channel between the power adapter charging circuit 101 and the type-c adapter charging circuit 102 is cut off, therefore, even if the output voltages of the type-c adapter charging circuit 102 and the power adapter charging circuit 101 are inconsistent, no influence is caused between the type-c adapter charging circuit 102 and the power adapter charging circuit 101,
in order to better implement the corresponding functions of the above embodiments, while providing a hardware circuit, the Embedded chip of the computer needs to be supported by related software, and software setting needs to be performed. In any case, as long as the Embedded chip detects that the power adapter charging circuit 101 is connected to the computer, the Type-C adapter charging circuit 102 meeting the condition for charging the battery is also connected to the Type C port, the computer defaults to a dual-adapter power supply state, and the Embedded chip performs a series of adjustments on the register of the battery Management chip through SMBUS (System Management Bus, SMBUS for short). Firstly, the battery charge stop point needs to be increased, because the battery management chip obtains the magnitude of the adapter inflow current I1 by detecting the voltage difference between two ends of the resistor R4, when the computer is connected with only one adapter, I1= I2+ I3, as the power consumption of the motherboard system 103 increases, i.e. the current of I2 increases, I1 also increases, when I1 reaches a certain value, the battery management chip controls the charge current I3 to decrease, thereby ensuring that I1 is unchanged, and the value of I1 is called as the battery charge stop point. When the computer is connected to two adapters, the charging current of the battery is actually provided by the type-c adapter charging circuit 102, i.e. the current is I4, I1 is equal to I2. If the battery management chip also uses the original setting, when it detects that I1 reaches the battery stop charging point, the battery management chip will also reduce the charging current, and the type-c adapter charging circuit 102 is not used. Therefore, after the two adapters are connected simultaneously, the Embedded chip needs to heighten the battery charging stop point through the SMBUS, and a designer can set a specific value of the battery charging stop point according to the rated power consumption of the inserted type-c adapter charging circuit 102. In addition, because of the adjustment of the battery stop charge point value, in order to ensure that the power adapter charging circuit 101 is not overloaded, the power consumption of the motherboard system 103 needs to be limited by detecting the voltage of the IADAP PIN of the battery management chip through the Embedded chip, and when the Embedded chip reads that the voltage of the IADAP PIN reaches a certain value, the operating frequency of the CPU and the GPU needs to be reduced, so that the power consumption of the motherboard system 103 is limited.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
Claims (4)
1. A dual charging control circuit, comprising a power adapter charging circuit and a type-c adapter charging circuit;
the power adapter charging circuit is used for supplying power to a mainboard system and a battery when a power adapter connected with the power adapter charging circuit is connected in a single mode, and supplying power to the mainboard system when the type-c adapter charging circuit is connected in a type-c adapter in a single mode;
the type-c adapter charging circuit is used for supplying power to a mainboard system and a battery when a type-c adapter connected with the type-c adapter charging circuit is connected in a separate mode, and supplying power to the battery when the power adapter charging circuit is connected in a separate mode;
the double-charging control circuit further comprises a first switch circuit, a second switch circuit and a third switch circuit;
the first switch circuit is respectively connected with the type-c adapter charging circuit, the mainboard system and the battery, and is used for controlling the type-c adapter charging circuit to supply power to the mainboard system and the battery;
the second switch circuit is connected with the mainboard system and the battery, and is used for isolating the output of the power adapter charging circuit and the output of the type-c adapter charging circuit when the power adapter charging circuit and the type-c adapter charging circuit are simultaneously connected, and controlling the power adapter charging circuit or the type-c adapter charging circuit to simultaneously supply power to the mainboard system and the battery when the power adapter charging circuit or the type-c adapter charging circuit is separately connected;
the third switch circuit is connected with the type-c adapter charging circuit and the battery, and is used for controlling the type-c adapter charging circuit to charge the battery when the power adapter charging circuit and the type-c adapter charging circuit are simultaneously connected;
the double-charging control circuit further comprises a first NAND gate circuit, a second NAND gate circuit and a first NOR gate circuit;
the first NAND gate circuit is connected with the first switch circuit and used for controlling the conduction and the disconnection of the first switch circuit;
the first exclusive-nor circuit is connected with the second switch circuit and is used for controlling the on and off of the second switch circuit;
the second NAND gate circuit is connected with the third switch circuit and used for controlling the connection and disconnection of the third switch circuit;
the power adapter charging circuit comprises a first enable signal output port and a second enable signal output port, wherein the first enable signal output port is used for outputting a first enable signal, and the second enable signal is used for outputting a second enable signal;
the type-c adapter charging circuit comprises a third enable signal output port, and the third enable signal output port is used for outputting a third enable signal;
the first enable signal after logical negation and the third enable signal after logical negation are output to the first NAND gate circuit;
the second enable signal after logical negation and a third enable signal after logical negation are output to the second NAND gate circuit;
and the second enabling signal and the third enabling signal are output to the first exclusive-OR gate circuit.
2. The dual charge control circuit of claim 1, wherein the first, second, and third switch circuits each comprise a KTS1677 chip.
3. The dual charge control circuit of claim 1, wherein the first, second, and third switching circuits are active at a low level.
4. A dual charging control method, wherein a dual charging control circuit is used to charge a motherboard system and a battery, the dual charging control circuit comprises a power adapter charging circuit and a type-c adapter charging circuit, the dual charging control method comprises:
when the power adapter connected with the power adapter charging circuit is independently accessed, the power adapter charging circuit supplies power to the mainboard system and the battery;
when a type-c adapter connected with a type-c adapter charging circuit is independently accessed, the type-c adapter charging circuit supplies power to a mainboard system and a battery;
when the power adapter charging circuit and the type-c adapter charging circuit are connected simultaneously, the power adapter charging circuit supplies power to the mainboard system, and the type-c adapter charging circuit charges a battery;
the second enabling signal output by the power adapter charging circuit is at a low level, and the third enabling signal of the type-c adapter charging circuit is at a high level;
the second enabling signal and the third enabling signal are output to a first exclusive OR gate circuit, the output of the first exclusive OR gate circuit is at a low level, and the first exclusive OR gate circuit drives a second switch circuit to be conducted so as to supply power to a mainboard system and a battery at the same time;
the third enabling signal after the logical negation is output to the first NAND gate circuit and the second NAND gate circuit, so that the output of the first NAND gate circuit and the second NAND gate circuit is high level, the first switch circuit and the third switch circuit are driven to be disconnected, and the third enabling signal is used for disconnecting the connection between the type-c adapter charging circuit and the mainboard system and the battery;
the power adapter charging circuit supplies power to the mainboard system and the battery;
the third enabling signal of the type-c adapter charging circuit is at a low level, the first enabling signal output by the power adapter charging circuit is at a low level, and the second enabling signal is at a high level;
the second enable signal after the logical negation and the third enable signal after the logical negation are output to the second NAND gate circuit, so that the output of the second NAND gate circuit is in a high level, the third switch circuit is controlled to be disconnected, and the connection between the type-c adapter charging circuit and the battery is disconnected;
the first enable signal after the logical negation and the third enable signal after the logical negation are output to the first NAND gate circuit, so that the first NAND gate circuit outputs a low level, and the first switch circuit is controlled to be conducted, so that the connection between the type-c adapter charging circuit and the mainboard system is realized;
the second enabling signal and the third enabling signal are output to the first NOR gate circuit to enable the first NOR gate circuit to output low level, and the second NOR gate circuit is controlled to be conducted to supply power to the mainboard system and the battery at the same time;
the type-c adapter charging circuit supplies power to the mainboard system and the battery through a first switch circuit;
the third enabling signal of the type-c adapter charging circuit is at a low level, the first enabling signal output by the power adapter charging circuit is at a high level, and the second enabling signal is at a low level;
the first enabling signal after logical negation and the third enabling signal after logical negation are output to the first NAND gate circuit, so that the first NAND gate circuit outputs a high level, and controls the first switch circuit to be disconnected, so that the connection between the type-c adapter charging circuit and the mainboard system is disconnected;
the second enabling signal and the third enabling signal are output to the first exclusive-nor circuit to enable the first exclusive-nor circuit to output a high level, the second switching circuit is controlled to be disconnected and used for disconnecting the mainboard system from the battery, and the power adapter charging circuit supplies power to the mainboard system;
and the second enabling signal after the logical negation and the third enabling signal after the logical negation are output to the second NAND gate circuit, so that the output of the second NAND gate circuit is low level, and the third switching circuit is controlled to be conducted, so that the type-c adapter charging circuit can supply power to the battery through the third switching circuit.
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