CN112231101B - Memory allocation method and device and readable storage medium - Google Patents
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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Abstract
The embodiment of the invention provides a memory allocation method, a memory allocation device and a readable storage medium, wherein the method comprises the following steps: acquiring the size of an application memory, and performing memory allocation based on a modified DPDK idle linked list according to the size of the application memory; the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and, the interval of the memory intervals of each idle linked list is the same. By modifying the number of the DPDK idle linked lists, the interval range of the DPDK idle memory linked list is reduced, and meanwhile, the lock conflict probability when multiple CPUs apply for memory simultaneously is greatly reduced, so that the memory allocation speed is better improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a memory allocation method, apparatus, and readable storage medium.
Background
The memory management used by the firewall system is a heap memory management mechanism in a DPDK (Data Plane Development Kit ) open source kit, and the memory management mechanism has good stability and memory allocation efficiency when the memory application is not frequent, the allocated memory returns in time and the memory size is uncertain. The memory slicing algorithm uses a large page memory mechanism, and fundamentally solves the problem of unstable performance caused by TLB miss (TLB: translation Lookaside Buffer, translation lookaside buffer). The algorithm can automatically merge adjacent memory fragments, reduce the generation of memory fragments, improve the use efficiency of the memory, is a stable and reliable memory allocation algorithm, but the memory allocation size of a firewall system is random, and the message processing delay is required to be in a microsecond level, so the requirement on the speed of memory allocation is higher. When the system runs for a period of time, fragments of the original continuous memory can appear, the length of the idle linked list is increased, so that the time for searching the memory with proper size is prolonged when the memory is allocated, and under the limit condition, the whole idle linked list can be traversed, and even the condition that the proper memory size cannot be found can be avoided. Meanwhile, there is a case of applying for memory in parallel by multiple cores, and when one core cannot be successfully allocated for a long time, other CPUs (Central Processing Unit, central processing units) are all in a waiting state. When the service pressure of the firewall system is increased, the memory allocation rate is required to be high, and when the memory cannot be applied quickly, the service flow is blocked, and the performance is seriously reduced.
Another common memory allocation algorithm is the partner algorithm, which differs most from the heap memory management algorithm of DPDK in that the size of the free memory blocks in the free linked list is all the same. Partner algorithms trade off memory usage efficiency for memory allocation rate. The method uses the idea of binary optimization, cuts and distributes the memory by taking the power of 2 as a unit, and the sizes of memory blocks on all idle linked lists are consistent. Only the partner memory blocks can be merged when merging, and three conditions that two memory blocks are partners are: the addresses are consecutive and split from the same parent block with the same size. The algorithm has the greatest advantages of avoiding memory fragmentation, simultaneously matching the memory fragmentation to a needed idle memory block, and has the greatest disadvantages of memory waste and incapability of distributing idle memory. For example, allocation of a 33 byte memory requires allocation over a 64 fixed size free chain.
Disclosure of Invention
Aiming at the technical problems existing in the prior art, the embodiment of the invention provides a memory allocation method, a memory allocation device and a readable storage medium.
In a first aspect, an embodiment of the present invention provides a memory allocation method, including:
acquiring the size of an application memory, and performing memory allocation based on a modified DPDK idle linked list according to the size of the application memory;
the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and, the interval of the memory intervals of each idle linked list is the same.
Optionally, the preset index includes a mixed traffic throughput rate and a newly-built connection number; the number of the modified DPDK idle linked lists is 150.
Optionally, the intervals between the memory intervals of the idle linked lists are the same, including:
the memory intervals of the idle linked lists are spaced by the size of the first preset byte.
Optionally, when the memory interval range of the idle linked list exceeds the size of the second preset byte, the memory intervals of the idle linked list are set at intervals in a preset mode.
Optionally, the first preset byte is 64 bytes; the second preset byte is 8192 bytes; the preset manner is to increase in a manner of power of 2.
Optionally, the memory allocation based on the modified DPDK idle linked list according to the size of the application memory includes:
according to the size of the application memory, searching a memory block corresponding to the size of the application memory in a previous idle linked list of an idle linked list corresponding to the size of the application memory; and the interval range of the upper idle linked list is larger than the size of the application memory.
In a second aspect, an embodiment of the present invention provides a memory allocation apparatus, including:
the memory allocation module is used for acquiring the size of the application memory, and performing memory allocation based on the modified DPDK idle linked list according to the size of the application memory;
the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and, the interval of the memory intervals of each idle linked list is the same.
Optionally, the preset index includes a mixed traffic throughput rate and a newly-built connection number, and the number of the modified DPDK idle linked list is 150.
In a third aspect, an embodiment of the present invention provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to the first aspect when the program is executed.
In a fourth aspect, embodiments of the present invention provide a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method according to the first aspect.
According to the memory allocation method, the device and the readable storage medium, the DPDK idle linked list is modified, the number of the DPDK idle linked list is increased, memory allocation is performed based on the modified DPDK idle linked list according to the size of the application memory, the interval range of the DPDK idle memory linked list is reduced by modifying the number of the DPDK idle linked list, and meanwhile the lock conflict probability when multiple CPUs apply for memory simultaneously is greatly reduced, so that the memory allocation speed is better improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a memory allocation method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a memory allocation device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The interval between the idle memory SIZE in the DPDK17.05.2 idle linked list is the power of 2, the interval number is 13, and the memory SIZE of the minimum idle linked list is 0B-256B, so that the memory blocks from 1GB to MAX SIZE are stored in the last interval. When the memory with fixed size needs to be allocated, a first memory block with the size meeting the allocation requirement is found from the idle linked list meeting the allocation requirement. After the needed memory size is cut out from the idle memory blocks, the rest memory is inserted into an idle linked list meeting the requirement according to the size. The size of each memory block in each idle linked list is not fixed, but the size of each memory block needs to meet the range interval of the corresponding idle linked list. The range of intervals of the idle linked list is shown in table 1.
The defects existing in the prior art when memory allocation is performed based on the DPDK idle linked list are mainly shown in the following aspects:
first, the number of memory free queues is small. The CPUs used by firewall systems are multi-core, even many-core architectures. The fewer the memory free queues, the greater the probability of lock conflicts between CPUs, resulting in insufficient CPU performance.
Second, the memory idle queue single interval spans are large. A single free queue may be particularly long, with a single traversal time. Such as: if the interval of the idle queue is 0-64B, the size of the idle block mounted on the queue is only 63, and memory blocks with other sizes can be mounted on other idle queues. If the interval of the idle queue is 0-256B, the probability that the idle memory block falls into the interval is larger, and the length of the idle queue is longer after the system runs for a period of time.
In this regard, an embodiment of the present invention provides a memory allocation method, and fig. 1 is a schematic flow chart of the memory allocation method provided in the embodiment of the present invention, as shown in fig. 1, where the method includes:
s101: acquiring the size of an application memory, and performing memory allocation based on a modified DPDK idle linked list according to the size of the application memory;
the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and, the interval of the memory intervals of each idle linked list is the same.
Specifically, as shown in table 1, the number of idle linked lists DPDK17.05.2 is 13, and in a service system applying a DPDK heap memory management algorithm, the number of idle linked lists of DPDK is increased until the comprehensive performance of the system under a preset index is the best, and further, a modified idle linked list of DPDK is obtained. And when memory allocation is carried out, acquiring the size of an application memory, and carrying out memory allocation based on the modified DPDK idle linked list according to the size of the application memory.
According to the method provided by the embodiment of the invention, the number of DPDK idle linked lists is increased, so that the interval range of the idle memory linked list is reduced, and the lock conflict probability when multiple CPUs apply for the memory simultaneously is greatly reduced; only modifying individual parameters of the DPDK idle linked list can achieve the purpose of improving the memory allocation speed; the modified DPDK idle linked list can be applied to firewall products to improve the performance of the firewall products.
Based on the above embodiment, the preset indicators include a mixed traffic throughput rate and a newly-built connection number; the number of the modified DPDK idle linked lists is 150.
Specifically, in a service system applying a DPDK heap memory management algorithm, the number of DPDK idle linked lists is increased, and based on two indexes of traffic throughput rate and newly-built connection number, when the number of idle linked lists is 150, the comprehensive performance is best through comprehensive evaluation, so that the number of DPDK idle linked lists is modified from original 13 to 150.
According to the method provided by the embodiment of the invention, based on two indexes of traffic throughput rate and newly-built connection number, the number of DPDK idle linked lists is increased to 150, the interval range of the idle memory linked lists is reduced, and meanwhile, the lock conflict probability when multiple CPUs apply for memory simultaneously is greatly reduced.
Based on any one of the foregoing embodiments, the memory interval of each idle linked list is the same, including:
the memory intervals of the idle linked lists are spaced by the size of the first preset byte.
In particular, since the use of the small block memory is frequent, the overlong effect of the individual linked list on the traversal efficiency is easy to occur. Therefore, special design is carried out among linked list sizes of the small block memory, and the original power increasing mode of 2 is changed into fixed size increase of the first preset byte.
The method provided by the embodiment of the invention reduces the interval range of the DPDK idle memory linked list, and can avoid the influence of overlong individual linked list on the traversing efficiency, thereby further improving the memory allocation efficiency.
Based on any of the above embodiments, when the memory interval range of the idle linked list exceeds the size of the second preset byte, the memory intervals of the idle linked list are set at intervals in a preset manner.
Specifically, since the small block memory is frequently used, when the memory interval range of the idle linked list exceeds the size of the second preset byte, the intervals of the memory intervals of the idle linked list are set in a preset mode.
The method provided by the embodiment of the invention reduces the interval range of the idle memory linked list, and simultaneously greatly reduces the lock conflict probability when multiple CPUs apply for memories at the same time.
Based on any of the above embodiments, the first preset byte is 64byte; the second preset byte is 8192 bytes; the preset manner is to increase in a manner of power of 2.
In particular, since the use of the small block memory is frequent, the overlong effect of the individual linked list on the traversal efficiency is easy to occur. Therefore, the special design is carried out among the linked list sizes of the small block memory, the original power increasing mode of 2 is changed into fixed 64byte size increasing mode, and the linked list size is increased by power of 2 after exceeding 8K (8192 byte). The ranges of the modified DPDK idle linked list are shown in table 2.
The method provided by the embodiment of the invention reduces the interval range of the DPDK idle memory linked list, and can avoid the influence of overlong individual linked list on the traversing efficiency, thereby further improving the memory allocation efficiency.
The prior art has the defects that the idle memory searching algorithm is low-efficiency besides the two aspects when the memory allocation is performed based on the DPDK idle linked list, and when a memory with a fixed size is needed, the idle linked list of the interval is needed to be traversed. Due to sequential traversal, on average, half of the elements in the free linked list are traversed under random conditions. Under the worst condition, the memory block with proper size may not be searched, and then the previous idle linked list needs to be traversed again.
In this regard, based on any one of the above embodiments, the performing memory allocation according to the size of the application memory and based on the modified DPDK idle linked list includes:
according to the size of the application memory, searching a memory block corresponding to the size of the application memory in a previous idle linked list of an idle linked list corresponding to the size of the application memory; and the interval range of the upper idle linked list is larger than the size of the application memory.
Specifically, when a memory with a specific size needs to find the idle linked list, a memory block is directly found in the idle linked list of the previous memory, for example: as shown in table 2, if a memory smaller than 256B is required, the idle linked list corresponding to the size of the memory is numbered 3, and then a memory block corresponding to the size of the memory is searched in the idle linked list of the previous stage of the idle linked list with the number 3, that is, memory allocation is performed in the idle linked list with the number 4 and the interval range of 256B-320B.
According to the method provided by the embodiment of the invention, the idle linked list does not need to be traversed, the fastest searching path is searched by utilizing the distribution rule of the memory linked list, and the searched memory blocks in the idle linked list necessarily meet the application size requirement, so that the idle memory searching efficiency is improved.
In order to test the effect of the embodiment of the invention, the memory allocation method provided by the embodiment of the invention is adopted to improve the memory allocation efficiency in the same hardware platform, the same configuration and the same test model.
The memory allocation device provided by the embodiment of the present invention is described below, and the memory allocation device described below and the memory allocation method described above may be referred to correspondingly.
Based on any of the above embodiments, fig. 2 is a schematic structural diagram of a memory allocation device according to an embodiment of the present invention, and as shown in fig. 2, the memory allocation device includes a memory allocation module 201.
The memory allocation module 201 is configured to obtain a size of an application memory, and allocate the memory based on the modified DPDK idle linked list according to the size of the application memory; the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and, the interval of the memory intervals of each idle linked list is the same.
According to the device provided by the embodiment of the invention, the number of DPDK idle linked lists is increased, so that the interval range of the idle memory linked list is reduced, and the lock conflict probability when multiple CPUs apply for the memory simultaneously is greatly reduced; only modifying individual parameters of the DPDK idle linked list can achieve the purpose of improving the memory allocation speed; the modified DPDK idle linked list can be applied to firewall products to improve the performance of the firewall products.
Based on any of the foregoing embodiments, the preset indicators include a mixed traffic throughput rate and a newly-built connection number, and the number of modified DPDK idle linked lists is 150.
Based on any one of the foregoing embodiments, the memory interval of each idle linked list is the same, including:
the memory intervals of the idle linked lists are spaced by the size of the first preset byte.
Based on any of the above embodiments, when the memory interval range of the idle linked list exceeds the size of the second preset byte, the memory intervals of the idle linked list are set at intervals in a preset manner.
Based on any of the above embodiments, the first preset byte is 64byte; the second preset byte is 8192 bytes; the preset manner is to increase in a manner of power of 2.
Based on any of the foregoing embodiments, the memory allocation according to the size of the application memory and based on the modified DPDK idle linked list includes:
according to the size of the application memory, searching a memory block corresponding to the size of the application memory in a previous idle linked list of an idle linked list corresponding to the size of the application memory; and the interval range of the upper idle linked list is larger than the size of the application memory.
The memory allocation device of the embodiment of the present invention may be used to execute the technical solutions of the embodiments of the foregoing memory allocation methods, and its implementation principle and technical effects are similar, and are not repeated here.
Fig. 3 illustrates a physical schematic diagram of an electronic device, as shown in fig. 3, where the electronic device may include: processor 310, communication interface (Communications Interface) 320, memory 330 and communication bus 340, wherein processor 310, communication interface 320, memory 330 accomplish communication with each other through communication bus 340. Processor 310 may invoke logic instructions in memory 330 to perform the flow of steps provided by the method embodiments described above.
Further, the logic instructions in the memory 330 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, embodiments of the present invention also provide a non-transitory computer readable storage medium having stored thereon a computer program that, when executed by a processor, is implemented to perform the step flow provided by the above embodiments.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A memory allocation method, comprising:
acquiring the size of an application memory, and performing memory allocation based on a modified DPDK idle linked list according to the size of the application memory;
the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and the interval between the memory intervals of the idle linked lists is the same;
the preset indexes comprise mixed flow throughput rate and newly-built connection number; the number of the modified DPDK idle linked lists is 150;
the memory interval of each idle linked list is the same, and the method comprises the following steps:
the memory interval of each idle linked list takes the size of a first preset byte as an interval; when the memory interval range of the idle linked list exceeds the size of a second preset byte, setting intervals among the memory intervals of the idle linked list in a preset mode; the preset manner is to increase in a manner of power of 2.
2. The memory allocation method according to claim 1, wherein the first predetermined byte is 64 bytes; the second preset byte is 8192 bytes.
3. The memory allocation method according to claim 1, wherein the performing memory allocation based on the modified DPDK idle linked list according to the size of the application memory includes:
according to the size of the application memory, searching a memory block corresponding to the size of the application memory in a previous idle linked list of an idle linked list corresponding to the size of the application memory; and the interval range of the upper idle linked list is larger than the size of the application memory.
4. A memory allocation apparatus, comprising:
the memory allocation module is used for acquiring the size of the application memory, and performing memory allocation based on the modified DPDK idle linked list according to the size of the application memory;
the modified DPDK idle linked list is obtained by increasing the number of the DPDK idle linked list based on a preset index; and the interval between the memory intervals of the idle linked lists is the same;
the preset indexes comprise mixed flow throughput rate and newly-built connection number; the number of the modified DPDK idle linked lists is 150;
the memory interval of each idle linked list is the same, and the method comprises the following steps:
the memory interval of each idle linked list takes the size of a first preset byte as an interval; when the memory interval range of the idle linked list exceeds the size of a second preset byte, setting intervals among the memory intervals of the idle linked list in a preset mode; the preset manner is to increase in a manner of power of 2.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the memory allocation method according to any one of claims 1 to 3 when executing the program.
6. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor performs the steps of the memory allocation method according to any of claims 1 to 3.
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| CN113220604B (en) * | 2021-05-31 | 2021-12-07 | 深圳华云信息系统有限公司 | Memory application method and device, electronic equipment and computer readable storage medium |
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