CN117271384A - Storage access method, device, chip and storage medium - Google Patents
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Abstract
The invention relates to the technical field of integrated circuits and discloses a storage access method, a device, a chip and a storage medium. The method comprises the following steps: acquiring a current access request and corresponding access storage addresses; obtaining a cut-off size corresponding to a current access memory request according to each access memory address, and dividing the current access memory request based on the cut-off size to obtain a plurality of sub access memory requests; performing address hash mapping on the access memory addresses corresponding to the sub access memory requests to obtain mapped access memory addresses corresponding to the sub access memory requests; and sending each sub memory request to a corresponding memory module matched with the mapping memory address so as to execute corresponding memory operation. According to the technical scheme, through cutting off the memory length of the memory request and carrying out address hash mapping on each sub memory request, the bus transmission efficiency can be improved, the memory conflict probability of a plurality of IPs in the same time period can be reduced, the stable memory efficiency is ensured, and the overall bandwidth utilization rate can be improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a memory access method, apparatus, chip, and storage medium.
Background
The current artificial intelligent chip has larger and larger storage capacity, realizes efficient and stable storage access, and has important significance for improving the performance of the chip.
In the prior art, each intellectual property (Intellectual Property, IP) core itself sends an access request to a memory module to perform a corresponding data storage or read operation. However, because the distances between the IP core initiating the storage access and each storage module are different, the routing paths are different, and the like, the delay and the bandwidth of accessing different address spaces can be greatly different; in addition, when multiple IP cores access the same memory module for a period of time, competition can occur between the IP cores, so that the access efficiency is unstable.
Disclosure of Invention
The invention provides a memory access method, a memory access device, a memory access chip and a memory medium, which can reduce the bandwidth difference of different address sections of access memories, reduce the access memory conflict probability of a plurality of IP (Internet protocol) within the same time section, ensure stable access memory efficiency and improve the overall bandwidth utilization rate.
According to an aspect of the present invention, there is provided a storage access method including:
acquiring a current access request and each access storage address corresponding to the current access request;
Obtaining a cut-off size corresponding to the current access memory request according to each access memory address, and dividing the current access memory request based on the cut-off size to obtain a plurality of sub access memory requests;
performing address hash mapping on the access memory address corresponding to each sub access memory request to obtain a mapped access memory address corresponding to each sub access memory request;
and sending each sub memory request to a corresponding memory module matched with the mapping memory address so as to execute corresponding memory operation.
According to another aspect of the present invention, there is provided a storage access apparatus including:
the access memory request acquisition module is used for acquiring a current access memory request and each access memory address corresponding to the current access memory request;
the access memory request segmentation module is used for obtaining the cut-off size corresponding to the current access memory request according to each access memory address, and segmenting the current access memory request based on the cut-off size so as to obtain a plurality of sub access memory requests;
the address hash mapping module is used for carrying out address hash mapping on the access memory addresses corresponding to the sub access memory requests so as to obtain mapped access memory addresses corresponding to the sub access memory requests;
And the sub memory request sending module is used for sending each sub memory request to the corresponding memory module matched with the mapping memory address so as to execute corresponding memory access operation.
According to another aspect of the present invention, there is provided a chip including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the memory access method of any one of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement a storage access method according to any one of the embodiments of the present invention when executed.
According to the technical scheme, the current access memory request and each access memory address corresponding to the current access memory request are obtained; then, according to each access storage address, obtaining a cut-off size corresponding to the current access storage request, and dividing the current access storage request based on the cut-off size to obtain a plurality of sub access storage requests; further, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests to obtain mapped access memory addresses corresponding to the sub access memory requests; finally, each sub memory access request is sent to a corresponding memory module matched with the mapping memory access address so as to execute corresponding memory access operation; the access length cut-off is carried out on the access request, so that the bus performance limit can be adapted, and the bus transmission efficiency is improved; and secondly, by carrying out address hash mapping on each sub memory access request, the bandwidth difference of different address sections of memory access can be reduced, the memory access conflict probability of a plurality of IPs in the same time section can be reduced, the stable memory access efficiency is ensured, and the overall bandwidth utilization rate can be improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1A is a flow chart of a method for memory access according to a first embodiment of the present invention;
FIG. 1B is a diagram illustrating request splitting according to a first embodiment of the present invention;
FIG. 1C is a diagram of an address hash map according to a first embodiment of the present invention;
FIG. 1D is a diagram illustrating another address hash map provided in accordance with a first embodiment of the present invention;
FIG. 1E is a diagram of another address hash map provided in accordance with a first embodiment of the present invention;
FIG. 1F is a diagram of another address hash map provided in accordance with a first embodiment of the present invention;
FIG. 1G is a diagram illustrating an address mapping according to a first embodiment of the present invention;
FIG. 2A is a flow chart of a method for memory access according to a second embodiment of the present invention;
FIG. 2B is a flowchart of another method for memory access according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a memory access device according to a third embodiment of the present invention;
fig. 4 is a schematic diagram of a chip for implementing a memory access method according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," "target," and the like in the description and claims of the present invention and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1A is a flowchart of a storage access method according to an embodiment of the present invention, where the method may be performed by a storage access device, and the storage access device may be implemented in hardware and/or software, and the storage access device may be configured in a chip. As shown in fig. 1A, the method includes:
s110, acquiring a current access request and each access storage address corresponding to the current access request.
The access request may be an access request for a storage module, and may include an identifier and an address of an access initiator, an identifier and an address of a storage module to be accessed, and the like. Specifically, after receiving the current access request, the current access request may be parsed based on a preset communication protocol, so as to obtain a storage access address corresponding to the current access request. The storage access address may be address information of a storage module to be accessed.
It should be noted that, a memory access operation for a plurality of memory modules may be initiated simultaneously by one memory access request; thus, in one access request, multiple memory module identifications and corresponding access memory addresses may be included. Specifically, by performing content analysis on the current access request, storage access addresses corresponding to the plurality of storage modules can be obtained. The data structure of the access request is not particularly limited in this embodiment.
In this embodiment, a master-slave (master slave mode) architecture may be adopted, where each storage access initiator is used as a master node, and a storage module is used as a slave node; the master node is used for accessing the slave node to execute data writing operation, and the slave node is used for executing data storage operation according to the memory access request of the master node. The routing paths between different master nodes and slave nodes may be the same or different.
S120, according to each access storage address, obtaining a cut-off size corresponding to the current access storage request, and dividing the current access storage request based on the cut-off size to obtain a plurality of sub access storage requests.
The cut-off size may include 128 bytes (B) and/or 512 bytes, among others. It will be appreciated that the supported cutoff size may be adaptively adjusted as the hardware configuration changes.
In this embodiment, for different request address ranges, corresponding cutoff sizes may be preset, and a mapping relationship between the request address ranges and the cutoff sizes may be established; thus, after a plurality of access memory addresses are acquired, it is possible to determine in which request address range each access memory address falls; after the request address range corresponding to each access storage address is successfully determined, the truncation size corresponding to the current access storage request can be determined according to the mapping relation between the preset request address range and the truncation size.
Specifically, after determining the cut-off size, the current access request may be divided into a plurality of sub-access requests with equal or unequal sizes according to the cut-off size, and the request identifier corresponding to the current access request may be remapped to the request identifier corresponding to each sub-access request. For example, as shown in fig. 1B, taking a truncated size of 512 bytes as an example, 512 bytes per interval is a truncated boundary; in one scenario, the Burst Length (BL) of the current memory request is 16 (memory request 1), and the addresses are aligned, access 16×128B (representing that the continuous transmission involves 16 memory modules), and the request identifier (Identity document, ID) is a; after splitting (clip), the sub-memory requests (access 4 x 128B) become 4 BL4, and the request identifications are remapped (remap) to A1 to A4.
In another scenario, the BL of the current memory request is 5 (memory request 2), the request is identified as B, and the addresses are not aligned, access 5X 128B, after clip and remap, become sub-memory requests of one BL3 and one BL2, and the IDs are remapped to B1 and B2. In another scenario, the BL of the current memory request is 16 (memory request 3), and the addresses are not aligned, 16X 128B is accessed, the request ID is C, after clip and remap, it becomes sub-memory requests of 1 BL1, 3 BL4 and 1 BL3, and the ID is remapped to C1 to C5.
The above arrangement has the advantage that the memory access request can be adapted to the performance limitations of AMBA (Advanced Microcontroller Bus Architecture ) buses, so that the transmission efficiency of the buses can be improved.
S130, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests to obtain mapped access memory addresses corresponding to the sub access memory requests.
In this embodiment, after the current access request is truncated, an address hash (hash) mapping may be performed on the access memory address corresponding to each sub-access request, so as to uniformly distribute the sub-access requests to the corresponding memory modules. When the address hash mapping is performed, the current cut-off size can be used as granularity of the hash. The mapping memory address may be an access address of a memory module obtained after address hash mapping.
In this embodiment, the type of the hash algorithm is not particularly limited, as long as the address hash mapping of the memory access can be implemented.
S140, each sub memory access request is sent to a corresponding memory module matched with the mapping memory access address so as to execute corresponding memory access operation.
Specifically, after the mapped memory address corresponding to each sub memory request is obtained, a memory module matched with each mapped memory address can be found according to a mapping relation between a preset address and the memory module, and each sub memory request is sent to the matched memory module, so that the memory module executes a data writing operation corresponding to the corresponding sub memory request.
According to the technical scheme, the current access memory request and each access memory address corresponding to the current access memory request are obtained; then, according to each access storage address, obtaining a cut-off size corresponding to the current access storage request, and dividing the current access storage request based on the cut-off size to obtain a plurality of sub access storage requests; further, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests to obtain mapped access memory addresses corresponding to the sub access memory requests; finally, each sub memory access request is sent to a corresponding memory module matched with the mapping memory access address so as to execute corresponding memory access operation; the access length cut-off is carried out on the access request, so that the bus performance limit can be adapted, and the bus transmission efficiency is improved; and secondly, by carrying out address hash mapping on each sub memory access request, the bandwidth difference of different address sections of memory access can be reduced, the memory access conflict probability of a plurality of IPs in the same time section can be reduced, the stable memory access efficiency is ensured, and the overall bandwidth utilization rate can be improved.
In an optional implementation manner of this embodiment, according to each access storage address, obtaining the truncated size corresponding to the current access storage request may include:
determining a primary address window corresponding to the current access memory request according to each access memory address;
and acquiring the cut-off size corresponding to the current access request according to the primary address window and the mapping relation between the preset address window and the cut-off size.
In this embodiment, a certain number of primary address windows may be preset, where each primary address window corresponds to a certain address interval range and is provided with a corresponding cutoff size; specifically, when determining the cut-off size corresponding to the current access request, it may first determine in which primary address window address range the access memory addresses fall, so as to determine the primary address window corresponding to the current access request; then, in the mapping relation between the preset address window and the cut-off size, searching to obtain the current cut-off size matched with the current primary address window, and taking the current cut-off size as the cut-off size corresponding to the current access request.
In another optional implementation manner of this embodiment, performing address hash mapping on the access storage address corresponding to each sub-access memory request to obtain a mapped access storage address corresponding to each sub-access memory request may include:
Acquiring the number of the storage modules;
when the number of the memory modules is the power of N of 2, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests based on a preset bit operation hash function to obtain mapped access memory addresses corresponding to the sub access memory requests; and
when the number of the storage modules is not the power of N of 2, performing address hash mapping on the access storage addresses corresponding to the sub access storage requests based on a mode of combining a preset bit operation hash function and a table lookup hash method so as to obtain mapped access storage addresses corresponding to the sub access storage requests;
wherein N is a natural number less than or equal to 5, and the values can be 0, 1, 2, 3, 4 and 5.
In this embodiment, when performing address hash mapping, different address hash mapping modes may be adopted for different numbers of storage modules. Specifically, the number of the memory modules included can be determined according to the address interval range of the primary address window corresponding to the current access request; alternatively, the number of memory modules may be determined according to preset configuration information. Further, when the number of the storage modules is N (N is less than or equal to 5) power of 2, a first-level address hash mapping mode can be adopted, and a mapping memory address corresponding to each sub memory request is obtained through a preset bit operation hash function; when the number of the storage modules is not 2 and N (N is less than or equal to 5) is not the power of N, a two-stage address hash mapping mode can be adopted, and the mapping memory access corresponding to each sub memory access request is obtained through a preset bit operation hash function and a table lookup hash method.
In a specific example, when the number of the memory modules is N (N is less than or equal to 5) power of 2, that is, when the hash of N power of 2 slave is performed, the access memory address corresponding to each sub-memory request and the preset hash mask may be brought into the preset bit operation hash function to calculate and obtain the mapped memory address corresponding to each sub-memory request. For example, the preset bit operation hash function may be expressed as:
function automatic[4:0]hash；
input[30:0]hash_mask[4:0]；//different mask for different bitsinput[30:0]addr_in；//address bits[37:7]
addr_hash[0]＝^(addr_in&hash_mask[0])；
addr_hash[1]＝^(addr_in&hash_mask[1])；
addr_hash[2]＝^(addr_in&hash_mask[2])；
addr_hash[3]＝^(addr_in&hash_mask[3])；
addr_hash[4]＝^(addr_in&hash_mask[4])；
endfunction
wherein, & represents a bitwise AND operation, & lt/EN & gt represents a bitwise XOR operation, and the granularity of the hash may be 128B or 512B. For example, a hash address calculation schematic with a granularity of 128b, a number of slots of 16, and a size of 32G for each slot may be shown in fig. 1C, where the mapping address is 4 bits; the granularity of the hash is 512b, the number of the slave is 16, and the size of each slave is 32G, which can be shown in fig. 1D; the granularity of the hash is 128b, the number of the slots is 8, and a hash address calculation schematic diagram with the size of 32G of each slot can be shown in fig. 1E; a hash address calculation schematic with a hash granularity 512b and a number of slots of 8, and a size of 32G for each slot may be shown in fig. 1F.
In this embodiment, after address hash mapping, the bandwidth difference of different address segments of access memory is greatly reduced, and meanwhile, the collision probability of initiating access memory in the same time period of multiple IPs is reduced, and the overall bandwidth utilization rate is improved.
In another optional implementation manner of this embodiment, based on a combination of a preset bit operation hash function and a table lookup hash method, performing address hash mapping on an access memory address corresponding to each sub-access memory request to obtain a mapped access memory address corresponding to each sub-access memory request may include:
based on a preset bit operation hash function, carrying out hash calculation on an access memory address corresponding to a current sub access memory request to obtain a memory group index value corresponding to the current sub access memory request;
acquiring a row index value and a column index value according to an access memory address corresponding to the current sub-access memory request and the number of memory modules corresponding to a memory group, and acquiring a lookup table index value corresponding to the current sub-access memory request from a preset lookup table according to the row index value and the column index value;
and acquiring a mapping memory address corresponding to the current sub memory request according to the memory group index value and the lookup table index value corresponding to the current sub memory request.
In a specific example, the number of slave is 10, and the address hash mapping procedure may be expressed as:
hash calculation of the slave group:
group_index= ζ (addr_in [23:7] & hash_mask); hash calculation of 5 slave using 1 hash_mask:
offset＝addr_in[23:8]/5；//13bits
row_index [6:0] = ζ (offset [12:0] & hash_mask [ i ]); use 7 hash_masks
col_index＝addr_in[23:8]％5；
lut _index=lookup_table [ row_index ] [ col_index ]; lookup table of// 128entry
Obtain index and offset of a certain slave:
slave_index＝lut_index*2+group_index；
slave_offset＝{offset[12:0],addr[6:0]}
specifically, first, the slave is divided into two storage groups (slave groups), and based on a preset bit operation hash function, hash calculation for selecting the slave group is performed with 128B as granularity, so as to obtain a storage group index value group_index, and the storage group index value group_index is used for selecting the upper slave group and the lower slave group. Meanwhile, 5 slave in the storage group are selected, specifically, 256B is used as granularity to calculate, after the access storage address is divided by 5, the quotient is brought into a preset bit operation hash function, and the row index value row_index of the lookup table is calculated; then, after carrying out modulo-5 operation on the access memory address, taking the remainder as a column index value col_index of the lookup table; further, based on the row_index and the col_index, searching in a lookup table to obtain a lookup table index value lut _index; finally, the index value of a certain distributed shared storage (Distributed shared storage system, DSM) is determined by the lut _index and the group_index to be used as the mapping memory address corresponding to the current sub memory access request.
The content of the lookup table is that the following 5 rows are always repeated: 0 12 3 4; 12 3 4 0;2 3 40 1;3 40 1 2; 40 12 3; the lookup_table may be defined as:
Persudo Code:
It should be noted that, the index value of each DSM occupies 2M (MByte) of memory space in the address mapping file, but the effective physical address actually has only 1M of space, and the addr_out [20] may be complemented with 0, and the address mapping may be as shown in fig. 1G.
In this embodiment, by adopting different address hash mapping modes according to different address ranges and storage device attributes and adjusting the setting of the hash mask, most of the address patterns in the real application scene can be more evenly located in all access memory regions.
Example two
Fig. 2A is a flowchart of a storage access method according to a second embodiment of the present invention, where the technical solution in this embodiment may be combined with one or more of the foregoing embodiments. As shown in fig. 2A, the method includes:
s210, acquiring a current access request and each access storage address corresponding to the current access request.
S220, determining a primary address window corresponding to the current access memory request according to each access memory address.
S230, obtaining a cut-off size corresponding to the current access request according to the primary address window and a mapping relation between a preset address window and the cut-off size, and dividing the current access request based on the cut-off size to obtain a plurality of sub-access requests.
Specifically, when dividing a current access request, firstly, performing matching detection of a primary address window on the current access request to determine which primary address window the current access request belongs to; then, according to the matching detection result of the primary address window and the mapping relation between the preset primary address window and the cut-off length, determining the cut-off size corresponding to the current access request; and finally, dividing the current access request into sub access requests corresponding to different identifications according to the cut-off size.
S240, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests to obtain mapped access memory addresses corresponding to the sub access memory requests.
S250, determining a secondary address window corresponding to each sub-access request according to the mapping access address corresponding to each sub-access request, and acquiring access priority corresponding to each sub-access request according to the secondary address window corresponding to each sub-access request.
In this embodiment, after determining the mapped memory address corresponding to each sub-memory request, a preset dynamic priority adjustment policy may be adopted to dynamically adjust the memory priority of each sub-memory request. Specifically, a mapping relationship among the secondary address window, the access address range and the dynamic priority adjustment policy may be preset, so that the secondary address window corresponding to the current sub-access request may be determined by determining the access address range of which secondary address window the mapped access address corresponding to the current sub-access request falls to, and further, the access priority corresponding to the current sub-access request may be determined according to the dynamic priority adjustment policy corresponding to the secondary address window.
The dynamic priority adjustment policy may be rule information for performing priority adjustment for the sub-access requests falling in the secondary address window, for example, setting the access priority to a preset value, a priority adjustment proportion, and the like. The access priority may be a priority of sending the sub-access request to the corresponding memory module for processing.
S260, according to the access priority corresponding to each sub access request, each sub access request is sent to a corresponding memory module matched with the mapping access address so as to execute corresponding access operation.
Specifically, after determining the access priority corresponding to each sub-access request, each sub-access request may be sequentially sent to the storage modules matched with the corresponding mapping access addresses according to the order of the priority from high to low, so that each storage module executes the corresponding access operation of the sub-access request after receiving the sub-access request.
In this embodiment, by adopting a dynamic priority adjustment policy, different priority adjustment policies are set for each master according to factors such as the position and bandwidth requirement of each master in the chip, so that the effect of balancing the access bandwidth of each master in the multi-master access system can be finally achieved.
After the mapping memory address corresponding to each sub memory request is obtained, determining a secondary address window corresponding to each sub memory request according to the mapping memory address corresponding to each sub memory request, and obtaining the memory priority corresponding to each sub memory request according to the secondary address window corresponding to each sub memory request; finally, according to the access priority corresponding to each sub access request, each sub access request is sent to a corresponding memory module matched with the mapping access address so as to execute corresponding access operation; by adopting a dynamic priority adjustment strategy, different access priorities are set for the masters at different positions, so that the access bandwidths of the different masters can be balanced, and the storage can be controlled without affinity.
In an optional implementation manner of this embodiment, according to the secondary address window corresponding to each sub-access request, obtaining the access priority corresponding to each sub-access request may include:
acquiring a priority adjustment proportion matched with a current secondary address window corresponding to a current sub-access request;
judging whether priority adjustment is needed to be carried out on the current sub-access request according to the priority adjustment proportion and the placement sequence of the current sub-access request in the current secondary address window;
If yes, acquiring the update priority matched with the current secondary address window, and adjusting the access priority corresponding to the current sub-access request to the update priority.
In a specific example, a corresponding priority adjustment RATIO qos_ratio=l/M may be set in advance for each secondary address window, that is, each M sub-memory requests, and the memory priority of the previous L sub-memory requests is rewritten to an updated priority QOS value. The QOS value may be preset according to historical experience, or may be calculated according to a relative position between the master and slave. And after the M sub memory access requests are sent, restarting to calculate and rewrite QOS values of the subsequent previous L sub memory access requests.
Specifically, according to the priority adjustment proportion corresponding to each secondary address window, determining the L and M values corresponding to the current sub-access request; then, judging whether the current sub-memory request is positioned in the L sub-memory request according to the placement sequence of the current sub-memory request in the current secondary address window; if yes, determining that priority adjustment is required to be performed on the current sub-access request, and calculating to obtain update priority according to the relative position between the master and slave corresponding to the current sub-access request, for example, if the relative position is far, setting higher update priority; if the relative position is closer, setting lower update priority and the like; finally, the access priority may be rewritten to the update priority.
In a specific implementation of this embodiment, the flow of the storage access method may be as shown in fig. 2B. Specifically, first, performing primary address window matching and mapping for an input access request to determine a cut-off size corresponding to the input access request; secondly, performing access length interception and identifier remapping based on the interception size to obtain a plurality of sub access requests; then, address hash mapping is carried out on each sub-access request so as to obtain a mapping access address corresponding to each sub-access request; further, performing secondary address window matching and QOS dynamic adjustment on each sub-access request to obtain the access priority corresponding to each sub-access request; and finally, outputting each sub-access request to a corresponding storage module according to the access priority corresponding to each sub-access request.
In the embodiment, through intercepting an input access request, performing configurable address hash mapping and dynamic priority adjustment, the method realizes the deamplification access to a large storage system, reduces the bandwidth reduction caused by multi-master access storage conflict, and balances the bandwidth of parallel access storage among a plurality of masters.
Example III
Fig. 3 is a schematic structural diagram of a memory access device according to a third embodiment of the present invention. As shown in fig. 3, the apparatus may include: the memory access request acquisition module 310, the memory access request segmentation module 320, the address hash mapping module 330 and the sub memory access request sending module 340; wherein,
The access request obtaining module 310 is configured to obtain a current access request and each access memory address corresponding to the current access request;
the memory request splitting module 320 is configured to obtain a cut-off size corresponding to the current memory request according to each of the access memory addresses, and split the current memory request based on the cut-off size, so as to obtain a plurality of sub memory requests;
the address hash mapping module 330 is configured to perform address hash mapping on the access memory address corresponding to each sub-access memory request, so as to obtain a mapped access memory address corresponding to each sub-access memory request;
the sub-memory request sending module 340 is configured to send each sub-memory request to a corresponding memory module with a mapped memory address, so as to execute a corresponding memory operation.
According to the technical scheme, the current access memory request and each access memory address corresponding to the current access memory request are obtained; then, according to each access storage address, obtaining a cut-off size corresponding to the current access storage request, and dividing the current access storage request based on the cut-off size to obtain a plurality of sub access storage requests; further, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests to obtain mapped access memory addresses corresponding to the sub access memory requests; finally, each sub memory access request is sent to a corresponding memory module matched with the mapping memory access address so as to execute corresponding memory access operation; the access length cut-off is carried out on the access request, so that the bus performance limit can be adapted, and the bus transmission efficiency is improved; and secondly, by carrying out address hash mapping on each sub memory access request, the bandwidth difference of different address sections of memory access can be reduced, the memory access conflict probability of a plurality of IPs in the same time section can be reduced, the stable memory access efficiency is ensured, and the overall bandwidth utilization rate can be improved.
Optionally, the memory access request splitting module 320 is specifically configured to determine, according to each of the memory access addresses, a primary address window corresponding to the current memory access request;
and acquiring the cut-off size corresponding to the current access request according to the primary address window and the mapping relation between the preset address window and the cut-off size.
Optionally, the address hash mapping module 330 is specifically configured to obtain the number of storage modules;
when the number of the memory modules is the power of N of 2, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests based on a preset bit operation hash function to obtain mapped access memory addresses corresponding to the sub access memory requests; and
when the number of the storage modules is not the power of N of 2, performing address hash mapping on the access storage addresses corresponding to the sub access storage requests based on a mode of combining a preset bit operation hash function and a table lookup hash method so as to obtain mapped access storage addresses corresponding to the sub access storage requests;
wherein N is a natural number less than or equal to 5.
Optionally, the address hash mapping module 330 is specifically configured to perform hash computation on an access storage address corresponding to a current sub-access request based on a preset bit operation hash function, so as to obtain a storage group index value corresponding to the current sub-access request;
Acquiring a row index value and a column index value according to an access memory address corresponding to the current sub-access memory request and the number of memory modules corresponding to a memory group, and acquiring a lookup table index value corresponding to the current sub-access memory request from a preset lookup table according to the row index value and the column index value;
and acquiring a mapping memory address corresponding to the current sub memory request according to the memory group index value and the lookup table index value corresponding to the current sub memory request.
Optionally, the sub-access request sending module 340 is specifically configured to determine a secondary address window corresponding to each sub-access request according to a mapped access address corresponding to each sub-access request, and obtain an access priority corresponding to each sub-access request according to the secondary address window corresponding to each sub-access request;
and sending each sub-access request to a corresponding memory module matched with the mapping access address according to the access priority corresponding to each sub-access request so as to execute corresponding access operation.
Optionally, the sub-access request sending module 340 is specifically configured to obtain a priority adjustment ratio matched with a current secondary address window corresponding to a current sub-access request;
Judging whether priority adjustment is needed to be carried out on the current sub-access request according to the priority adjustment proportion and the placement sequence of the current sub-access request in the current secondary address window;
if yes, acquiring the update priority matched with the current secondary address window, and adjusting the access priority corresponding to the current sub-access request to the update priority.
Optionally, the truncated size includes 128 bytes and/or 512 bytes.
The memory access device provided by the embodiment of the invention can execute the memory access method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
It should be noted that, in the technical solution of the present embodiment, the related acquisition, storage, application, etc. of the personal information of the user all conform to the rules of the related laws and regulations, and do not violate the popular regulations of the public order.
Example IV
Fig. 4 shows a schematic diagram of the structure of a chip 40 that may be used to implement an embodiment of the invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the chip 40 includes at least one processor 41, and a memory communicatively connected to the at least one processor 41, such as a Read Only Memory (ROM) 42, a Random Access Memory (RAM) 43, etc., in which the memory stores a computer program executable by the at least one processor, and the processor 41 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 42 or the computer program loaded from the storage unit 48 into the Random Access Memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the chip 40 can also be stored. The processor 41, the ROM 42 and the RAM 43 are connected to each other via a bus 44. An input/output (I/O) interface 45 is also connected to bus 44.
The various components in the chip 40 are connected to the I/O interface 45, including: an input unit 46, an output unit 47, and a storage unit 48; and a communication unit 49 such as a network card, modem, wireless communication transceiver, etc. The communication unit 49 allows the chip 40 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The processor 41 may be various general and/or special purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 41 performs the various methods and processes described above, such as a memory access method.
In some embodiments, the storage access method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 48. In some embodiments, part or all of the computer program may be loaded and/or installed onto the chip 40 via the ROM 42 and/or the communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the storage access method described above may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the memory access method in any other suitable way (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A memory access method, comprising:
acquiring a current access request and each access storage address corresponding to the current access request;
obtaining a cut-off size corresponding to the current access memory request according to each access memory address, and dividing the current access memory request based on the cut-off size to obtain a plurality of sub access memory requests;
performing address hash mapping on the access memory address corresponding to each sub access memory request to obtain a mapped access memory address corresponding to each sub access memory request;
And sending each sub memory request to a corresponding memory module matched with the mapping memory address so as to execute corresponding memory operation.
2. The method of claim 1, wherein obtaining the truncated size corresponding to the current access request according to each access memory address comprises:
determining a primary address window corresponding to the current access memory request according to each access memory address;
and acquiring the cut-off size corresponding to the current access request according to the primary address window and the mapping relation between the preset address window and the cut-off size.
3. The method of claim 1, wherein performing address hash mapping on the access memory address corresponding to each of the sub-access memory requests to obtain a mapped access memory address corresponding to each of the sub-access memory requests, comprises:
acquiring the number of the storage modules;
when the number of the memory modules is the power of N of 2, performing address hash mapping on the access memory addresses corresponding to the sub access memory requests based on a preset bit operation hash function to obtain mapped access memory addresses corresponding to the sub access memory requests; and
when the number of the storage modules is not the power of N of 2, performing address hash mapping on the access storage addresses corresponding to the sub access storage requests based on a mode of combining a preset bit operation hash function and a table lookup hash method so as to obtain mapped access storage addresses corresponding to the sub access storage requests;
Wherein N is a natural number less than or equal to 5.
4. The method of claim 3, wherein performing address hash mapping on the access memory address corresponding to each sub-access memory request based on a combination of a preset bit operation hash function and a table lookup hash method to obtain a mapped access memory address corresponding to each sub-access memory request, comprises:
based on a preset bit operation hash function, carrying out hash calculation on an access memory address corresponding to a current sub access memory request to obtain a memory group index value corresponding to the current sub access memory request;
acquiring a row index value and a column index value according to an access memory address corresponding to the current sub-access memory request and the number of memory modules corresponding to a memory group, and acquiring a lookup table index value corresponding to the current sub-access memory request from a preset lookup table according to the row index value and the column index value;
and acquiring a mapping memory address corresponding to the current sub memory request according to the memory group index value and the lookup table index value corresponding to the current sub memory request.
5. The method of claim 1, wherein sending each of the child memory requests to a corresponding mapped memory address-matched memory module to perform a respective memory operation comprises:
Determining a secondary address window corresponding to each sub-access request according to the mapping access address corresponding to each sub-access request, and acquiring access priority corresponding to each sub-access request according to the secondary address window corresponding to each sub-access request;
and sending each sub-access request to a corresponding memory module matched with the mapping access address according to the access priority corresponding to each sub-access request so as to execute corresponding access operation.
6. The method of claim 5, wherein obtaining access priorities corresponding to the sub-access requests according to secondary address windows corresponding to the sub-access requests, comprises:
acquiring a priority adjustment proportion matched with a current secondary address window corresponding to a current sub-access request;
judging whether priority adjustment is needed to be carried out on the current sub-access request according to the priority adjustment proportion and the placement sequence of the current sub-access request in the current secondary address window;
if yes, acquiring the update priority matched with the current secondary address window, and adjusting the access priority corresponding to the current sub-access request to the update priority.
7. The method according to claim 1 or 2, characterized in that the cut-off size comprises 128 bytes and/or 512 bytes.
8. A memory access device, comprising:
the access memory request acquisition module is used for acquiring a current access memory request and each access memory address corresponding to the current access memory request;
the access memory request segmentation module is used for obtaining the cut-off size corresponding to the current access memory request according to each access memory address, and segmenting the current access memory request based on the cut-off size so as to obtain a plurality of sub access memory requests;
the address hash mapping module is used for carrying out address hash mapping on the access memory addresses corresponding to the sub access memory requests so as to obtain mapped access memory addresses corresponding to the sub access memory requests;
and the sub memory request sending module is used for sending each sub memory request to the corresponding memory module matched with the mapping memory address so as to execute corresponding memory access operation.
9. A chip, the chip comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the storage access method of any one of claims 1-7.
10. A computer readable storage medium storing computer instructions for causing a processor to implement the storage access method of any one of claims 1-7 when executed.
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| CN117478626B (en) * | 2023-12-27 | 2024-04-05 | 天津光电聚能通信股份有限公司 | Quick matching searching system, method, equipment and medium based on group connection cache |
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