CN112148655A - Method and device for processing multi-bit data across clock domains - Google Patents
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Abstract
The invention provides a method and a device for processing multi-bit data across clock domains; wherein, the method comprises the following steps: acquiring data output from a sending clock domain side to a receiving clock domain side, wherein the sending clock domain and the receiving clock domain are different clock domains; detecting whether the data is changed; under the condition that the data are changed, updating and outputting the data; and keeping the original output data under the condition that the data is not changed. The invention solves the problems of large hardware overhead and high transmission delay caused by bidirectional interaction of the sending clock domain and the receiving clock domain in the processing mode of cross-clock domain transmission in the related technology.
Description
Technical Field
The invention relates to the field of computers, in particular to a method and a device for processing multi-bit data across clock domains.
Background
In modern electronic systems, digital integrated circuit systems are becoming larger and larger, and include more and more modules, and support more and more complex functions, and the requirements for power consumption are also becoming higher and higher. Therefore, today, SoC (System on Chip) usually includes multiple clock domains, and the clock architecture design adopts GALS form, i.e. Global Asynchronous (Global Asynchronous) processing and Local Synchronous (Local Synchronous) processing.
The GALS clock architecture has many advantages, such as (1) on the premise of meeting performance requirements, each module can be operated at the lowest possible clock frequency, and dynamic power consumption is smaller; (2) the clock is relatively easy to realize, the clock tree is small, the time sequence is easy to converge, and the area is smaller.
In GALS socs, there is inevitably a data transfer across clock domains. Since the phase relationship between asynchronous clocks is uncertain, it is easy for data to be transferred from one clock domain to another asynchronous clock domain if the setup time (setup time) or hold time (hold time) of a register is not satisfied, resulting in meta-stability. Metastability issues can lead to erroneous sampling of the transmitted data, and, if not handled correctly, can even worse lead to a faulty state of the SoC system, which is not working properly and is difficult to locate.
For a single-bit signal, when the signal is transmitted across clock domains, a two-stage register synchronization mode is usually adopted to effectively reduce the probability of metastable state occurrence. Even if a metastable state occurs, after the single-bit signal is subjected to two-stage synchronous processing, wrong data sampling cannot occur, and only the delay of data transmission is changed.
For a multi-bit signal, when the signal is transmitted across clock domains, only a two-stage register synchronization mode cannot be adopted. Because there is data coherence between multi-bit signals, that is, if a bit or multi-bit signal is metastable, erroneous intermediate data may be sampled, resulting in an error state in the SoC system.
In the related art, the processing modes of multi-bit signal transmission across clock domains include the following three types: 1) enabling a signal synchronization mode; 2) handshake (Handshaking) interaction mode; 3) asynchronous FIFO mode. In the above methods in the related art, bidirectional interaction of control signals of the sending clock domain and the receiving clock domain is required, and the implementation is complex, the hardware overhead is large, and the transmission delay is high.
In view of the above problems in the related art, no effective technical solution exists at present.
Disclosure of Invention
The embodiment of the invention provides a method and a device for processing multi-bit data across clock domains, which are used for at least solving the problems of high hardware overhead and high transmission delay caused by bidirectional interaction of a sending clock domain and a receiving clock domain in a processing mode of cross-clock domain transmission in the related technology.
According to an embodiment of the present invention, there is provided a method for processing multiple bits of data across clock domains, including: acquiring data output from a sending clock domain side to a receiving clock domain side, wherein the sending clock domain and the receiving clock domain are different clock domains; detecting whether the data is changed; under the condition that the data are changed, updating and outputting the data; and keeping the original output data under the condition that the data is not changed.
According to another embodiment of the present invention, there is provided a multi-bit data clock domain crossing processing apparatus, including: an obtaining module, configured to obtain data output from a sending clock domain side to a receiving clock domain side, where the sending clock domain and the receiving clock domain are different clock domains; the detection module is used for detecting whether the data are changed or not; the processing module is used for updating and outputting the data when the change of the data is detected; and keeping the original output data under the condition that the data is not changed.
According to the method and the device, data output from a sending clock domain side to a receiving clock domain side are obtained, wherein the sending clock domain and the receiving clock domain are different clock domains, and then whether the data change or not is detected, and the data are output after being updated under the condition that the data change; under the condition that the data is not changed, original output data is kept; therefore, the method and the device realize the processing of the multi-bit data across clock domains under the condition that the sending clock domain and the receiving clock domain are relatively independent, solve the problems of high hardware overhead and high transmission delay caused by bidirectional interaction of the sending clock domain and the receiving clock domain in the processing mode of the cross-clock domain transmission in the related technology, and can use more application scenes, and the whole implementation mode is efficient and simple.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a flow chart of a method of processing multi-bit data across clock domains according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a multi-bit data cross-clock domain transmission apparatus according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of multi-bit data transfer across clock domains according to an embodiment of the invention;
FIG. 4 is a schematic diagram of signal waveforms at various key points in accordance with an embodiment of the present invention;
fig. 5 is a schematic diagram of a multi-bit data clock domain crossing processing apparatus according to an alternative embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Example 1
In this embodiment, a multi-bit data cross-clock domain processing method is provided, and fig. 1 is a flowchart of a multi-bit data cross-clock domain processing method according to an embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:
step S102, acquiring data output from a sending clock domain side to a receiving clock domain side, wherein the sending clock domain and the receiving clock domain are different clock domains;
step S104, detecting whether the data changes;
step S106, updating and outputting the data under the condition that the data are changed; and keeping the original output data under the condition that the data is not changed.
Through the steps S102 to S106, data output from the sending clock domain side to the receiving clock domain side is obtained, where the sending clock domain and the receiving clock domain are different clock domains, and then whether the data changes is detected, and the data is output after being updated under the condition that the data changes; under the condition that the data is not changed, original output data is kept; therefore, the method and the device realize the processing of the multi-bit data across clock domains under the condition that the sending clock domain and the receiving clock domain are relatively independent, solve the problems of high hardware overhead and high transmission delay caused by bidirectional interaction of the sending clock domain and the receiving clock domain in the processing mode of the cross-clock domain transmission in the related technology, and can use more application scenes, and the whole implementation mode is efficient and simple.
It should be noted that the method steps of steps S102 to S106 are all executed on the receiving clock domain side, that is, executed by a device or apparatus on the receiving clock domain side, and do not relate to the transmitting clock domain side. As in the optional implementation manner of this embodiment, as to the manner of acquiring the data output by the sending clock domain side to the receiving clock domain side in step S102 of this application, it can be implemented by the following manner:
step S102-11, receiving data output from the register of the sending clock domain side to the receiving clock domain side;
and S102-12, carrying out synchronous processing on the data through an N-level data synchronizer at the receiving clock domain side, wherein the value of N is determined by the average fault interval time.
It can be seen that after receiving the data output from the transmitting clock domain side, the receiving clock domain side data synchronizer performs the synchronization process, i.e. the step S102-11 and the step S102-12 are performed on the receiving clock domain side.
The number of stages N of the synchronizer is determined by the requirement of Mean Time Between Failures (MTBF).
In equation (1), S reserves the decision time for the data synchronizer for the register. The resolution time (resolution time), i.e. the time for the register to recover to a stable value of 0 or 1 randomly after entering the meta-stable state because the setup or hold time is not satisfied. The relationship between the number of stages N and S of the data synchronizer is shown as follows.
S＝T·(N-1)
Formula (2) with N ≧ 2
In equation (2), T represents the clock period of the receiving clock domain. For example, when N is 2, S is equal to 1 clock period of the receive clock; when N is 3, S is equal to 2 clock periods of the receive clock. τ is a constant associated with the process. W is the sum of the register setup time and hold time, which is related to the process. FC is the frequency of the receive clock. FD is the frequency at which data is transmitted. In summary, according to the requirement of the MTBF, the S value, and thus the number of stages N of the data synchronizer, is determined.
In addition, in another optional implementation manner of this embodiment, a manner of whether the detection data involved in step S104 of this application is changed may be: whether the data of the current period is changed or not compared with the data of the last period is detected by a change detector on the receiving clock domain side to determine whether the received data is changed or not. It can be seen that the detection is also performed by the change detector on the receiving clock domain side.
In another optional embodiment of the present application, in a case that data changes, updating and outputting the data includes: under the condition that data changes, an edge detector on the receiving clock domain side outputs an effective value and triggers a data selector on the receiving clock domain side to output updated data; under the condition that the data is not changed, the original output data is maintained, and the method comprises the following steps: when data changes, an edge detector on the receiving clock domain side outputs an invalid value, and triggers a data selector to keep the original output data. It can be seen that the output of data (including the output after updating and the retention of the original output data) is performed by the receiving clock domain side edge detector.
It should be noted that the method steps of the present application further include: after detecting whether the data changes, buffering the data output by the change detector through an M-level buffer on the receiving clock domain side, wherein M is larger than or equal to N-1.
In order that the present disclosure may be more clearly understood, the present disclosure will now be described with reference to alternative embodiments thereof;
the optional embodiment provides a design method and a device for a novel multi-bit data cross-clock-domain transmission digital integrated circuit, so as to meet the requirement of multi-bit data cross-clock-domain transmission in the digital integrated circuit.
Fig. 2 is a schematic structural diagram of a multi-bit data cross-clock domain transmission apparatus according to an embodiment of the present invention, as shown in fig. 2: the sending clock domain1 and the receiving clock domain2 are different clock domains, and the clocks are asynchronous. Meanwhile, the transmitting clock domain and the receiving clock domain may be different power domains (power domain1 and power domain2) or different voltage domains (voltage domain1 and voltage domain 2).
The sending data output from the sending clock domain register enters a receiving clock domain, is received by the multi-bit data cross-clock domain transmission device disclosed by the invention, is correctly processed and then is provided for a functional logic circuit of the receiving clock domain to use.
The multi-bit data clock domain crossing device comprises the following 5 functional modules: a data synchronizer, a change detector, a buffer, an edge detector, and a data selector.
The overall work flow (i.e. signal processing flow) of the device comprises:
step S11, the received data is synchronized by the data synchronizer;
step S12, detecting whether there is a change in the data by the change detector;
step S13, if the received data is changed, the change detector outputs a change indication signal, and the multi-bit data is stabilized through the buffering of the buffer;
step S14, the change indication signal is processed by the edge detector to instruct the data selector to update the output data;
in step S15, if the received data has not changed, the data selector keeps the original output.
It should be noted that all the above entire processes are performed in the receiving clock domain, and the sending clock domain is not involved.
The functional modules in the device are explained below.
The data synchronizer is a two-stage or multi-stage register synchronizer with the same bit width as the transmission data and is used for reducing the probability of the metastable state of the clock domain crossing. The number of stages N of the synchronizer is determined by the requirement of Mean Time Between Failures (MTBF).
Wherein S reserves the decision time for the data synchronizer to the register. The resolution time (resolution time), i.e. the time for the register to recover to a stable value of 0 or 1 randomly after entering the meta-stable state because the setup or hold time is not satisfied. The relation between the stage number N and S of the data synchronizer is as follows:
S＝T·(N-1)
N≥2
where T represents the clock period of the receiving clock domain. For example, when N is 2, S is equal to 1 clock period of the receive clock; when N is 3, S is equal to 2 clock periods of the receive clock. In addition, τ is a constant associated with the process. W is the sum of the register setup time and hold time, which is related to the process. FCIs the frequency of the receive clock. FDIs the frequency at which the data is transmitted.
Therefore, the number of stages N of the data synchronizer is determined by determining the S value according to the requirement of the MTBF. It should be noted that each transmit data needs to be held for at least N clock cycles of the receive clock domain before it can be changed to ensure that the transmit data can be correctly sampled without being lost.
The change detector is used for detecting whether the synchronized data changes; if there is a change in the data of the current cycle compared to the data of the previous cycle, the change detector outputs a valid value. The change detector outputs an invalid value if the data of the current cycle is unchanged from the data of the previous cycle.
The buffer is used for carrying out register buffer processing on the output value of the change detector, and is used for waiting for the stabilization of the multi-bit data, keeping the correlation among the bits in the multi-bit data and avoiding the error sampling of the intermediate state of the multi-bit data. The relation between the buffering level M of the buffer and the level N of the data synchronizer is as follows: m is not less than N-1
Optionally, the data transmission delay (latency) is: latency ═ N + M · T
Where Latency represents the time interval between data input and output. When the stage number M of the buffer is equal to the stage number N-1 of the data synchronizer, the data can be correctly sampled and the transmission delay is optimal on the premise of meeting the MTBF requirement.
The edge detector is used for detecting whether the output of the buffer changes; if the signal of the current period changes compared with the signal of the last period, the output of the edge detector is a valid value and is kept for one sampling clock period. If the signal of the current period is unchanged from the signal of the previous period, the edge detector output is an invalid value.
The data selector selects and outputs either the currently input multi-bit data or the last valid multi-bit data by using the output of the edge detector as a selection signal. When the selection signal output by the edge detector is invalid, the valid multi-bit data on the output is maintained. When the selection signal is effective, the multi-bit data currently input is selected and output.
The optional implementation mode aims at the application scene of multi-bit data cross-clock domain, the data transmission is controlled in a one-way mode, the transmission delay is configurable, the efficiency is high, the operation is ingenious, a sending clock does not need to participate in the cross-clock domain processing, and the independence of the sending clock domain and the receiving clock domain is improved.
Therefore, the optional embodiment is not only applicable to the application scenario of multi-bit data crossing clock domains in the general case, but also more applicable to the application scenario in which the transmit clock domain and the receive clock domain are relatively independent, for example, the transmit clock domain and the receive clock domain are in different power domains or different voltage domains. Based on this, there is no need to design circuit devices in the transmit clock domain; on the other hand, except for sending data, no other control signal crosses a clock domain (or a power domain or a voltage domain), so that the high efficiency and the simplicity are realized. In addition, the data synchronizer stage number and the buffer stage number are set according to the requirement of Mean Time Between Failures (MTBF), and the configuration is flexible.
Fig. 3 is a schematic diagram of multi-bit data transmission across clock domains according to an embodiment of the present invention, as shown in fig. 3, the present embodiment samples data on the rising edge of the clock, and the 5 functional blocks are the data synchronizer (20), the change detector (21), the buffer (22), the rising edge detector (23), and the data selector (24), respectively.
The data synchronizer (20) is a two-stage or multi-stage register synchronizer that is as wide as the transmission data and is used for receiving and synchronizing the data0 transmitted from the transmission clock domain so as to reduce the probability of metastable state occurring across the clock domains. Generally speaking, a two-stage data synchronizer can meet the MTBF requirements. In this embodiment, the data synchronizer is composed of a D flip-flop (DFF), the number of stages N is 2, and the data bit width is 3 bits.
The function of the change detector (21) is to detect whether the synchronized data changes, and the output signal is processed by the change detector (21), the buffer (22) and the rising edge detector (23) and used for controlling the data selector (24). If one or more bits of the data2 of the current period are changed from the data3 of the previous period, the change detector (21) outputs a signal1 of 1' b 1. If the data2 of the current period has not changed from the data3 of the previous period, the change detector (21) outputs a signal1 of 1' b 0. In the present embodiment, the change detector (21) is composed of a D flip-flop and an exclusive or gate (XOR).
The buffer (22) is used for buffering the output signal1 of the change detector (21), and is correctly selected and sampled after the data2 is stabilized, so that intermediate state data are prevented from being acquired. In this embodiment, the buffer (22) is composed of D flip-flops, and the number of buffer stages M is the same as the number of stages N of the data synchronizer (20), i.e., M is 2. Signal2 is the first stage buffered output signal and signal3 is the second stage buffered output signal.
The rising edge detector (23) functions to detect whether or not a rising edge change occurs in the output signal3 of the buffer (22). If the signal3 of the current period is changed from 1 ' b0 to 1 ' b1 compared to the signal4 of the previous period, the rising edge detector output signal5 is 1 ' b1 and is held for one sampling clock period for the data selector (24) to gate and update the output data. In addition, the edge detector output signal5 is 1' b 0. In the present embodiment, the rising edge detector (23) is composed of a D flip-flop, a not gate, an AND gate (AND), AND the like.
The data selector (24) functions to select either one of the currently inputted multi-bit data2 and the last valid multi-bit data4 for output. When the select signal5 is 1' b0, the last valid data4 is kept output. When the selection signal5 is 1' b1, the currently input data2 is selected to be updated and output. In the present embodiment, the data selector (24) is composed of a D flip-flop and an alternative selector (MUX).
The input signal is data transmitted in the transmission clock domain and the clock of the reception clock domain, the output signal is data received in the reception clock domain, and the entire transmission delay is N + M, which is 4 clock cycles of the reception clock.
Fig. 4 is a schematic diagram of signal waveforms at various keys according to an embodiment of the present invention, and signal names in fig. 4 correspond to respective signals shown in fig. 3. As shown in fig. 4, at any time between the 2 nd time and the 3 rd time, the data0 transmitted by the transmission clock domain changes from 3 'b 000 to 3' b 111. The transmit clock is not shown in fig. 3, but is independent of the transmit clock domain since embodiments of the present application do not need to focus on transmit clock information. Data0 is sampled by the clock of the receiving clock domain on each rising edge. The data synchronizer performs two-stage synchronization on data 0. The first stage output data is data1, and the second stage output data is data 2.
At time 3, each bit of data1 may be either a0 or a1 due to metastability reasons, so data1 may be any intermediate state from 3 'b 000 to 3' b111 as a whole. In fig. 4, only the intermediate state 3' b101 is taken as an example.
At time 4, data1 is correctly sampled as 3' b111 with a large probability within the MTBF interval. Meanwhile, the change detector detects a change between data2 and data3, and the output signal1 changes from 1 'b 0 to 1' b 1.
Note that, when data2 is in the intermediate state (3' b101), erroneous sampling output to data4 should be avoided. Therefore, signal1 outputs signal3 after two-stage buffering by the buffer. Data update of the data4 is controlled by the signal 3.
And the 5 th time is the signal buffering time, and the data correlation of each bit is kept after the data2 is restored to a stable state.
At time 6, after the rising edge detector detects the rising edge of signal3, output signal5 changes from 1 'b 0 to 1' b1 and remains for 1 clock cycle. Meanwhile, signal5 gates the data selector, data4 is updated, and data2 is output, that is, multi-bit data after crossing the clock domain is output, and the whole transmission delay is 4 clock cycles of the receiving clock.
According to the embodiment, the method and the device mainly aim at the multi-bit data cross-clock domain application scene, the data transmission is controlled in a one-way mode, the transmission delay is configurable, the method and the device are efficient and ingenious, a sending clock does not need to participate in cross-clock domain processing, and the independence of the sending clock domain and the receiving clock domain is improved. The method is not only suitable for the application scenario of multi-bit data crossing clock domains in the common situation, but also more suitable for the application scenario that the sending clock domain and the receiving clock domain are relatively independent, for example, the sending clock domain and the receiving clock domain are in different power domains or different voltage domains. Therefore, no design circuit arrangement in the transmit clock domain is required; besides sending data, no other control signal crosses a clock domain (or a power domain or a voltage domain), and the high efficiency and the simplicity are realized. In addition, the application supports setting the number of data synchronizers and the number of buffers according to the requirement of Mean Time Between Failure (MTBF) so as to make the configuration flexible.
Example 2
In this embodiment, a multi-bit data clock domain crossing processing apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description already made is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 5 is a block diagram of a multi-bit data clock domain crossing processing apparatus according to an embodiment of the present invention, as shown in fig. 5, the apparatus including: an obtaining module 52, configured to obtain data output from a sending clock domain side to a receiving clock domain side, where the sending clock domain and the receiving clock domain are different clock domains; the detection module 54 is coupled and linked with the acquisition module 52 and is used for detecting whether the data is changed; the processing module 56 is coupled to the detection module 54, and is configured to update and output the data when detecting that the data changes; and keeping the original output data when the data is not detected to be changed.
Optionally, the obtaining module 52 in the present application further includes: a data synchronizer for receiving data output from the register on the transmission clock domain side to the reception clock domain side; and carrying out synchronous processing on the data, wherein the data synchronizer is an N-level synchronizer, and the value of N is determined by the average fault interval time.
Optionally, the detection module 54 in the present application may further include: and the change detector is used for detecting whether the comparison between the data of the current period and the data of the previous period changes or not so as to determine whether the received data changes or not.
Optionally, the processing module 56 in the present application may further include: the edge detector is used for outputting an effective value under the condition that the data changes and triggering the data selector at the receiving clock domain side to output updated data; and under the condition that the data are changed, outputting an invalid value and triggering a data selector to keep the original output data.
Optionally, the apparatus in the present application may further include: and the buffer is used for buffering the data output by the change detector after detecting whether the data is changed, wherein the buffer is an M-level buffer, and M is more than or equal to N-1.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for processing multi-bit data across clock domains, comprising:
acquiring data output from a sending clock domain side to a receiving clock domain side, wherein the sending clock domain and the receiving clock domain are different clock domains;
detecting whether the data is changed;
under the condition that the data are changed, updating and outputting the data; and keeping the original output data under the condition that the data is not changed.
2. The method of claim 1, wherein obtaining data output by a transmit clock domain side to a receive clock domain side comprises:
receiving data output to the receiving clock domain side by a register of the transmitting clock domain side;
and carrying out synchronous processing on the data through an N-level data synchronizer at the receiving clock domain side, wherein the value of N is determined by the average fault interval time.
3. The method of claim 2, wherein the detecting whether the data is changed comprises:
and detecting whether the comparison between the data of the current period and the data of the previous period changes or not by a change detector at the receiving clock domain side so as to determine whether the received data changes or not.
4. The method of claim 3, comprising:
when the data changes, the updating and outputting of the data comprises the following steps: under the condition that the data changes, outputting an effective value by an edge detector on the receiving clock domain side, and triggering a data selector on the receiving clock domain side to output updated data;
under the condition that the data is not changed, the method for maintaining the original output data comprises the following steps: and under the condition that the data is not changed, outputting an invalid value by an edge detector on the receiving clock domain side, and triggering the data selector to keep the original output data.
5. The method of claim 4, wherein after detecting whether the data has changed, the method further comprises:
and buffering the data output by the change detector through an M-level buffer at the side of the receiving clock domain, wherein M is more than or equal to N-1.
6. A multi-bit data clock domain cross processing apparatus, comprising:
an obtaining module, configured to obtain data output from a sending clock domain side to a receiving clock domain side, where the sending clock domain and the receiving clock domain are different clock domains;
the detection module is used for detecting whether the data are changed or not;
the processing module is used for updating and outputting the data when the change of the data is detected; and keeping the original output data under the condition that the data is not changed.
7. The apparatus of claim 6, wherein the obtaining module comprises:
a data synchronizer for receiving data output from a register on a transmission clock domain side to the reception clock domain side; and carrying out synchronous processing on the data, wherein the data synchronizer is an N-level synchronizer, and the value of N is determined by the average fault interval time.
8. The apparatus of claim 7, wherein the detection module comprises:
and the change detector is used for detecting whether the comparison between the data of the current period and the data of the previous period changes or not so as to determine whether the received data changes or not.
9. The apparatus of claim 8, wherein the processing module comprises:
the edge detector is used for outputting an effective value under the condition that the data are changed and triggering the data selector at the receiving clock domain side to output updated data; and under the condition that the data is not changed, outputting an invalid value, and triggering the data selector to keep the original output data.
10. The apparatus of claim 9, further comprising:
and the buffer is used for buffering the data output by the change detector after detecting whether the data is changed, wherein the buffer is an M-level buffer, and M is more than or equal to N-1.
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| CN201910578841.3A CN112148655B (en) | 2019-06-28 | 2019-06-28 | Multi-bit data clock domain crossing processing method and device |
| KR1020217035272A KR20210141739A (en) | 2019-06-28 | 2020-04-30 | Method and apparatus for processing multi-digit data in cross clock domain |
| PCT/CN2020/088019 WO2020259080A1 (en) | 2019-06-28 | 2020-04-30 | Multi-digit data cross-clock domain processing method and apparatus |
| JP2021558008A JP7360472B2 (en) | 2019-06-28 | 2020-04-30 | Multi-bit data cross-clock domain processing method and device |
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| CN112953475A (en) * | 2021-02-04 | 2021-06-11 | 中国电子科技集团公司第五十八研究所 | Multi-bit data clock domain crossing synchronization circuit |
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| CN112148655B (en) | 2023-11-17 |
| KR20210141739A (en) | 2021-11-23 |
| WO2020259080A1 (en) | 2020-12-30 |
| JP2022539485A (en) | 2022-09-12 |
| JP7360472B2 (en) | 2023-10-12 |
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