CN112131168B - Multi-chip set and control method - Google Patents

Abstract

The invention discloses a multi-chip group, which comprises a host chip and a CPU-free chip, wherein the CPU-free chip is controlled and dispatched by the host chip, and the CPU-free chip comprises: the serial-parallel conversion circuit is used for receiving and converting a serial port input signal from the host chip; the protocol conversion circuit is used for converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module of a chip; the chip debugging logic is used for realizing the debugging function of the chip. A multichip module control method comprising: the CPU-free chip receives and converts a serial port input signal from the host chip; and converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol. The invention can not only meet the functional requirements of the responsible system, but also reduce the cost, the area and the power consumption of the chip.

Description

Multi-chip set and control method

Technical Field

The invention relates to the field of chipset design, in particular to a multi-chipset and a control method.

Background

The development of integrated circuits has been in the past 40 years and has been following the regular progression indicated by morgans, now entering the deep submicron regime. Due to the demand of the information market and the development of microelectronics itself, the development of various process integration technologies and application-oriented system-on-chip (soc) mainly characterized by microfabrication (the feature size of integrated circuits is continuously reduced) is initiated. A complex electronic system, such as a cell phone chip, an artificial intelligence control chip, a memory acceleration chip, etc., can be implemented on a single integrated circuit chip. However, with the development of 5G, Artificial Intelligence (AI), cloud + and other technologies, the data volume has increased explosively. With the continuous development of integrated circuits, application scenarios are also more complex, and more complex application scenarios can be realized by a set of multiple chipsets.

As shown in fig. 1, the multi-chip set system is composed of a plurality of chips, and taking a host chip, a chip 1 and a chip n shown in the figure as an example, which respectively represent a host control chip, a video Processing chip and an AI Processing chip, in order to better save system resources and reduce system power consumption, only the host chip has a CPU (Central Processing Unit), and neither the chip 1 nor the chip n has a CPU, so how to implement uniform control and scheduling of chips without built-in CPUs such as the chip 1 and the chip n, and put higher requirements on chip design without built-in CPUs.

Disclosure of Invention

In order to solve the technical problems, the invention provides a multi-chip set and a control method, wherein a chip without a CPU is matched with a host chip for use, so that the functional requirements of a responsible system can be met, and meanwhile, the cost, the area and the power consumption of the chip can be greatly reduced due to the fact that the chip without the CPU is adopted.

In order to achieve the purpose, the invention adopts the following technical scheme:

a multi-chip module comprising a host chip and a CPU-less chip, the CPU-less chip being controlled and dispatched by the host chip, the CPU-less chip comprising:

the serial-parallel conversion circuit is used for receiving and converting a serial port input signal from the host chip;

the protocol conversion circuit is used for converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module of a chip; the chip debugging logic is used for realizing the debugging function of the chip.

Further, the serial-parallel conversion circuit includes:

the serial-parallel conversion unit is used for synchronizing the serial port input signal to the clock domain of the corresponding functional module for sampling and converting the serial port input signal into parallel data;

the parallel-serial conversion unit is used for sending the read operation data of the AMBA bus to the host chip through a serial port;

the protocol analysis unit is used for analyzing different serial port protocols in the serial-parallel conversion process and controlling data scheduling;

and the storage unit is used for storing the converted parallel data.

Further, the protocol conversion circuit includes:

the conversion control state machine is used for controlling the conversion distribution of data flow and control flow between the serial-parallel conversion circuit and the protocol conversion circuit;

the AMBA protocol conversion circuit unit is used for analyzing the data stream and converting the data stream into an AMBA protocol, and accessing an address mapping space of the chip function module through an AMBA bus and an on-chip interconnection system to realize reading and writing and control of the chip function module;

and the system debugging circuit unit is used for analyzing the control flow and completing the debugging function of the chip according to the instruction.

Further, the AMBA protocol conversion circuit unit converts the protocol into an AXI bus, an AHB bus or an APB bus through an AMBA protocol conversion control state machine.

Further, the system debug circuit unit outputs a debug signal to the system control module, and the system debug circuit unit includes:

reset request logic to output a system reset signal;

system monitoring logic for outputting system monitoring signals;

and the system debugging logic is used for outputting a system debugging signal group.

Further, the common data format of the predefined protocol comprises: packet header information, handshake information, data information, and packet trailer information; the header information is used for distinguishing AMBA protocol data flow and debugging circuit control flow.

Further, the header information retains extensible function bits.

The invention also provides a multi-chip group control method, which comprises the following steps:

the CPU-free chip receives and converts a serial port input signal from the host chip;

converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module of the chip; the chip debugging logic is used for realizing the debugging function of the chip.

Further, the receiving and converting of the serial port input signal from the host chip by the CPU-less chip includes:

synchronizing the serial port input signal to a clock domain of a corresponding functional module for sampling, converting the serial port input signal into parallel data and storing the parallel data;

sending the read operation data of the AMBA bus to a host chip through a serial port;

different serial port protocols in the serial-parallel conversion process are analyzed, and data scheduling is controlled.

Further, the converting the data packet output by the serial-parallel conversion circuit into an AMBA protocol data packet and a chip debug logic according to a predefined protocol includes:

controlling the conversion distribution of data flow and control flow between the serial-parallel conversion circuit and the protocol conversion circuit according to a predefined protocol;

analyzing the data stream and converting the data stream into an AMBA protocol, and accessing an address mapping space of the chip functional module through an AMBA bus and an on-chip interconnection system to realize reading, writing and controlling of the chip functional module;

and analyzing the control flow and finishing the debugging function of the chip according to the instruction.

The invention has the beneficial effects that:

the invention provides a CPU-free chip and a control method, which are applied to a multi-chip group application scene, are matched with a host chip for use, realize the access, control and debugging of the whole chip through the software control and scheduling of the host chip and the conversion of a serial-parallel conversion circuit and a protocol conversion circuit, and cooperatively complete the functions of the whole chip group. Through the cooperative work of the multiple chip sets, the functional requirements of a responsible system can be met, and meanwhile, the cost, the area, the power consumption and the like of the chip can be greatly reduced without a CPU chip.

Drawings

FIG. 1 is a schematic diagram of a multi-chip module system connection configuration;

FIG. 2 is a diagram of a CPU-less chip hardware architecture according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an AMBA protocol conversion circuit unit structure according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a debug circuit unit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a generic data format according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating data formats of AMBA read-write operation data packets and debug operation data packets according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating a multi-chipset control method according to an embodiment of the present invention.

Detailed Description

In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

The embodiment of the invention discloses a multi-chip group, which comprises a host chip and a CPU-free chip, wherein the CPU-free chip is controlled and dispatched by the host chip, and the CPU-free chip has a structure shown in figure 2 and comprises the following components:

a serial-parallel conversion circuit 100 for receiving and converting a serial input signal from the host chip;

the protocol conversion circuit 200 is used for converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module of a chip; the chip debugging logic is used for realizing the debugging function of the chip.

The chip also comprises a universal serial port, an on-chip interconnection unit, each functional module and the like. The universal serial port has no special requirement, can be a low-speed simple serial port such as I2C/UART/SPI and the like, and can also be a high-speed serial port such as PCIe and the like.

Specifically, the serial-parallel conversion circuit 100 shown in fig. 2 includes a serial-parallel conversion unit, a parallel-serial conversion unit, a protocol analysis unit, and a storage unit.

The serial-parallel conversion unit is used for synchronizing the serial port input signals to the clock domain of the corresponding functional module for sampling, and converting the serial port input signals into parallel data according to different protocol regulations; the parallel data is stored to an internal storage unit.

And the parallel-serial conversion unit is used for sending the read operation data of the AMBA bus to the host chip through a serial port.

The protocol analysis unit is used for analyzing different serial port protocols in the serial-parallel conversion process and realizing data scheduling meeting protocol requirements in the control serial-parallel conversion process; the parallel data packet of the serial-parallel conversion circuit may be 8-bit, 32-bit, 64-bit data, depending on the protocol.

The storage unit is used for storing the converted parallel data.

The protocol conversion circuit 200 mainly includes a conversion control state machine, an AMBA protocol conversion circuit unit, and a system debug circuit unit.

The conversion control state machine is used for controlling the conversion distribution of data flow and control flow between the serial-parallel conversion circuit and the protocol conversion circuit.

The AMBA protocol conversion circuit unit is used for analyzing the data stream and converting the data stream into an AMBA protocol, and accesses an address mapping space of the chip functional module through an AMBA bus and an on-chip interconnection system to realize reading, writing and controlling of the chip functional module, and finally achieves the purposes of controlling, configuring and debugging the internal functional module of the chip; the internal structure of the AMBA protocol conversion circuit unit is shown in fig. 3, and the AMBA protocol conversion control state machine converts the protocol into an AXI bus, an AHB bus or an APB bus according to different protocol conversion requirements through data analysis.

The system debugging circuit unit is used for analyzing the control flow and completing the debugging function of the chip according to the instruction. As shown in fig. 4, the system debug circuit unit outputs a debug signal to the system control module through data analysis, the system debug circuit unit includes a reset request logic, a system monitoring logic, and a system debug logic, and the reset request logic is used for outputting a system reset signal; the system monitoring logic is used for outputting a system monitoring signal; the system debug logic is to output a set of system debug signals.

The data analysis is performed according to a predefined software protocol. The general data format is shown in fig. 5 and includes header information, handshake information, data information, and trailer information.

According to different operation requirements, the protocol of the embodiment of the invention can flexibly combine data packets meeting functional requirements, fig. 6 shows that the AMBA read-write operation data packet includes multi-bit information in the packet header information for distinguishing whether the data stream is AMBA protocol data stream or a debugging circuit control stream, the packet header information is four bytes of address data, and then is multi-byte data information. Fig. 6 also includes the definition of the debug operation, and the packet header information can be used to distinguish the packet as the debug operation, and the packet header information is followed by 4 debug bytes.

The definition of the header information is shown in table 1, and the definition of the byte information is shown in table 2.

Table 1 header information table

TABLE 2 byte information Table

As shown in fig. 7, an embodiment of the present invention further provides a multi-chip set control method, including:

the CPU-free chip receives and converts a serial port input signal from the host chip;

converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module of a chip; the chip debugging logic is used for realizing the debugging function of the chip.

The no CPU chip receives and converts the serial port input signal from the host computer chip, including:

synchronizing the serial port input signal to a clock domain of a corresponding functional module for sampling, converting the serial port input signal into parallel data and storing the parallel data;

sending the read operation data of the AMBA bus to a host chip through a serial port;

different serial port protocols in the serial-parallel conversion process are analyzed, and data scheduling is controlled.

The converting the data packet output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to the predefined protocol comprises the following steps:

controlling conversion distribution of data flow and control flow between the serial-parallel conversion circuit and the protocol conversion circuit according to a predefined protocol;

analyzing the data stream and converting the data stream into an AMBA protocol, and accessing an address mapping space of the chip functional module through an AMBA bus and an on-chip interconnection system to realize reading, writing and controlling of the chip functional module;

and analyzing the control flow, and finishing the debugging function of the chip according to the instruction.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the invention, various modifications or changes which can be made by a person skilled in the art without creative efforts are still within the protection scope of the invention.

Claims (8)

1. A multi-chip set comprising a host chip and a CPU-less chip, the CPU-less chip being controlled and dispatched by the host chip, the CPU-less chip comprising:

the serial-parallel conversion circuit is used for receiving and converting a serial port input signal from the host chip;

the protocol conversion circuit is used for converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module without a CPU chip; the chip debugging logic is used for realizing the debugging function of a CPU-free chip;

the protocol conversion circuit includes:

the conversion control state machine is used for controlling the conversion distribution of data flow and control flow between the serial-parallel conversion circuit and the protocol conversion circuit;

the AMBA protocol conversion circuit unit is used for analyzing the data stream and converting the data stream into an AMBA protocol, and accessing an address mapping space of the CPU-free chip functional module through an AMBA bus and an on-chip interconnection system to realize reading, writing and controlling of the CPU-free chip functional module;

and the system debugging circuit unit is used for analyzing the control flow and completing the debugging function of the CPU-free chip according to the instruction.

2. The multi-chip set of claim 1, wherein the serial-to-parallel conversion circuit comprises:

the serial-parallel conversion unit is used for synchronizing the serial port input signal to the clock domain of the corresponding functional module for sampling and converting the serial port input signal into parallel data;

the parallel-serial conversion unit is used for sending the read operation data of the AMBA bus to the host chip through a serial port;

the protocol analysis unit is used for analyzing different serial port protocols in the serial-parallel conversion process and controlling data scheduling;

and the storage unit is used for storing the converted parallel data.

3. The multichip stack of claim 1, wherein the AMBA protocol conversion circuit unit converts protocols to AXI bus, AHB bus, or APB bus through an AMBA protocol conversion control state machine.

4. The multichip module according to claim 1, wherein the system debug circuit unit outputs a debug signal to the system control module, and the system debug circuit unit comprises:

reset request logic to output a system reset signal;

a system monitoring logic for outputting a system monitoring signal;

and the system debugging logic is used for outputting a system debugging signal group.

5. The multichip module according to claim 1, wherein the generic data format of the predefined protocol comprises: packet header information, handshake information, data information, and packet trailer information; the header information is used for distinguishing AMBA protocol data flow and debugging circuit control flow.

6. The multi-chipset of claim 5, wherein the header information holds extensible function bits.

7. A multi-chip set control method, wherein a CPU-less chip is controlled and scheduled by a host chip, comprising:

the CPU-free chip receives and converts a serial port input signal from the host chip;

converting the data packet converted and output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to a predefined protocol; the AMBA protocol data packet is used for reading, writing and controlling a functional module without a CPU chip; the chip debugging logic is used for realizing the debugging function of a CPU-free chip;

the converting the data packet output by the serial-parallel conversion circuit into an AMBA protocol data packet and chip debugging logic according to the predefined protocol comprises the following steps:

controlling conversion distribution of data flow and control flow between the serial-parallel conversion circuit and the protocol conversion circuit according to a predefined protocol;

analyzing the data stream and converting the data stream into an AMBA protocol, and accessing an address mapping space of the CPU-free chip functional module through an AMBA bus and an on-chip interconnection system to realize reading, writing and controlling of the CPU-free chip functional module;

and analyzing the control flow, and completing the debugging function without the CPU chip according to the instruction.

8. The multi-chipset control method of claim 7 wherein the CPU-less chip receiving and converting serial input signals from the host chip comprises:

synchronizing the serial port input signal to a clock domain of a corresponding functional module for sampling, converting the serial port input signal into parallel data and storing the parallel data;

sending the read operation data of the AMBA bus to a host chip through a serial port;

different serial port protocols in the serial-parallel conversion process are analyzed, and data scheduling is controlled.

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