CN112114615B - Cross-clock domain data synchronization circuit, method and equipment - Google Patents
Cross-clock domain data synchronization circuit, method and equipment Download PDFInfo
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Abstract
The application discloses a cross-clock domain data synchronization circuit, a method and a device, wherein the circuit comprises: the data slicing module is used for slicing the data to be synchronized according to the bit width of the data to be synchronized to obtain a plurality of data slices and generating a plurality of data coding modules and data synchronization modules; the data coding module is used for coding the input data slice to obtain a coded data slice; the data synchronization module is used for synchronizing the clock domain crossing of the coded data slice to obtain a synchronous data slice; and the data decoding module is used for carrying out continuity confirmation on the plurality of synchronous data pieces, and decoding and integrating the plurality of synchronous data pieces after the continuity is confirmed to be complete. According to the data synchronization method and device, data fragmentation can be carried out on the data to be synchronized, corresponding processing is carried out through the corresponding data encoding module and the data synchronization module, decoding integration is completed through the data decoding module, cross-clock-domain synchronization of the data is completed, and the speed and reliability of the data when the data are synchronized across clock domains are increased.
Description
Technical Field
The present application relates to the field of data synchronization, and in particular, to a clock domain crossing data synchronization circuit, method, and device.
Background
At present, the electronic information technology industry develops rapidly, the performance requirement of a special chip is higher and higher, the complexity of an integrated circuit is exponentially increased while the integrated circuit manufacturing technology is rapidly improved, the research and development production period is greatly prolonged, and the electronic information technology industry cannot well adapt to changeable market requirements. And a large-scale field programmable logic device (FPGA) provides a method capable of flexibly realizing a circuit, and the contradiction between the product research and development period and the product performance is balanced.
However, in the prior art, due to the complexity of the FPGA design function rising, it is often necessary to implement cross-clock domain synchronization of large-bit-width high-speed data, and a large-bit-width First-in First-out (FIFO) queue is directly used for data synchronization, which often cannot implement high-frequency clock reading and writing due to FPGA resources, architecture, and the like, so that the data cross-clock domain synchronization portion becomes a performance bottleneck of system design.
Disclosure of Invention
In order to solve the above problem, the present application provides a cross-clock domain data synchronization circuit, which includes a data slicing module, a data encoding module, a data synchronization module connected to the data encoding module, and a data decoding module connected to the data synchronization module; the data slicing module is used for slicing the data to be synchronized according to the bit width of the data to be synchronized to obtain a plurality of data slices and generating a plurality of data coding modules and data synchronization modules; the data coding module is used for coding the input data slice to obtain a coded data slice; the data synchronization module is used for carrying out clock domain crossing synchronization on the coded data slices to obtain synchronous data slices; and the data decoding module is used for carrying out continuity confirmation on the plurality of synchronous data slices and decoding and integrating the plurality of synchronous data slices after the continuity is confirmed to be complete.
In one example, the data slicing module calculates a calculated value according to a bit width of data to be synchronized and a unit bit width of each preset data slice; and performing data slicing on the data to be synchronized to obtain data slices of the calculated values, and generating the data encoding modules and the data synchronization modules of the calculated values, wherein each data encoding module is provided with one-to-one corresponding data synchronization module for processing one data slice.
In one example, the bit width of the data to be synchronized is not less than 128 bits, and the unit bit width is 64 bits.
In one example, the data synchronization module is further configured to send the synchronized data slice and the corresponding data slice identifier to the data decoding module; the data decoding module is used for confirming the continuity of a plurality of synchronous data slices based on the data slice identification.
In one example, a corresponding FIFO is arranged in each data synchronization module, and the bit width of the FIFO is not less than the sum of the unit bit width and the bit width corresponding to the data slice identifier.
In one example, the data decoding module is further configured to report an error and discard data of the current frame after confirming that the continuity is incomplete.
In one example, the data encoding module encodes the input piece of data using a one-hot code or a gray code.
In one example, the data synchronization module is further configured to buffer data.
On the other hand, the present application also provides a cross-clock domain data synchronization method, which applies the circuit according to any of the above examples to perform cross-clock domain data synchronization, and the method includes: performing data fragmentation on the data to be synchronized through a data fragmentation module according to the bit width of the data to be synchronized to obtain a plurality of data fragments, generating a plurality of data coding modules and a data synchronization module, and respectively sending the plurality of data fragments to the plurality of data coding modules; coding the input data slice through the data coding module to obtain a coded data slice, and sending the coded data slice to the corresponding data synchronization module; performing clock domain crossing synchronization on the coded data slices through the data synchronization module to obtain synchronous data slices, and sending the synchronous data slices to a data decoding module; and the data decoding module is used for confirming the continuity of the plurality of synchronous data slices and decoding and integrating the plurality of synchronous data slices after the completeness of the continuity is confirmed.
On the other hand, the present application also provides a cross-clock domain data synchronization device, which is characterized in that a circuit according to any one of the above examples is applied to perform cross-clock domain data synchronization, and the device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to: performing data fragmentation on the data to be synchronized through a data fragmentation module according to the bit width of the data to be synchronized to obtain a plurality of data fragments, generating a plurality of data coding modules and a data synchronization module, and respectively sending the plurality of data fragments to the plurality of data coding modules; the data encoding module is used for encoding the input data slice to obtain an encoded data slice, and the encoded data slice is sent to the corresponding data synchronization module; performing clock domain crossing synchronization on the coded data slice through the data synchronization module to obtain a synchronous data slice, and sending the synchronous data slice to a data decoding module; and the data decoding module is used for confirming the continuity of the plurality of synchronous data slices, and decoding and integrating the plurality of synchronous data slices after the completeness of the continuity is confirmed.
The synchronous circuit provided by the application can bring the following beneficial effects:
according to the data synchronization method and device, the design performance bottleneck caused by the fact that a single large-bit-width FIFO is used for data synchronization in the existing FPGA design can be overcome, data to be synchronized can be subjected to data slicing, corresponding processing is carried out through the corresponding data encoding module and the data synchronization module, decoding integration is completed through the data decoding module, cross-clock-domain synchronization of data is completed, and the speed and reliability of the data when the data is synchronized across clock domains are increased.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a clock domain crossing data synchronization circuit according to an embodiment of the present application;
FIG. 2 is a schematic flow chart illustrating a cross-clock domain data synchronization method according to an embodiment of the present application;
fig. 3 is a schematic diagram of a device for data synchronization across clock domains in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present application provides a clock domain crossing data synchronization circuit, where the synchronization circuit includes a data slicing module FPM, a data encoding module BMM, a data synchronization module FRM, and a data decoding module JMM.
Specifically, each synchronization circuit may generally include a data fragmentation module, where the data fragmentation module is configured to receive data to be synchronized (in this embodiment, the data is referred to as data to be synchronized), and perform data fragmentation on the data to be synchronized to obtain a plurality of data fragments. And the data slicing module can also generate a plurality of data coding modules and data synchronization modules for carrying out corresponding processing on the data slices. The data fragmentation refers to a process of dividing data to be identified according to a preset rule so as to obtain multiple groups of data, and the data to be synchronized in the embodiment of the present application refers to data of one frame, and correspondingly, the data fragmentation is also data fragmentation performed on the frame of data to be synchronized. The number of the data coding modules and the number of the data synchronization modules generated by the data slicing module are the same and are corresponding to the number of the data slices, and each data coding module is provided with a data decoding module which is in one-to-one correspondence and is used for processing one data slice.
In each synchronous circuit, the number of the data encoding modules is usually a plurality, i.e. at least two. After the data coding module receives the data slice sent by the data slicing module, the data coding module may code the related data in the data slice, and the coded data slice is called a coded data slice. When encoding data, the data may be encoded using a unique hot code or a gray code, which is not described herein again.
After the data encoding module encodes the data slice, the encoded data slice can be written into the corresponding data synchronization module. Each data coding module is connected with a data synchronization module in one-to-one correspondence, and after the data synchronization module receives a coded data slice, the coded data slice can be synchronized across clock domains, and the data slice after synchronization can be referred to as a synchronous data slice. After the data synchronization module completes the cross-clock domain synchronization of the data slice, the synchronous data slice can be sent to the data decoding module. In addition, the data synchronization module can perform data buffering besides data synchronization, and the data buffering, namely the Cache technology, is essentially matched with a speed difference.
In general, each synchronization circuit also includes only one data decoding module, and the data decoding module is connected to the plurality of data synchronization modules, and after receiving the synchronization data pieces sent by all the data synchronization modules, the continuity of the synchronization data pieces can be confirmed. If the continuity is determined to be complete and has no problem, namely no frame loss is generated, the synchronous data slices can be decoded and integrated into complete data, and then the clock domain crossing synchronization is completed. Of course, if the continuity is not complete during the continuity check, an error may be reported and the data of the current frame may be discarded, and the data of the next frame may be synchronized.
In an embodiment, before the data fragmentation module performs fragmentation on the data, the number of the data fragments obtained by the current required fragmentation is calculated and determined. And when the number is calculated, the calculation can be carried out based on the bit width of the data to be synchronized and the preset synchronization precision level. Wherein different synchronization precision levels correspond to different unit bit widths. Since the synchronization circuit in the embodiment of the present application mainly aims at the large-bit-width data, and in general, data with a bit width not less than 128 bits is called large-bit-width data, when a unit bit width is set, the unit bit width can be set to 64 bits, which can meet the slicing requirement of the large-bit-width data, and the unit bit width is explained as 64 bits in the following. And setting the bit width of the data to be synchronized as N, and carrying out data fragmentation on each frame of data by taking 64 bits as a unit. When N is an integer multiple of 64, data fragmentation can be performed to obtain N/64 data fragments. When N is not an integer multiple of 64, [ N/64] +1 data pieces can be obtained. The number of the generated data encoding modules and data synchronization modules is the same as the number of the data pieces, and is not described herein again.
In one embodiment, when the data synchronization module sends the synchronization data slice to the data decoding module, in addition to sending the synchronization data slice, a corresponding data slice identifier needs to be sent to the data decoding module, and at this time, the data decoding module can perform continuity confirmation on a plurality of received synchronization data slices according to the identifier.
Specifically, each data synchronization module is provided with a corresponding FIFO for data synchronization. If the bit width of the FIFO is set too high, resource waste may be caused, and if the bit width of the FIFO is set too low, the data synchronization function may not be performed, so when the bit width of the FIFO is set, the bit width may be set to be not less than the sum of the unit bit width and the bit width corresponding to the slice identifier to ensure that the data synchronization function may be performed, and when the bit width is set, the bit width may also be set to be the sum of the unit bit width and the bit width corresponding to the slice identifier, and a difference value between the unit bit width and the bit width before the FIFO is lower than a preset threshold value. Taking the unit bit width of 64 bits as an example, since the bit width of the large-bit-width data (to-be-identified data) is usually 512 bits at the highest, at this time, the large-bit-width data needs to be divided into 8 data pieces, when the 8 data pieces are represented by binary numbers, the data piece identification needs a bit width of at least 3 bits, and in order to prevent an unexpected situation, the bit width of the FIFO can be set to 68-70 bits, which can almost satisfy the to-be-identified data with any bit width, and does not cause too much resource waste.
As shown in fig. 2, an embodiment of the present application further provides a cross-clock domain data synchronization method, where the synchronization circuit described in any of the above embodiments is applied to perform cross-clock domain data synchronization, and the method includes:
s201, performing data slicing on the data to be synchronized through a data slicing module according to the bit width of the data to be synchronized to obtain a plurality of data slices, generating a plurality of data coding modules and a data synchronization module, and respectively sending the plurality of data slices to the plurality of data coding modules.
S202, the data coding module is used for coding the input data slice to obtain a coded data slice, and the coded data slice is sent to the corresponding data synchronization module.
S203, performing clock domain crossing synchronization on the coded data slice through the data synchronization module to obtain a synchronous data slice, and sending the synchronous data slice to a data decoding module.
S204, the data decoding module is used for confirming the continuity of the plurality of synchronous data slices, and after the continuity is confirmed to be complete, the plurality of synchronous data slices are decoded and integrated.
The synchronization method in the embodiment of the present application is similar to the related contents in the above-mentioned synchronization circuit, and thus will not be described here.
As shown in fig. 3, an embodiment of the present application further provides a cross-clock-domain data synchronization device, where the synchronization circuit described in any of the above embodiments is applied to perform cross-clock-domain data synchronization, and the device includes:
at least one processor; and (c) a second step of,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to cause the at least one processor to perform:
performing data fragmentation on the data to be synchronized through a data fragmentation module according to the bit width of the data to be synchronized to obtain a plurality of data fragments, generating a plurality of data coding modules and a data synchronization module, and respectively sending the plurality of data fragments to the plurality of data coding modules;
coding the input data slice through the data coding module to obtain a coded data slice, and sending the coded data slice to the corresponding data synchronization module;
performing clock domain crossing synchronization on the coded data slices through the data synchronization module to obtain synchronous data slices, and sending the synchronous data slices to a data decoding module;
and the data decoding module is used for confirming the continuity of the plurality of synchronous data slices and decoding and integrating the plurality of synchronous data slices after the completeness of the continuity is confirmed.
After data to be synchronized is sliced into a plurality of data slices, a corresponding number of data coding modules and data synchronization modules can be generated, and each data code is generated.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the device and media embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference may be made to some descriptions of the method embodiments for relevant points.
The device and the medium provided by the embodiment of the application correspond to the method one to one, so the device and the medium also have the similar beneficial technical effects as the corresponding method, and the beneficial technical effects of the method are explained in detail above, so the beneficial technical effects of the device and the medium are not repeated herein.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises that element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present application shall be included in the scope of the claims of the present application.
Claims (9)
1. A clock domain crossing data synchronization circuit is characterized by comprising a data slicing module, a data coding module, a data synchronization module connected with the data coding module and a data decoding module connected with the data synchronization module;
the data fragmentation module calculates to obtain a calculated value according to the bit width of the data to be synchronized and the unit bit width of each preset data fragment; performing data slicing on the data to be synchronized to obtain a data slice of the calculated value, and generating the data encoding module and the data synchronization module of the calculated value, wherein for each data encoding module, the data synchronization module in one-to-one correspondence exists and is used for processing one data slice;
the data coding module is used for coding the input data slice to obtain a coded data slice; each data coding module is connected with the data synchronization modules in one-to-one correspondence, and after the data synchronization modules receive coded data slices, the coded data slices are synchronized across clock domains;
the data synchronization module is used for carrying out clock domain crossing synchronization on the coded data slices to obtain synchronous data slices;
and the data decoding module is used for carrying out continuity confirmation on the plurality of synchronous data slices and decoding and integrating the plurality of synchronous data slices after the continuity is confirmed to be complete.
2. The circuit according to claim 1, wherein the bit width of the data to be synchronized is not less than 128 bits, and the unit bit width is 64 bits.
3. The circuit of claim 1, wherein the data synchronization module is further configured to send the synchronized data slice and the corresponding data slice identifier to the data decoding module;
the data decoding module is used for confirming the continuity of a plurality of synchronous data slices based on the data slice identification pairs.
4. The circuit according to claim 3, wherein each data synchronization module is provided with a corresponding FIFO, and the bit width of the FIFO is not less than the sum of the unit bit width and the bit width corresponding to the slice identifier.
5. The circuit of claim 1, wherein the data decoding module is further configured to report an error and discard the data of the current frame after confirming the incomplete continuity.
6. The circuit of claim 1, wherein the data encoding module encodes the input data slice using a one-hot code or a gray code.
7. The circuit of claim 1, wherein the data synchronization module is further configured to buffer data.
8. A method for cross-clock-domain data synchronization, wherein the circuit of any one of claims 1-7 is applied to perform cross-clock-domain data synchronization, the method comprising:
calculating to obtain a calculated value according to the bit width of the data to be synchronized and the unit bit width of each preset data slice through a data slicing module; performing data slicing on the data to be synchronized to obtain a data slice of the calculated value, and generating the data encoding module and the data synchronization module of the calculated value, wherein for each data encoding module, the data synchronization module in one-to-one correspondence exists and is used for processing one data slice;
the data encoding module is used for encoding the input data slice to obtain an encoded data slice, and the encoded data slice is sent to the corresponding data synchronization module; each data coding module is connected with a data synchronization module in one-to-one correspondence, and after the data synchronization module receives a coded data slice, the coded data slice is synchronized across clock domains;
performing clock domain crossing synchronization on the coded data slices through the data synchronization module to obtain synchronous data slices, and sending the synchronous data slices to a data decoding module;
and the data decoding module is used for confirming the continuity of the plurality of synchronous data slices, and decoding and integrating the plurality of synchronous data slices after the completeness of the continuity is confirmed.
9. A cross-clock-domain data synchronization device, characterized in that a circuit according to any of claims 1-7 is applied to perform cross-clock-domain data synchronization, the device comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to cause the at least one processor to perform:
calculating to obtain a calculated value according to the bit width of the data to be synchronized and the unit bit width of each preset data slice through a data slicing module; performing data slicing on the data to be synchronized to obtain a data slice of the calculated value, and generating the data encoding module and the data synchronization module of the calculated value, wherein for each data encoding module, the data synchronization module in one-to-one correspondence exists and is used for processing one data slice;
coding the input data slice through the data coding module to obtain a coded data slice, and sending the coded data slice to the corresponding data synchronization module; each data coding module is connected with one-to-one corresponding data synchronization module, and after the data synchronization module receives the coded data slices, the coded data slices are synchronized across clock domains;
performing clock domain crossing synchronization on the coded data slices through the data synchronization module to obtain synchronous data slices, and sending the synchronous data slices to a data decoding module;
and the data decoding module is used for confirming the continuity of the plurality of synchronous data slices, and decoding and integrating the plurality of synchronous data slices after the completeness of the continuity is confirmed.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002097646A2 (en) * | 2001-05-31 | 2002-12-05 | Koninklijke Philips Electronics N.V. | Parallel data communication having skew intolerant data groups |
| CN107656886A (en) * | 2017-09-30 | 2018-02-02 | 中国科学院长春光学精密机械与物理研究所 | A kind of cross clock domain signal processing circuit and its processing method |
| CN109525365A (en) * | 2018-11-06 | 2019-03-26 | 哈尔滨工业大学（深圳） | A kind of channel coding and modulating system and method passed applied to unmanned plane figure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7085950B2 (en) * | 2001-09-28 | 2006-08-01 | Koninklijke Philips Electronics N.V. | Parallel data communication realignment of data sent in multiple groups |
| CN101692218A (en) * | 2009-09-27 | 2010-04-07 | 上海大学 | High-speed data transmission method |
| CN102012876B (en) * | 2010-11-19 | 2015-09-16 | 中兴通讯股份有限公司 | The write of large bit wide data, read method and controller |
| CN110134365B (en) * | 2019-05-21 | 2022-10-11 | 合肥工业大学 | Method and device for reading FIFO (first in first out) in parallel by multiple channels |
| CN111580595A (en) * | 2020-05-08 | 2020-08-25 | 济南浪潮高新科技投资发展有限公司 | System for signal synchronization in related derivative clock domains of FPGA (field programmable Gate array) |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002097646A2 (en) * | 2001-05-31 | 2002-12-05 | Koninklijke Philips Electronics N.V. | Parallel data communication having skew intolerant data groups |
| CN107656886A (en) * | 2017-09-30 | 2018-02-02 | 中国科学院长春光学精密机械与物理研究所 | A kind of cross clock domain signal processing circuit and its processing method |
| CN109525365A (en) * | 2018-11-06 | 2019-03-26 | 哈尔滨工业大学（深圳） | A kind of channel coding and modulating system and method passed applied to unmanned plane figure |
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