CN112084063B - 100Gbps Ethernet filtering method - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/02—Capturing of monitoring data
- H04L43/028—Capturing of monitoring data by filtering
Abstract
The invention discloses a 100Gbps Ethernet filtering method, which comprises a field programmable gate array, an upper computer and a memory, wherein a CMAC-IP core is arranged in the field programmable gate array, and a filtering state machine is constructed in the field programmable gate array. The field programmable gate array and the memory are connected with the upper computer through standard electric interfaces. The Ethernet data flow enters a CMAC-IP core at the test rate of 100Gbps, 4 128-bit data channels are arranged in the CMAC-IP core, and the Ethernet data flow is sequentially circularly output in the 4 128-bit data channels; the data output by the data channel enters a filtering state machine for filtering; the filtered data is stored in a memory and is checked by a host computer. The 100Gbps Ethernet filtering method provided by the invention comprises a filtering method based on standard Ethernet frames, a user-defined graph filtering method and an error code type filtering method, can realize effective data screening in 100Gbps high-speed, multi-protocol and large-flow Ethernet data, and improves the efficiency of extracting useful information.
Description
Technical Field
The invention relates to the field of Ethernet data packet filtering at a test rate of 100Gbps, in particular to a 100Gbps Ethernet filtering method.
Background
With the rapid development of information technology, ultra-high speed, ultra-large capacity and ultra-wide bandwidth become the development trend of the wired communication future. Currently, industry parties including telecom operators, equipment vendors, etc. are actively pushing application deployment of 100G technology. The Ethernet tester is also developed rapidly in recent years, and shows the trend that the testing speed is continuously improved, the capability of complex testing for application is stronger and stronger, and the like. The research of the high-speed network protocol test mainly realizes the technology and implementation means of high-speed protocol detection integration, automatic test and the like, and directly aims at the information highly concerned by the user to obtain the evaluation result. Because of the limitation of core technologies such as high interface speed, large data flow, complex and various protocols, the domestic high-speed Ethernet tester has the conditions of low test speed, incomplete protocol test, lack of applicability information test, filtering and screening capability and the like, and needs to be comprehensively and greatly improved.
At present, the testing speed of the mainstream domestic instruments is mainly concentrated on giga and tera, the development of 100G network testers is in progress, and the development of the Ethernet latest technology is difficult to meet. Also, how to achieve efficient data screening from 100Gbps high rate, multiprotocol, large traffic data is a new challenge.
Disclosure of Invention
The invention aims to provide a 100Gbps Ethernet filtering method, which realizes the function of screening Ethernet frames interested by a user by setting filtering conditions by the user and improves the efficiency of extracting useful information.
The invention adopts the following technical scheme:
the 100Gbps Ethernet filtering method comprises a field programmable gate array, an upper computer and a memory, wherein a CMAC-IP core is arranged in the field programmable gate array, and a filtering state machine is constructed in the field programmable gate array; the field programmable gate array and the memory are connected with the upper computer through standard electrical interfaces;
the filtering method comprises the following steps:
step 1: the Ethernet data flow enters a CMAC-IP core at the test rate of 100Gbps, 4 128-bit data channels are arranged in the CMAC-IP core, and the Ethernet data flow is sequentially circularly output in the 4 128-bit data channels;
step 2: the data output by the data channel enters a filtering state machine for filtering;
step 3: the filtered data is stored in a memory and is checked by a host computer.
Preferably, the filtering process based on standard ethernet frames:
the filtering state machine constructed in the field programmable gate array is a tree state machine which is used for making the Ethernet protocol, and the tree state machine is used for classifying all the Ethernet protocols in a layering way;
the step 2 specifically comprises the following steps:
step 2.1: the filtering state machine firstly filters the basic protocol type of the frame head, then sequentially determines specific protocols step by step, and stores the protocol and reads the protocol by a host computer after finding out the protocol meeting the conditions;
step 2.2: since the start position of the frame may occur in any one of 4 128-bit data lanes, 4 128-bit data lanes including lane 0, lane 1, lane 2 and lane 3, and if the start position is in lane 0, then subsequent data occurs in the sequence of lane 1, lane 2, lane 3, lane 0, … …; the filtering state machine judges the data channel in which the starting position of the frame is located, the upper computer reads the stored protocol to capture the data flow in the data channel in sequence, and the captured frame is stored in the memory.
Preferably, the user customizes the filtering process of the graph:
the filtering state machine constructed in the field programmable gate array is a self-defined graph filtering state machine, the self-defined graph filtering state machine comprises a base address, an offset, a graph and a mask, the base address is a reference position of filtering conditions, the offset is an integer multiple byte offset relative to the base address, the graph is information required to be searched by a user, the length can reach 16 bytes, the mask corresponds to the graph, the length is also 16 bytes, when the mask bit is equal to 1, the corresponding graph bit is valid, and when the mask bit is zero, the corresponding bit is invalid;
the step 2 specifically comprises the following steps:
step 2.1: the user inputs the base address, the offset, the graph and the mask through the upper computer, and the mapping command of the graph filtering state machine is customized;
step 2.2: since the start position of data may occur in any one of 4 128-bit data lanes, 4 128-bit data lanes include lane 0, lane 1, lane 2 and lane 3, and if the start position is in lane 0, then subsequent data occurs in lane 1, lane 2, lane 3, lane 0, … … in sequence; the user-defined graph filtering state machine judges the data channel in which the starting position of the data is, the user-defined graph filtering state machine sequentially performs sliding comparison on the data flow in the data channel through the base address, the offset and the graph and the mask, and when the filtering condition is met, the data is captured and stored in the memory.
Preferably, the filtering process of the error code type:
the filtering state machine constructed in the field programmable gate array is an error code type filtering state machine, wherein FCS error frame filtering, undersize short frame filtering, IPv4 check and error frame filtering are arranged in the error code type filtering state machine;
when filtering FCS error frames, step 2 specifically includes:
the error code type filtering state machine adopts a 32-bit cyclic redundancy check algorithm, when the enabling signal RX_ENAOUT and the termination signal RX_EOPOUT of the data channel are 1 at the same time, namely the current time sequence is the end of the current frame, the current frame is temporarily stored in the dual-port RAM, the last 32 bits are check codes of the current frame, if the 32-bit check codes calculated by the error code type filtering state machine are different from the original FCS of the current frame, the current frame is in error, namely the FCS is in error, and the error code type filtering state machine further starts to read data from the frame heads in the dual-port RAM and sequentially writes the data into the memory;
when the short frame is filtered, the step 2 specifically comprises:
the IEEE802.3 standard specifies that ethernet frames are at a minimum of 64 bytes, and when they are less than this length, the packet is in error, i.e. a short frame, in the CMAC-IP core, there are 4 128-bit data channels, i.e. 64 bytes, and the error type filtering state machine always detects the start and end of the frame, after the current frame header appears, the frame end must appear at the earliest in the last channel of the next valid clock edge, if the frame end appears in advance, the frame length must be less than 64 bytes, i.e. a short frame error, the error type filtering state machine relocates to the frame header of this short frame, and then the whole frame is written from the dual-port RAM into memory;
when filtering the IPv4 checksum error frame, the step 2 specifically includes:
the error type filtering state machine first locates the IP datagram start position, the header checksum length is the inverse of the 16-bit accumulated sum, and at the 10 th byte position relative to the IP datagram Wen Toubu, and the 6-byte source mac+2-byte type+10-byte IP header=24 bytes relative to the offset position of the MAC frame, so the checksum corresponds to the 6 th and 7 th bytes of the next data lane of the data lane where the data starts, and when the checksum is incorrect, the error type filtering state machine captures the frame and writes it to memory.
The invention has the beneficial effects that:
the 100Gbps Ethernet filtering method provided by the invention comprises a filtering method based on standard Ethernet frames, a user-defined graph filtering method and an error code type filtering method, can realize effective data screening in 100Gbps high-speed, multi-protocol and large-flow Ethernet data, and improves the efficiency of extracting useful information.
Drawings
FIG. 1 is a schematic diagram of a tree state machine.
Fig. 2 is a basic schematic diagram of fixed-length 64 byte IP frame filtering.
FIG. 3 is a basic schematic diagram of user-defined graphical filtering.
Fig. 4 is a basic schematic of a sliding window.
Fig. 5 is a basic diagram of error type filtering.
Detailed Description
The following description of the embodiments of the invention will be given with reference to the accompanying drawings and examples:
ethernet testers typically include two basic functions, transmit and receive. The reception function includes full and partial reception. The total reception is that the tester receives and stores all the data, while the partial reception is that of filtering all the received data, which is usually selected according to the requirements. In filtering reception, trigger reception is a special filtering, which is triggered according to a user set condition to further grasp a data packet, and generally includes a start trigger, an intermediate trigger, a tail trigger, and the like. The filtering reception conditions of the ethernet tester generally include a source MAC address, a destination MAC address, a source IP address, a destination IP address, a graphics trigger, frames of different kinds of bit errors, and the like.
Referring to fig. 1 to 5, a 100Gbps ethernet filtering method includes a field programmable gate array, an upper computer and a memory, wherein the field programmable gate array has a CMAC-IP core, and a filtering state machine is built in the field programmable gate array. The field programmable gate array and the memory are connected with the upper computer through standard electric interfaces. The memory is DDR4 memory.
The field programmable gate array is a high-speed FPGA, ultraScale of an UltraScale series as a programmable hardware platform, has large-scale distributed hardware resources, and has the characteristics of high speed, short development period, good parallel performance and the like, and is very suitable for processing high-speed data with 100 Gbps. In addition, the CMAC-IP core of the product supports the international standards IEEE std 802.3-2012CAUI-10 and CAUI-4, so that the requirements of the invention can be met.
The CMAC IP core includes high speed transceivers, RS-FEC (Reed-Solomon Forward Error Correction), transceiver PCS (Physical Coding Sublayer), control state machines, local bus LBUS (Local BUS), and so on. The LBUS comprises a sending module and a receiving module, and the receiving interface comprises 4 128 bit data channels RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2 and RX_DATAOUT3, wherein the received data sequentially appear in a channel 0, channel 1, channel 2 and channel 3 channel circulation mode. Each channel includes an enable, a data start, a data end, an error indication, a last byte empty indication, etc.
The filtering method comprises the following steps:
step 1: the Ethernet data stream enters the CMAC-IP core at the test rate of 100Gbps, 4 128-bit data channels are arranged in the CMAC-IP core, the 4 128-bit data channels comprise a channel 0, a channel 1, a channel 2 and a channel 3, and the Ethernet data stream is sequentially circularly output in the 4 128-bit data channels.
Step 2: the data output by the data channel enters a filtering state machine for filtering;
step 3: the filtered data is stored in a memory and is checked by a host computer.
The invention provides a filtering method based on a standard Ethernet frame, a user-defined graph filtering method and an error code type filtering method.
Example 1
Since the CMAC-IP core has automatically processed the PREAMBLE and SFD (Start-of-Frame delay), the data received by the LBUS is from the destination MAC address to the FCS portion. The information relative position of the frame header indicates that it has been fixed according to the ethernet standard, so the relative position in the CMAC-IP core data lane has also been determined.
Filtering process based on standard Ethernet frame:
the filtering state machine constructed in the field programmable gate array is a tree-type state machine which is used for classifying all the Ethernet protocols in a layered manner, as shown in fig. 1.
The step 2 specifically comprises the following steps:
step 2.1: the filtering state machine firstly filters the basic protocol type of the frame head, then sequentially determines specific protocols step by step, and stores the protocol and reads the protocol by a host computer after finding out the protocol meeting the conditions;
step 2.2: since the start position of a frame may occur in any one of 4 128-bit data lanes, 4 128-bit data lanes including lane 0, lane 1, lane 2 and lane 3, and assuming that the start position is in lane 0, then subsequent data occurs in the sequence of lane 1, lane 2, lane 3, lanes 0, … …, and the principle of the start position of a frame occurring first in one of the other 3 lanes is similar. The filtering state machine judges the data channel in which the starting position of the frame is located, the upper computer reads the stored protocol to capture the data flow in the data channel in sequence, and the captured frame is stored in the memory.
Because Of the wide variety Of ethernet protocols, in the following, taking a common 64 byte IP frame as an example, it is assumed that the data Start position occurs on channel 0, that is, the enable signal rx_enaout= 1, and the Start signal rx_sopout 1= 1, SOF (Start-Of-Packet) data occurs on channel rx_dataout0. The correspondence of the four LBUS channels is shown in tables 1 to 4.
TABLE 1 LBUS channel 0 correspondence
TABLE 2 LBUS channel 1 correspondence
TABLE 3 LBUS channel 2 correspondence
TABLE 4 LBUS channel 3 correspondence
Fig. 2 illustrates the basic principle of the hardware filtering process with a 64 byte IP frame as an example, and the ethernet other protocol implementation principle is similar.
Example 2
To be independent of standard ethernet frame-based, a user may customize some key patterns to filter the received data.
Filtering process of user-defined graph:
the filtering state machine constructed in the field programmable gate array is a self-defined graph filtering state machine, the self-defined graph filtering state machine comprises a base Address, an offset, a graph and a mask, the base Address is a reference position of filtering conditions and can be Top of Frame, top of VLAN, top of IPv4 Header, top of TCP Header, top of UDP Header, IP Address and the like, the offset is an integer multiple byte offset relative to the base Address, the graph is information required to be searched by a user, the length can reach 16 bytes, the mask corresponds to the graph, the length is 16 bytes, when the mask bit is equal to 1, the corresponding graph bit is valid, and when the mask bit is zero, the corresponding graph bit is invalid;
the step 2 specifically comprises the following steps:
step 2.1: the user inputs the base address, the offset, the graph and the mask through the upper computer, and the mapping command of the graph filtering state machine is customized;
step 2.2: since the start position of data may occur in any one of 4 128-bit data lanes, 4 128-bit data lanes include lane 0, lane 1, lane 2 and lane 3, and if the start position is in lane 0, then subsequent data occurs in lane 1, lane 2, lane 3, lane 0, … … in sequence; the user-defined graph filtering state machine judges the data channel in which the starting position of the data is, the user-defined graph filtering state machine sequentially performs sliding comparison on the data flow in the data channel through the base address, the offset and the graph and the mask, and when the filtering condition is met, the data is captured and stored in the memory.
The basic principle of filtering the user-defined graph is shown in fig. 3.
The core function of the user-defined graph is realized in a user-defined graph filtering state machine, the user-defined graph filtering state machine looks like a sliding window, when the received information flow arrives in sequence, the user-defined graph filtering state machine continuously slides on 4 data channels for comparison, when the condition is met, the user-defined graph filtering state machine captures and stores data into a DDR memory, and an upper computer can read and view interested information according to the user requirement. As shown in fig. 4.
Example 3
After the data is transmitted, the received data may have errors, and compared with the previous two embodiments, the error code type filtering and receiving function needs to finish receiving all frames, and some frames can determine the specific error type of the frame after being calculated according to a checking algorithm. In order to trace back frame data, a dual-port RAM is introduced as a buffer memory to temporarily store the current frame, and the filtered data packet is transferred to a memory after determining the error type. Common errors are FCS (Frame Check Sequence) errors, undersize short frame errors, IPv4 checksum errors, etc. The basic principle of the filtration is shown in fig. 5.
The filtering process of the error code type:
the filtering state machine constructed in the field programmable gate array is an error code type filtering state machine, wherein FCS error frame filtering, undersize short frame filtering, IPv4 check and error frame filtering are arranged in the error code type filtering state machine;
when filtering FCS error frames, step 2 specifically includes:
the error code type filtering state machine adopts a 32-bit cyclic redundancy check algorithm, when the enabling signal RX_ENAOUT and the termination signal RX_EOPOUT of the data channel are 1 at the same time, namely the current time sequence is the end of the current frame, the current frame is temporarily stored in the dual-port RAM, the last 32 bits are check codes of the current frame, if the 32-bit check codes calculated by the error code type filtering state machine are different from the original FCS of the current frame, the current frame is in error, namely the FCS is in error, and the error code type filtering state machine further starts to read data from the frame heads in the dual-port RAM and sequentially writes the data into the memory;
when the short frame is filtered, the step 2 specifically comprises:
the IEEE802.3 standard specifies that ethernet frames are at a minimum of 64 bytes, and when they are less than this length, the packet is in error, i.e. a short frame, in the CMAC-IP core, there are 4 128-bit data channels, i.e. 64 bytes, and the error type filtering state machine always detects the start and end of the frame, after the current frame header appears, the frame end must appear at the earliest in the last channel of the next valid clock edge, if the frame end appears in advance, the frame length must be less than 64 bytes, i.e. a short frame error, the error type filtering state machine relocates to the frame header of this short frame, and then the whole frame is written from the dual-port RAM into memory;
when filtering the IPv4 checksum error frame, the step 2 specifically includes:
the error type filtering state machine first locates the IP datagram start position, the header checksum length is the inverse of the 16-bit accumulated sum, and at the 10 th byte position relative to the IP datagram Wen Toubu, and the 6-byte source mac+2-byte type+10-byte IP header=24 bytes relative to the offset position of the MAC frame, so the checksum corresponds to the 6 th and 7 th bytes of the next data lane of the data lane where the data starts, and when the checksum is incorrect, the error type filtering state machine captures the frame and writes it to memory.
It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.
Claims (3)
1. The 100Gbps Ethernet filtering method is characterized by comprising a field programmable gate array, an upper computer and a memory, wherein a CMAC-IP core is arranged in the field programmable gate array, and a filtering state machine is constructed in the field programmable gate array; the field programmable gate array and the memory are connected with the upper computer through standard electrical interfaces;
the filtering method comprises the following steps:
step 1: the Ethernet data flow enters a CMAC-IP core at the test rate of 100Gbps, 4 128-bit data channels are arranged in the CMAC-IP core, and the Ethernet data flow is sequentially circularly output in the 4 128-bit data channels;
step 2: the data output by the data channel enters a filtering state machine for filtering;
step 3: storing the filtered data into a memory, and checking by a host computer;
filtering process based on standard Ethernet frame:
the filtering state machine constructed in the field programmable gate array is a tree state machine which is used for making the Ethernet protocol, and the tree state machine is used for classifying all the Ethernet protocols in a layering way;
the step 2 specifically comprises the following steps:
step 2.1: the filtering state machine firstly filters the basic protocol type of the frame head, then sequentially determines specific protocols step by step, and stores the protocol and reads the protocol by a host computer after finding out the protocol meeting the conditions;
step 2.2: since the start position of the frame may occur in any one of 4 128-bit data lanes, 4 128-bit data lanes including lane 0, lane 1, lane 2 and lane 3, and if the start position is in lane 0, then subsequent data occurs in the sequence of lane 1, lane 2, lane 3, lane 0, … …; the filtering state machine judges the data channel in which the starting position of the frame is located, the upper computer reads the stored protocol to capture the data flow in the data channel in sequence, and the captured frame is stored in the memory.
2. The 100Gbps ethernet filtering method of claim 1, wherein the filtering process of the user-defined graphics:
the filtering state machine constructed in the field programmable gate array is a self-defined graph filtering state machine, the self-defined graph filtering state machine comprises a base address, an offset, a graph and a mask, the base address is a reference position of filtering conditions, the offset is an integer multiple byte offset relative to the base address, the graph is information required to be searched by a user, the length can reach 16 bytes, the mask corresponds to the graph, the length is also 16 bytes, when the mask bit is equal to 1, the corresponding graph bit is valid, and when the mask bit is zero, the corresponding bit is invalid;
the step 2 specifically comprises the following steps:
step 2.1: the user inputs the base address, the offset, the graph and the mask through the upper computer, and the mapping command of the graph filtering state machine is customized;
step 2.2: since the start position of data may occur in any one of 4 128-bit data lanes, 4 128-bit data lanes include lane 0, lane 1, lane 2 and lane 3, and if the start position is in lane 0, then subsequent data occurs in lane 1, lane 2, lane 3, lane 0, … … in sequence; the user-defined graph filtering state machine judges the data channel in which the starting position of the data is, the user-defined graph filtering state machine sequentially performs sliding comparison on the data flow in the data channel through the base address, the offset and the graph and the mask, and when the filtering condition is met, the data is captured and stored in the memory.
3. The 100Gbps ethernet filtering method of claim 1, wherein the error type filtering process:
the filtering state machine constructed in the field programmable gate array is an error code type filtering state machine, wherein FCS error frame filtering, undersize short frame filtering, IPv4 check and error frame filtering are arranged in the error code type filtering state machine;
when filtering FCS error frames, step 2 specifically includes:
the error code type filtering state machine adopts a 32-bit cyclic redundancy check algorithm, when the enabling signal RX_ENAOUT and the termination signal RX_EOPOUT of the data channel are 1 at the same time, namely the current time sequence is the end of the current frame, the current frame is temporarily stored in the dual-port RAM, the last 32 bits are check codes of the current frame, if the 32-bit check codes calculated by the error code type filtering state machine are different from the original FCS of the current frame, the current frame is in error, namely the FCS is in error, and the error code type filtering state machine further starts to read data from the frame heads in the dual-port RAM and sequentially writes the data into the memory;
when the short frame is filtered, the step 2 specifically comprises:
the IEEE802.3 standard specifies that ethernet frames are at a minimum of 64 bytes, and when they are less than this length, the packet is in error, i.e. a short frame, in the CMAC-IP core, there are 4 128-bit data channels, i.e. 64 bytes, and the error type filtering state machine always detects the start and end of the frame, after the current frame header appears, the frame end must appear at the earliest in the last channel of the next valid clock edge, if the frame end appears in advance, the frame length must be less than 64 bytes, i.e. a short frame error, the error type filtering state machine relocates to the frame header of this short frame, and then the whole frame is written from the dual-port RAM into memory;
when filtering the IPv4 checksum error frame, the step 2 specifically includes:
the error type filtering state machine first locates the IP datagram start position, the header checksum length is the inverse of the 16-bit accumulated sum, and at the 10 th byte position relative to the IP datagram Wen Toubu, and the 6-byte source mac+2-byte type+10-byte IP header=24 bytes relative to the offset position of the MAC frame, so the checksum corresponds to the 6 th and 7 th bytes of the next data lane of the data lane where the data starts, and when the checksum is incorrect, the error type filtering state machine captures the frame and writes it to memory.
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| WO2019119389A1 (en) * | 2017-12-22 | 2019-06-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and apparatus for configuring a flex ethernet node |
| CN108880686A (en) * | 2018-07-14 | 2018-11-23 | 苏州大学张家港工业技术研究院 | Single-chip OUN towards the FPGA transceiver for more applying PON |
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