CN112084063A - 100Gbps Ethernet filtering method - Google Patents

Abstract

The invention discloses a 100Gbps Ethernet filtering method which comprises a field programmable gate array, an upper computer and a memory, wherein a CMAC-IP core is arranged in the field programmable gate array, and a filtering state machine is constructed in the field programmable gate array. The field programmable gate array and the memory are connected with an upper computer through a standard electrical interface. The Ethernet data flow enters a CMAC-IP core under the test rate of 100Gbps, the CMAC-IP core is provided with 4 128 bit data channels, and the Ethernet data flow is sequentially and circularly output in the 4 128 bit data channels; the data output by the data channel enters a filtering state machine for filtering; and storing the filtered data into a memory for an upper computer to check. The 100Gbps Ethernet filtering method provided by the invention comprises a filtering method based on a standard Ethernet frame, a user-defined graph filtering method and an error code type filtering method, can realize effective data screening in 100Gbps high-speed, multi-protocol and high-flow Ethernet data, and improves the efficiency of extracting useful information.

Description

100Gbps Ethernet filtering method

Technical Field

The invention relates to the field of filtering Ethernet data packets at a 100Gbps test rate, in particular to a 100Gbps Ethernet filtering method.

Background

With the rapid development of information technology, ultra-high speed, ultra-large capacity and ultra-wide bandwidth become the future development trend of wired communication. Currently, all parties in the industry, including telecom operators, equipment vendors, etc., are actively driving the deployment of applications for 100G technology. The Ethernet tester is developed rapidly in recent years, and shows the trends of increasing the testing speed, and increasing the capability of carrying out complex testing towards the application. The foreign high-speed network protocol testing research is mainly embodied in the technologies and implementation means of high-speed protocol detection integration, automatic testing and the like, and an evaluation result is directly obtained according to information which is highly concerned by a user. Due to the limitations of core technologies such as high interface speed, large data flow, complex and various protocols and the like, the domestic high-speed ethernet tester has the conditions of low test speed, incomplete protocol test, lack of filtering and screening capabilities of application information test and the like, and needs to be comprehensively and greatly improved.

At present, the mainstream domestic instrument testing rate is mainly concentrated on giga and tera, and the development of a 100G network tester is in progress, so that the development of the latest technology of the Ethernet is difficult to meet. Also, how to implement efficient data screening from 100Gbps high-rate, multi-protocol, and high-traffic data is a new challenge.

Disclosure of Invention

The invention aims to provide a 100Gbps Ethernet filtering method, which realizes the function of screening Ethernet frames interested by a user by setting filtering conditions by the user and improves the efficiency of extracting useful information.

The invention adopts the following technical scheme:

a100 Gbps Ethernet filtering method comprises a field programmable gate array, an upper computer and a memory, wherein a CMAC-IP core is arranged in the field programmable gate array, and a filtering state machine is constructed in the field programmable gate array; the field programmable gate array and the memory are connected with an upper computer through a standard electrical interface;

the filtering method comprises the following steps:

step 1: the Ethernet data flow enters a CMAC-IP core under the test rate of 100Gbps, the CMAC-IP core is provided with 4 128 bit data channels, and the Ethernet data flow is sequentially and circularly output in the 4 128 bit data channels;

step 2: the data output by the data channel enters a filtering state machine for filtering;

and step 3: and storing the filtered data into a memory for an upper computer to check.

Preferably, the filtering process based on standard ethernet frames:

the filtering state machine constructed in the field programmable gate array is a tree state machine which is made of protocols of the Ethernet and carries out layered classification on all the protocols of the Ethernet;

the step 2 specifically comprises the following steps:

step 2.1: the filtering state machine firstly filters the basic protocol type of the frame header, then sequentially determines specific protocols step by step, and stores the protocols and provides the protocols for the upper computer to read after the protocols meeting the conditions are found;

step 2.2: since the start position of a frame may occur in any one of the 4 128-bit data lanes, the 4 128-bit data lanes include lane 0, lane 1, lane 2, and lane 3, assuming the start position is lane 0, then subsequent data occurs in order at lane 1, lane 2, lane 3, lane 0, … …; and the filtering state machine judges which data channel the initial position of the frame is in, the upper computer reads the stored protocol to capture the data streams in the data channels in sequence, and the captured frame is stored in the memory.

Preferably, the filtering process of the user-defined graph is as follows:

the filtering state machine constructed in the field programmable gate array is a user-defined graph filtering state machine, the user-defined graph filtering state machine comprises a base address, an offset, a graph and a mask, the base address is a reference position of a filtering condition, the offset is an integral multiple byte offset relative to the base address, the graph is information which needs to be searched by a user, the length can reach 16 bytes, the mask corresponds to the graph, the length is 16 bytes, when a mask bit is equal to 1, the corresponding graph bit is valid, and when the mask bit is zero, the corresponding bit is invalid;

the step 2 specifically comprises the following steps:

step 2.1: inputting a base address, an offset, a graph and a mask code and customizing a mapping command of a graph filtering state machine by a user through an upper computer;

step 2.2: since the starting position of data may occur in any one of the 4 128-bit data lanes, the 4 128-bit data lanes include lane 0, lane 1, lane 2, and lane 3, assuming the starting position is lane 0, then subsequent data occurs in order at lane 1, lane 2, lane 3, lane 0, … …; and the user-defined graph filtering state machine judges which data channel the initial position of the data is in, sequentially carries out sliding comparison on data streams in the data channels through the base address, the offset, the graph and the mask, and captures the data and stores the data in a memory when the filtering condition is met.

Preferably, the filtering of the error types:

the filtering state machine constructed in the field programmable gate array is an error code type filtering state machine, and FCS error frame filtering, Undersize short frame filtering, IPv4 check sum error frame filtering are arranged in the error code type filtering state machine;

when filtering an FCS error frame, step 2 specifically includes:

the error code type filtering state machine adopts a 32-bit cyclic redundancy check algorithm, when an enabling signal RX _ ENOUT and a terminating signal RX _ EOPOUT of a data channel are simultaneously 1, namely the current time sequence is the end of a current frame, the current frame is temporarily stored in the dual-port RAM, the last 32 bits are the check code of the current frame, if the 32-bit check code calculated by the error code type filtering state machine is different from the original FCS of the current frame, the current frame is in error, namely the FCS is in error, and the error code type filtering state machine further reads data from the frame header in the dual-port RAM and sequentially writes the data into a memory;

when filtering the Undersize short frame, the step 2 specifically comprises:

the IEEE802.3 standard stipulates that the shortest of Ethernet frames is 64 bytes, when the length is less than the length, the data packet has errors, namely a short frame, in the CMAC-IP core, 4 128-bit data channels, namely 64 bytes are included, and an error code type filtering state machine always detects the start and the end of the frame, after the current frame head appears, the frame tail must appear in the last channel of the next beat of effective clock edge earliest, if the frame tail appears in advance, the frame length must be less than 64 bytes, namely the short frame is wrong, the error code type filtering state machine relocates to the frame head of the short frame, and then the whole frame is written into a memory from a double-port RAM;

when IPv4 checksum error frame filtering, step 2 specifically includes:

the error code type filtering state machine firstly locates the initial position of the IP datagram, according to the Ethernet standard, the length of the header check sum is 16-bit accumulated sum of the anti-codes, and the offset position relative to the MAC frame is 6 bytes of MAC +6 bytes of source MAC +2 bytes type +10 bytes IP header is 24 bytes relative to the 10 th byte position of the IP data message header, so the check sum corresponds to the 6 th and 7 th bytes of the next data channel of the data initial, when the check is incorrect, the error code type filtering state machine captures the frame and writes the frame into the memory.

The invention has the beneficial effects that:

the 100Gbps Ethernet filtering method provided by the invention comprises a filtering method based on a standard Ethernet frame, a user-defined graph filtering method and an error code type filtering method, can realize effective data screening in 100Gbps high-speed, multi-protocol and high-flow Ethernet data, and improves the efficiency of extracting useful information.

Drawings

FIG. 1 is a diagram of a tree state machine.

Fig. 2 is a basic schematic diagram of fixed-length 64-byte IP frame filtering.

FIG. 3 is a diagram of a user-defined graphical filtering rationale.

Fig. 4 is a basic schematic diagram of a sliding window.

Fig. 5 is a basic schematic diagram of error type filtering.

Detailed Description

The following description of the embodiments of the present invention will be made with reference to the accompanying drawings:

ethernet testers typically include two basic functions, transmit and receive. The receive function includes full and partial receive. Full reception is where the tester receives and stores all of the data, while partial reception is where all of the data received is filtered, usually selectively on demand. In filtering reception, trigger reception is a special filtering, which is triggered according to a condition set by a user to capture a data packet, and generally includes a start trigger, a middle trigger, a tail trigger, and the like. The filtering receiving condition of the ethernet tester generally includes a source MAC address, a destination MAC address, a source IP address, a destination IP address, a pattern trigger, frames of different kinds of error codes, and the like.

With reference to fig. 1 to 5, a 100Gbps ethernet filtering method includes a field programmable gate array, an upper computer and a memory, where the field programmable gate array has a CMAC-IP core, and a filtering state machine is constructed in the field programmable gate array. The field programmable gate array and the memory are connected with an upper computer through a standard electrical interface. The memory is a DDR4 memory.

The field programmable gate array is an ultra Scale series high-speed FPGA, the ultra Scale is used as a programmable hardware platform, has large-scale distributed hardware resources, and has the characteristics of high speed, short development period, good parallel performance and the like, and is very suitable for processing 100Gbps high-speed data. In addition, the CMAC-IP core of the product supports the international standards IEEE std 802.3-2012CAUI-10 and CAUI-4, so the requirements of the invention can be met.

The CMAC IP core comprises a high-speed transceiver, an RS-FEC (Reed-Solomon Forward Error Correction), a PCS (physical Coding subsystem), a control state machine, a local bus LBUS (local BUS) and the like. The LBUS comprises a sending module and a receiving module, the receiving interface comprises 4 128-bit data channels RX _ DATAOUT0, RX _ DATAOUT1, RX _ DATAOUT2 and RX _ DATAOUT3, and received data sequentially appears according to a channel 0, a channel 1, a channel 2 and a channel 3 in a channel circulation mode. Each channel includes an enable, a data start, a data end, an error indication, a last byte empty indication, etc.

The filtering method comprises the following steps:

step 1: the Ethernet data flow enters a CMAC-IP core under the test rate of 100Gbps, the CMAC-IP core is provided with 4 128-bit data channels, the 4 128-bit data channels comprise a channel 0, a channel 1, a channel 2 and a channel 3, and the Ethernet data flow is sequentially and circularly output in the 4 128-bit data channels.

Step 2: the data output by the data channel enters a filtering state machine for filtering;

and step 3: and storing the filtered data into a memory for an upper computer to check.

The invention provides a filtering method based on standard Ethernet frames, a user-defined graph filtering method and an error code type filtering method.

Example 1

Since the CMAC-IP core has automatically processed the PREAMBLEs PREAMBLE and SFD (Start-of-Frame limiter), the LBUS receives data from the destination MAC address to the FCS part. According to the ethernet standard, the information relative position indication of the frame header has been fixed, so the relative position in the CMAC-IP core data channel has also been determined.

Filtering process based on standard ethernet frames:

the filtering state machine constructed in the field programmable gate array is a tree state machine which is made of protocols of the Ethernet, and the tree state machine is used for hierarchically classifying all the protocols of the Ethernet, as shown in FIG. 1.

The step 2 specifically comprises the following steps:

step 2.1: the filtering state machine firstly filters the basic protocol type of the frame header, then sequentially determines specific protocols step by step, and stores the protocols and provides the protocols for the upper computer to read after the protocols meeting the conditions are found;

step 2.2: since the start of a frame may occur in any of the 4 128-bit data lanes, the 4 128-bit data lanes include lane 0, lane 1, lane 2, and lane 3, assuming the start is at lane 0, then the subsequent data occurs in order at lane 1, lane 2, lane 3, lane 0, … …, and the principle is similar for the start of a frame first occurring in one of the other 3 lanes. And the filtering state machine judges which data channel the initial position of the frame is in, the upper computer reads the stored protocol to capture the data streams in the data channels in sequence, and the captured frame is stored in the memory.

Since the ethernet protocols are various, taking the common IP frame with a length Of 64 bytes as an example for explanation, if the data Start position is present in channel 0, that is, when the enable signal RX _ ENAOUT is equal to 1 and the Start signal RX _ SOPOUT1 is equal to 1, the SOF (Start-Of-Packet) data is present in channel RX _ DATAOUT 0. The correspondence of the four LBUS channels is shown in tables 1 to 4.

TABLE 1 LBUS channel 0 correspondences

TABLE 2 LBUS channel 1 correspondences

TABLE 3 LBUS channel 2 correspondences

TABLE 4 LBUS channel 3 correspondences

Fig. 2 illustrates the basic principle of the hardware filtering process by taking a 64-byte IP frame as an example, and the other protocols of the ethernet network are implemented in a similar manner.

Example 2

In order to be independent of standard ethernet frame-based, users can customize some keyword graphs to filter the received data.

And (3) filtering the user-defined graph:

the filtering state machine constructed in the field programmable gate array is a self-defined graph filtering state machine, the self-defined graph filtering state machine comprises a base Address, an offset, a graph and a mask, the base Address is a reference position of a filtering condition and can be Top of Frame, Top of VLAN, Top of IPv4 Header, Top of TCP Header, Top of UDP Header, IP Address and the like, the offset is an integral multiple byte offset relative to the base Address, the graph is information required to be searched by a user, the length can reach 16 bytes, the mask corresponds to the graph, the length is also 16 bytes, when a mask bit is equal to 1, the corresponding graph bit is valid, and when the mask bit is zero, the corresponding bit is invalid;

the step 2 specifically comprises the following steps:

step 2.1: inputting a base address, an offset, a graph and a mask code and customizing a mapping command of a graph filtering state machine by a user through an upper computer;

step 2.2: since the starting position of data may occur in any one of the 4 128-bit data lanes, the 4 128-bit data lanes include lane 0, lane 1, lane 2, and lane 3, assuming the starting position is lane 0, then subsequent data occurs in order at lane 1, lane 2, lane 3, lane 0, … …; and the user-defined graph filtering state machine judges which data channel the initial position of the data is in, sequentially carries out sliding comparison on data streams in the data channels through the base address, the offset, the graph and the mask, and captures the data and stores the data in a memory when the filtering condition is met.

The basic principle of filtering of user-defined graphics is shown in fig. 3.

The core function of the user-defined graph is realized in the user-defined graph filtering state machine, the user-defined graph filtering state machine is like a sliding window, when the received information flow sequentially comes, the user-defined graph filtering state machine continuously slides and compares on 4 data channels, when the conditions are met, the user-defined graph filtering state machine captures and stores data into a DDR memory, and an upper computer can read and check the interested information according to the user requirements. As shown in fig. 4.

Example 3

After the data is transmitted, errors may occur in the received data, and compared with the previous two embodiments, the error code type filtering and receiving function needs to wait for all frames to be received, and the specific error type of some frames can be determined only after the frames are calculated according to the check algorithm. In order to trace back frame data, the invention introduces a double-port RAM as a buffer memory for temporarily storing a current frame, and transfers a filtered data packet to a memory after determining the error type. Common errors are fcs (frame Check sequence) errors, underize short frame errors, IPv4 checksum errors, etc. The basic principle of filtration is shown in figure 5.

Filtering process of error code type:

the filtering state machine constructed in the field programmable gate array is an error code type filtering state machine, and FCS error frame filtering, Undersize short frame filtering, IPv4 check sum error frame filtering are arranged in the error code type filtering state machine;

when filtering an FCS error frame, step 2 specifically includes:

the error code type filtering state machine adopts a 32-bit cyclic redundancy check algorithm, when an enabling signal RX _ ENOUT and a terminating signal RX _ EOPOUT of a data channel are simultaneously 1, namely the current time sequence is the end of a current frame, the current frame is temporarily stored in the dual-port RAM, the last 32 bits are the check code of the current frame, if the 32-bit check code calculated by the error code type filtering state machine is different from the original FCS of the current frame, the current frame is in error, namely the FCS is in error, and the error code type filtering state machine further reads data from the frame header in the dual-port RAM and sequentially writes the data into a memory;

when filtering the Undersize short frame, the step 2 specifically comprises:

the IEEE802.3 standard stipulates that the shortest of Ethernet frames is 64 bytes, when the length is less than the length, the data packet has errors, namely a short frame, in the CMAC-IP core, 4 128-bit data channels, namely 64 bytes are included, and an error code type filtering state machine always detects the start and the end of the frame, after the current frame head appears, the frame tail must appear in the last channel of the next beat of effective clock edge earliest, if the frame tail appears in advance, the frame length must be less than 64 bytes, namely the short frame is wrong, the error code type filtering state machine relocates to the frame head of the short frame, and then the whole frame is written into a memory from a double-port RAM;

when IPv4 checksum error frame filtering, step 2 specifically includes:

the error code type filtering state machine firstly locates the initial position of the IP datagram, according to the Ethernet standard, the length of the header check sum is 16-bit accumulated sum of the anti-codes, and the offset position relative to the MAC frame is 6 bytes of MAC +6 bytes of source MAC +2 bytes type +10 bytes IP header is 24 bytes relative to the 10 th byte position of the IP data message header, so the check sum corresponds to the 6 th and 7 th bytes of the next data channel of the data initial, when the check is incorrect, the error code type filtering state machine captures the frame and writes the frame into the memory.

It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.

Claims (4)

1. A100 Gbps Ethernet filtering method is characterized by comprising a field programmable gate array, an upper computer and a memory, wherein a CMAC-IP core is arranged in the field programmable gate array, and a filtering state machine is constructed in the field programmable gate array; the field programmable gate array and the memory are connected with an upper computer through a standard electrical interface;

the filtering method comprises the following steps:

step 1: the Ethernet data flow enters a CMAC-IP core under the test rate of 100Gbps, the CMAC-IP core is provided with 4 128 bit data channels, and the Ethernet data flow is sequentially and circularly output in the 4 128 bit data channels;

step 2: the data output by the data channel enters a filtering state machine for filtering;

and step 3: and storing the filtered data into a memory for an upper computer to check.

2. The method of claim 1, wherein the filtering process based on standard ethernet frames is:

the filtering state machine constructed in the field programmable gate array is a tree state machine which is made of protocols of the Ethernet and carries out layered classification on all the protocols of the Ethernet;

the step 2 specifically comprises the following steps:

step 2.1: the filtering state machine firstly filters the basic protocol type of the frame header, then sequentially determines specific protocols step by step, and stores the protocols and provides the protocols for the upper computer to read after the protocols meeting the conditions are found;

step 2.2: since the start position of a frame may occur in any one of the 4 128-bit data lanes, the 4 128-bit data lanes include lane 0, lane 1, lane 2, and lane 3, assuming the start position is lane 0, then subsequent data occurs in order at lane 1, lane 2, lane 3, lane 0, … …; and the filtering state machine judges which data channel the initial position of the frame is in, the upper computer reads the stored protocol to capture the data streams in the data channels in sequence, and the captured frame is stored in the memory.

3. The 100Gbps ethernet filtering method according to claim 1, wherein the filtering process of the user-defined graphics:

the filtering state machine constructed in the field programmable gate array is a user-defined graph filtering state machine, the user-defined graph filtering state machine comprises a base address, an offset, a graph and a mask, the base address is a reference position of a filtering condition, the offset is an integral multiple byte offset relative to the base address, the graph is information which needs to be searched by a user, the length can reach 16 bytes, the mask corresponds to the graph, the length is 16 bytes, when a mask bit is equal to 1, the corresponding graph bit is valid, and when the mask bit is zero, the corresponding bit is invalid;

the step 2 specifically comprises the following steps:

step 2.1: inputting a base address, an offset, a graph and a mask code and customizing a mapping command of a graph filtering state machine by a user through an upper computer;

step 2.2: since the starting position of data may occur in any one of the 4 128-bit data lanes, the 4 128-bit data lanes include lane 0, lane 1, lane 2, and lane 3, assuming the starting position is lane 0, then subsequent data occurs in order at lane 1, lane 2, lane 3, lane 0, … …; and the user-defined graph filtering state machine judges which data channel the initial position of the data is in, sequentially carries out sliding comparison on data streams in the data channels through the base address, the offset, the graph and the mask, and captures the data and stores the data in a memory when the filtering condition is met.

4. The method of claim 1, wherein the filtering of the error types comprises:

the filtering state machine constructed in the field programmable gate array is an error code type filtering state machine, and FCS error frame filtering, Undersize short frame filtering, IPv4 check sum error frame filtering are arranged in the error code type filtering state machine;

when filtering an FCS error frame, step 2 specifically includes:

the error code type filtering state machine adopts a 32-bit cyclic redundancy check algorithm, when an enabling signal RX _ ENOUT and a terminating signal RX _ EOPOUT of a data channel are simultaneously 1, namely the current time sequence is the end of a current frame, the current frame is temporarily stored in the dual-port RAM, the last 32 bits are the check code of the current frame, if the 32-bit check code calculated by the error code type filtering state machine is different from the original FCS of the current frame, the current frame is in error, namely the FCS is in error, and the error code type filtering state machine further reads data from the frame header in the dual-port RAM and sequentially writes the data into a memory;

when filtering the Undersize short frame, the step 2 specifically comprises:

the IEEE802.3 standard stipulates that the shortest of Ethernet frames is 64 bytes, when the length is less than the length, the data packet has errors, namely a short frame, in the CMAC-IP core, 4 128-bit data channels, namely 64 bytes are included, and an error code type filtering state machine always detects the start and the end of the frame, after the current frame head appears, the frame tail must appear in the last channel of the next beat of effective clock edge earliest, if the frame tail appears in advance, the frame length must be less than 64 bytes, namely the short frame is wrong, the error code type filtering state machine relocates to the frame head of the short frame, and then the whole frame is written into a memory from a double-port RAM;

when IPv4 checksum error frame filtering, step 2 specifically includes:

the error code type filtering state machine firstly locates the initial position of the IP datagram, according to the Ethernet standard, the length of the header check sum is 16-bit accumulated sum of the anti-codes, and the offset position relative to the MAC frame is 6 bytes of MAC +6 bytes of source MAC +2 bytes type +10 bytes IP header is 24 bytes relative to the 10 th byte position of the IP data message header, so the check sum corresponds to the 6 th and 7 th bytes of the next data channel of the data initial, when the check is incorrect, the error code type filtering state machine captures the frame and writes the frame into the memory.

Images