CN112035389A

CN112035389A - PLB-AXI bus conversion bridge and working method thereof

Info

Publication number: CN112035389A
Application number: CN202010888401.0A
Authority: CN
Inventors: 李磊; 贾一鸣; 肖建青; 巨新刚; 于飞; 赵翠华; 娄冕
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2020-12-04
Anticipated expiration: 2040-08-28
Also published as: CN112035389B

Abstract

The invention discloses a PLB-AXI bus conversion bridge and a working method thereof.A PLB slave interface unit divides a PLB access protocol interface and is used for processing a PLB interface signal; the protocol conversion control unit is used for realizing the complete conversion from the PLB protocol to the AXI protocol; the AXI main interface unit is used for realizing the division of an AXI access protocol interface and processing AXI interface signals; the register unit is used for registering the internal working state information of the protocol conversion control unit and sending the information to the DCR interface; and the exception processing unit is used for processing the internal work exception information of the protocol conversion control unit and sending the processed information to the exception/interrupt interface. The method adopts a two-stage flow protocol fast conversion strategy and a cache strategy for avoiding multi-access congestion, realizes the conversion of an access command initiated by a PLB (programmable logic bus) into an AXI (advanced extensible interface) bus access command of a slave device, realizes the protocol communication of two high-speed buses, improves the communication efficiency in a system, and solves the problem of efficient and highly reliable conversion from the access of the high-speed PLB bus to the AXI bus in an embedded system or an SoC (system on a chip) system.

Description

PLB-AXI bus conversion bridge and working method thereof

Technical Field

The invention belongs to the technical field of embedded system and integrated circuit design, and particularly relates to a PLB-AXI bus conversion bridge and a working method thereof.

Background

The super large scale set high performance SoC is designed without opening a high speed interconnection Bus System (Bus System) on chip, and the current mainstream high speed interconnection Bus on chip is represented by ARM corporation, such as amba (advanced microcontroller Bus architecture) Bus architecture, IBM corporation, and CoreConnect Bus specification. The axi (advanced eXtensible interface) bus protocol is the most important part of the AMBA3.0 protocol, and is widely applied to the field of SoC design due to the characteristics of high performance, high bandwidth and low delay. PLB (processor Local bus) and DCR bus (Device Control Register) are different bus protocols under the CoreConnect bus specification, and PLB bus has the characteristics of high reliability, high speed and the like, is suitable for complex processor systems, and is represented by PowerPC processor of IBM company. At present, a large number of peripheral IPs are designed based on an AXI bus protocol and cannot be directly applied to a PLB bus system, so that conversion of two bus protocols is required to be realized, and rapid transplantation of the peripheral IPs of different bus interfaces is facilitated. Therefore, it is important to design a conversion control structure from PLB bus to AXI bus protocol, especially for high-performance and high-reliability conversion control.

At present, the mainstream conversion control structure design takes two bus conversion bridges as a typical design, the access initiated by a PLB bus has high speed and randomness, if multiple access requests exist in a certain short time window, because a certain time overhead is required for completing one conversion by the conversion bridge, the conversion reliability needs to be ensured while the conversion is ensured to be correct, the problem of access congestion is solved, the access request cannot be lost, and the bridge does not have such function temporarily. Meanwhile, the bridge does not consider how to improve the conversion efficiency, and the components for realizing protocol conversion inside are not clear.

At present, the existing conversion structure can not consider the problems, reflects the deficiency of the corresponding technology on different levels, and has no method for well solving the problems after searching relevant documents.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a universal high-performance high-reliability fast conversion bridge from a PLB (programmable logic controller) bus to an AXI (advanced extensible interface) bus and a working method thereof by adopting a two-stage pipelining protocol fast conversion design, a congestion avoidance design of a multi-access cache, a multi-clock domain synchronous processing design of an asynchronous FIFO (first-in first-out) and the like aiming at the defects in the prior art and aiming at the fast conversion requirement among high-speed bus protocols, so that an access command initiated by the PLB bus can be converted into an AXI bus access command, the protocol communication of the two high-speed buses is realized, and the communication efficiency in a system is greatly; the problem of efficient and highly reliable conversion from high-speed PLB bus to AXI bus access in an embedded system and an SoC system is solved.

The invention adopts the following technical scheme:

a PLB-AXI bus translation bridge comprising:

the PLB slave interface unit realizes the division of PLB access protocol interfaces and is used for processing PLB interface signals;

the protocol conversion control unit is used for realizing the complete conversion from the PLB protocol to the AXI protocol;

the AXI main interface unit is used for realizing the division of an AXI access protocol interface and processing AXI interface signals;

the protocol conversion control unit is connected with a PLB bus through a PLB slave interface unit, the PLB slave interface unit is connected with an AXI bus through an AXI master interface unit, the AXI master interface unit is connected with a DCR interface through a register unit, and the AXI master interface unit is connected with an exception/interrupt interface through an exception processing unit;

the register unit is used for registering the internal working state information of the protocol conversion control unit, accessing the register unit through a DCR interface outside the conversion bridge and acquiring the current working state of the conversion bridge;

the exception handling unit is used for processing the abnormal information of the internal work of the protocol conversion control unit, generating exception or interrupt and sending the exception or interrupt to an exception/interrupt interface;

and the method adopts a two-stage flow protocol fast conversion strategy and a cache strategy for avoiding multi-access congestion to convert an access command initiated by the PLB bus into an AXI bus access command of the slave equipment.

Specifically, the protocol fast conversion strategy of the two-stage pipelining specifically includes:

the first stage is command/address protocol conversion, and the second stage is data protocol conversion; after the first stage access translation is completed, the second stage access translation is performed with minimal time delay, while the first stage begins the next translation.

Specifically, the cache policy for avoiding the multiple access congestion specifically includes:

and storing the command/address and the access data into the FIFO according to the sequence, and taking out the command/address and the access data in sequence according to the sequence for conversion, wherein the command/address FIFO and the data FIFO are included.

Furthermore, the depth of the command/address FIFO is n, the width meets the storage requirements of the command and the address, and the command/address FIFO is used for caching a plurality of access commands/addresses;

the depth of the data FIFO is the same as that of the command/address FIFO, the width of the data FIFO is the data volume m of one-time maximum Burst access, and each row of data corresponds to each row of command/address one by one and is used for caching a plurality of access data.

Specifically, the PLB slave interface unit includes a command/address interface for receiving command/address signals, a write data interface for receiving write data signals, and a read data interface for transmitting read data signals.

Specifically, the protocol conversion control unit comprises a PLB protocol analysis unit, a write channel unit, a write command/address FIFO unit, a write data FIFO unit, a read channel unit, a read command/address FIFO unit, a read data FIFO unit, and an AXI protocol analysis unit; the PLB protocol analysis unit is respectively connected with the write channel unit and the read channel unit, and the write channel unit is respectively connected with the AXI protocol analysis unit through the write command/address FIFO unit and the write data FIFO unit; the read channel unit is connected with the AXI protocol analysis unit through a read command/address FIFO unit and a read data FIFO unit respectively.

Furthermore, the PLB protocol analysis unit is used for realizing the analysis and selection of PLB command/address and read-write data protocols; the write channel unit is used for receiving the write protocol analyzed and completed by the PLB protocol analysis unit and distributing the write protocol to corresponding write channels, wherein the write channels comprise a write command/address channel, a write data channel and a write response channel; the write command/address FIFO unit is used for receiving and caching command information sent by a write command/address channel in the write channel unit; the write data FIFO unit is used for receiving and caching data sent by a write data channel in the write channel unit; the reading channel unit is used for receiving the reading protocol analyzed and completed by the PLB protocol analyzing unit and distributing the reading protocol to the corresponding reading channel, wherein the reading channel unit comprises a reading command/address channel, a reading data channel and a reading response channel; the read command/address FIFO unit is used for receiving and caching command information sent by a read command/address channel; the read data FIFO unit is used for sending the data received and buffered from the AXI protocol analysis unit to the middle read data channel; the AXI protocol analysis unit is used for realizing the analysis and selection of the AXI protocol, and realizing the acquisition of commands or data from the write command/address FIFO unit, the write data FIFO unit and the AXI protocol analysis unit, and the analysis is carried out to the AXI protocol and sent to the AXI main interface unit.

Furthermore, the AXI protocol resolution unit receives data sent by the AXI main interface unit and buffers the data into the read data FIFO unit.

Specifically, the AXI master interface unit includes an address interface for transmitting address signals, a write data interface for transmitting write data signals, and a read data interface for receiving read data signals.

Another technical solution of the present invention is a working method of a PLB-AXI bus conversion bridge, comprising the steps of:

s1, the peripheral PLB bus initiates access, and is processed by the PLB slave interface unit, and divided into a command/address interface, a write data interface and a read data interface;

s2, the divided PLB interface enters a protocol conversion control unit and is analyzed into write access and read access through a PLB protocol analysis unit; the write access is divided into write command/address, write data and write response, which enter the write channel unit respectively and are processed according to the corresponding channels, the write command/address is stored in the write command/address FIFO, the write data and the write response are stored in the write data FIFO, and are converted into the write access time sequence of AXI through the AXI protocol analysis unit; the read access is divided into read command/address, read data and read response, which enter the read channel unit respectively and are processed according to the corresponding channel, the read command/address is stored in the read command/address FIFO, the read data and the read response acquired by the AXI protocol analysis unit from the AXI interface are stored in the read data FIFO, are taken out by the read data and the read response channel in the read channel unit and are converted into PLB read time sequence, and then are transmitted to the PLB protocol analysis unit;

s3, the state of the protocol conversion control unit in operation enters the register unit and is sent to the DCR interface; the abnormity generated in the work enters an abnormity processing unit and is sent to an abnormity/terminal interface;

s4, AXI access generated by the protocol conversion control unit is divided into an address interface, a write data interface and a read data interface through AXI interface processing, and the access to a peripheral AXI bus is initiated.

Compared with the prior art, the invention has at least the following beneficial effects:

the PLB-AXI bus conversion bridge realizes the conversion of the access command initiated by the PLB bus into the AXI bus access command of the slave equipment, improves the communication efficiency in a system and simplifies the transplantation of an AXI interface peripheral IP. .

Furthermore, two-stage flow is adopted to realize rapid protocol conversion, and conversion efficiency is improved. The first stage is command/address protocol conversion and the second stage is data protocol conversion. After the first level access transition is completed, the second level access transition is performed with minimal time delay, while the first level may begin the next transition, and so on. And a conversion mode of two-stage pipelining is adopted, so that the conversion time overhead is greatly reduced.

Furthermore, a multi-access cache strategy is adopted, so that the problem of multi-access congestion is effectively avoided. Access requests (commands, data and the like) which cannot be processed in time are cached, and rapid conversion is sequentially carried out according to the sequence, so that the access requests are not lost, the congestion of multiple accesses can be avoided, and the reliability of a conversion bridge is greatly improved.

Further, the command/address FIFO and the data FIFO realize independent caching of commands and data, and command/address and access data are stored into the FIFO for multiple times according to the sequence and are sequentially taken out according to the sequence for conversion. The problem of access congestion caused by untimely processing can be solved, access loss caused by congestion can be effectively prevented, and the conversion reliability is greatly improved.

Furthermore, the PLB slave interface unit is divided according to the command/address interface, the write data interface and the read data interface, and the access initiated by the PLB interface can be efficiently processed.

Furthermore, the protocol conversion control unit realizes the rapid conversion from PLB access to AXI access through the interconnection among the PLB protocol analysis unit, the read-write channel, the read-write command/address FIFO, the read-write data FIFO and the AXI analysis unit.

Furthermore, the protocol conversion control unit realizes the rapid conversion from the PLB access to the AXI access by the detailed division of the read-write channel, through the read-write command/address FIFO and the read-write data FIFO and depending on the PLB protocol analysis unit and the AXI analysis unit.

Furthermore, read access data enters an AXI protocol for analysis through an AXI main interface, and the analyzed data is cached in a read data FIFO to complete the rapid circulation of the read data.

Furthermore, the AXI main interface unit is divided according to an address interface, a write data interface and a read data interface, and the access of the AXI interface can be efficiently processed.

A working method of a PLB-AXI bus conversion bridge adopts two-stage flow processing, multiple access cache and a strategy of realizing asynchronous bus synchronous processing by means of asynchronous FIFO to realize the conversion of an access command initiated by a PLB bus into an AXI bus access command of a slave device, thereby improving the communication efficiency in a system and simplifying the transplantation of an AXI interface peripheral IP.

In conclusion, the invention has the advantages of flexible and simple structure, high working efficiency, capability of adjusting the FIFO size according to the requirement, easiness in transplantation and expansion and capability of being widely applied to the design of an embedded system and an integrated circuit.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

FIG. 1 is a block diagram of a PLB-AXI bridge implementation of the present invention;

FIG. 2 is a schematic diagram of protocol fast conversion for a two-stage pipeline;

FIG. 3 is a schematic diagram of a cache to avoid multiple access congestion;

FIG. 4 is a timing diagram of a PLB-AXI bridge write transition;

FIG. 5 is a timing diagram of a PLB-AXI bridge read transition.

Detailed Description

The invention provides a high-performance and high-reliability conversion bridge from a PLB bus system to an AXI bus system, which supports the access conversion from a PLB6 bus interface to a standard AXI3/AXI4 interface.

Referring to fig. 1, a PLB-AXI bus conversion bridge according to the present invention includes a PLB slave interface unit 100, a protocol conversion control unit 200, an AXI master interface unit 300, a register unit 400, and a constant processing unit 500.

The protocol conversion control unit 200 is connected to the PLB bus via the PLB slave interface unit 100, the PLB slave interface unit 100 is connected to the AXI bus via the AXI master interface unit 300, the AXI master interface unit 300 is connected to the DCR interface via the register unit 400, and the AXI master interface unit 300 is connected to the exception/interrupt interface via the exception handling unit 500.

The PLB slave interface unit 100 implements the partitioning of the PLB access protocol interfaces for processing the PLB interface signals; the method comprises the following steps:

the command/address interface 101 is used for receiving command/address signals, the write data interface 102 is used for receiving write data signals and the read data interface 103 is used for sending read data signals;

the protocol conversion control unit 200 realizes the complete conversion from the PLB protocol to the AXI protocol; the method comprises the following steps:

the PLB protocol parsing unit 201 implements parsing and selection of PLB command/address and read-write data protocols.

And a write channel unit 202, configured to receive the write protocol that is analyzed by the PLB protocol analysis unit 201, and allocate the write protocol to a corresponding write channel, which includes a write command/address channel, a write data channel, and a write response channel.

The write command/address FIFO unit 203 is used for receiving and buffering command information sent by the write command/address channel in the write channel unit 202.

And the write data FIFO unit 204 is configured to receive and buffer data sent by the write data channel in the write channel unit 202.

A read channel unit 205, configured to receive the read protocol analyzed by the PLB protocol analyzing unit 201, and allocate the read protocol to a corresponding read channel, which includes a read command/address channel, a read data channel, and a read response channel.

The read command/address FIFO unit 206 is used to receive and buffer command information sent by the read command/address channel in 205.

The read data FIFO unit 207 is used to transmit the data received and buffered from the AXI protocol parsing unit 208 to the read data channel in 202.

The AXI protocol parsing unit 208 is configured to implement parsing and selection of an AXI protocol, implement obtaining a command or data from the

units

203, 204, and 208, parse the command or data into an AXI protocol, send the AXI protocol to the AXI master interface unit 300, and in addition, 208 may also receive data sent by the AXI master interface unit 300 and buffer the data into 207;

the AXI master interface unit 300 is capable of implementing the partitioning of an AXI access protocol interface for processing AXI interface signals;

the AXI master interface unit 300 includes:

the address interface 301 is for transmitting address signals, the write data interface 302 is for transmitting write data signals and the read data interface 303 is for receiving read data signals.

The register unit 400 is used for registering the internal working state information of the protocol conversion control unit 200, and accessing the register unit 400 through a DCR interface outside the conversion bridge, so as to obtain the current working state of the conversion bridge;

the exception handling unit 500 is configured to implement processing of exception information of the internal work of the protocol conversion control unit 200, generate an exception or an interrupt, and send the exception or the interrupt to an exception/interrupt interface, thereby perfecting an error reporting mechanism of the conversion bridge and improving reliability.

A working method of a PLB-AXI bus conversion bridge comprises the following steps:

s1, peripheral PLB bus initiates access, and is processed by PLB slave interface unit 100, and divided into command/address interface 101, write data interface 102 and read data interface 103;

and S2, entering the protocol conversion control unit 200 by the divided PLB interface, and analyzing the interface into write access and read access by the PLB protocol analysis unit 201. The write access is divided into write command/address, write data and write response, which enter the write channel unit 202 respectively, and are processed according to the corresponding channels, the write command/address is stored in the write command/address FIFO 203, the write data and the write response are stored in the write data FIFO 204, and are converted into the write access timing sequence of AXI through the AXI protocol analysis unit 208; the read access is divided into read command/address, read data and read response, which enter the read channel unit 205 respectively, and are processed according to the corresponding channel, the read command/address is stored in the read command/address FIFO 206, the read data and the read response acquired by the AXI protocol analysis unit 208 from the AXI interface 300 are stored in the read data FIFO207, and are taken out by the read data and the read response channel in the read channel unit, and are converted into the PLB read timing sequence, and then are transmitted to the PLB protocol analysis unit 201;

s3, the working state of the protocol conversion control unit 201 enters the register unit 400, and is sent to the DCR interface; the exception generated in the work enters the exception handling unit 500 and is sent to the exception/terminal interface;

s4, the AXI access generated by the protocol conversion control unit 201 is processed by the AXI interface 300, and divided into an address interface 301, a write data interface 302, and a read data interface 303, to initiate access to the peripheral AXI bus.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, the two-stage pipelined protocol fast conversion strategy of the present invention is directed to the access characteristics of two buses, the first stage is command/address protocol conversion, and the second stage is data protocol conversion. PLB bus initiation is divided into command/address access and data access procedures, whereas AXI bus access is divided into address access, data access and acknowledgement procedures. Therefore, for the access characteristics of the two buses, the two buses can be regarded as two-stage access, and a two-stage pipeline strategy is adopted in design to convert protocols, namely the conversion of AXI address access is synchronously realized in the PLB bus command/address access process, and the address access to AXI is initiated with the minimum time delay. And after the first-level access conversion is finished, entering a data access conversion process, immediately starting the conversion of the data access, initiating the data access to the AXI with the minimum time delay, analyzing the AXI response process by a conversion bridge, reporting the access result of the processor in a specific abnormal mode, and finishing the second-level access conversion. And a conversion mode of two-stage pipelining is adopted, so that the conversion time overhead is greatly reduced.

Referring to fig. 3, the caching strategy for avoiding multiple access congestion according to the present invention is divided into a command/address FIFO and a data FIFO.

The depth of the command/address FIFO is n, the width can meet the storage requirements of commands and addresses, the depth of the data FIFO is the same as that of the command/address FIFO, the width is the data volume m of one-time maximum Burst access, and each row of data corresponds to each row of command/addresses one to one. And storing the multiple access commands/addresses and the access data into the FIFO according to the sequence, and taking out the multiple access commands/addresses and the access data in sequence according to the sequence for conversion. The problem of access congestion caused by untimely processing can be solved, access loss caused by congestion can be effectively prevented, and the conversion reliability is greatly improved.

Referring to FIG. 4, the write transition timing for the PLB-AXI bridge is shown. Take the example of accessing data for 8 beats. The PLB slave port initiates write access with Burst of 8 through a command address channel, after the write access is converted by the PLB-AXI bridge, the AXI master port initiates write access with Burst of 8 to peripheral slave equipment through the address channel, the PLB master port sends 8 times of write data to the PLB-AXI bridge through a write data channel, and after the write data is converted into an AXI write time sequence, the write data is sent to the AXI master port through an AXI data channel, and one-time write conversion is realized.

Referring to FIG. 5, FIG. 5 shows the read transition timing of the PLB-AXI bridge. Take the example of accessing data for 8 beats. The PLB slave interface initiates read access with Burst of 8 through a command address channel, after PLB-AXI bridge conversion, the AXI master interface initiates read access with Burst of 8 to peripheral slave equipment through the address channel, 8 times of data are obtained through the AXI data channel, after 8 times of data are converted into PLB read time sequence, the PLB slave interface is sent to through a PLB read data channel, and once read conversion is realized. According to the PLB-AXI bridge implementation structure in fig. 1, the PLB-AXI high-performance high-reliability bus conversion bridge described in the present invention can be obtained by using the two-stage pipelining protocol fast conversion policy in fig. 2 and the multi-access congestion avoidance cache policy in fig. 3.

The invention is successfully applied to a high-performance SoC chip which takes double PowerPC processors as processing cores and multiple DSPs as fast computing cores. The PLB6 bus controller of the double PowerPC processor core can realize the rapid conversion from the PLB6 bus protocol to the AXI bus protocol through the conversion bridge of the invention, thereby realizing the high-efficiency access to a plurality of high-performance AXI interface peripherals in the AXI bus system. And all AXI standard interfaces can be compatible with peripheral IP unconditionally, so that the integration of the SoC system is simplified, and the design complexity is reduced.

In summary, the PLB-AXI bus conversion bridge of the present invention can ensure the correctness of protocol conversion, realize the high efficiency of protocol conversion, realize conversion with the least time overhead and the least delay, solve the problem of short-time multiple access congestion, prevent the phenomena of effective access loss, etc., and fully consider high efficiency and high reliability.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A PLB-AXI bus translation bridge, comprising:

the PLB slave interface unit (100) realizes the division of the PLB access protocol interface and is used for processing the PLB interface signal;

a protocol conversion control unit (200) for realizing the complete conversion from the PLB protocol to the AXI protocol;

an AXI master interface unit (300) that implements the partitioning of an AXI access protocol interface for processing AXI interface signals;

the protocol conversion control unit (200) is connected with a PLB bus through a PLB slave interface unit (100), the PLB slave interface unit (100) is connected with an AXI bus through an AXI master interface unit (300), the AXI master interface unit (300) is connected with a DCR interface through a register unit (400), and the AXI master interface unit (300) is connected with an exception/interrupt interface through an exception processing unit (500);

the register unit (400) is used for registering the internal working state information of the protocol conversion control unit (200), accessing the register unit (400) through a DCR interface outside the conversion bridge and acquiring the current working state of the conversion bridge;

the exception handling unit (500) is used for processing the internal work exception information of the protocol conversion control unit (200), generating exception or interrupt and sending the exception or interrupt to an exception/interrupt interface;

2. The PLB-AXI bus translation bridge of claim 1, wherein the protocol fast translation policy for two-level pipelining is specifically:

3. The PLB-AXI bus translation bridge of claim 1, wherein the caching policy to avoid multiple access congestion is specifically:

4. The PLB-AXI bus translation bridge of claim 3, wherein the command/address FIFO has a depth of n and a width that satisfies the memory requirements of commands and addresses for caching multiple access commands/addresses;

5. The PLB-AXI bus conversion bridge of claim 1, characterized in that the PLB slave interface unit (100) comprises a command/address interface (101), a write data interface (102) and a read data interface (103), the command/address interface (101) being arranged to receive command/address signals, the write data interface (102) being arranged to receive write data signals and the read data interface (103) being arranged to transmit read data signals.

6. The PLB-AXI bus conversion bridge of claim 1, characterized in that the protocol conversion control unit (200) comprises a PLB protocol resolution unit (201), a write channel unit (202), a write command/address FIFO unit (203), a write data FIFO unit (204), a read channel unit (205), a read command/address FIFO unit (206), a read data FIFO unit (207), and an AXI protocol resolution unit (208); the PLB protocol analysis unit (201) is respectively connected with the writing channel unit (202) and the reading channel unit (205), and the writing channel unit (202) is respectively connected with the AXI protocol analysis unit (208) through the writing command/address FIFO unit (203) and the writing data FIFO unit (204); the read channel unit (205) is connected to the AXI protocol resolution unit (208) via a read command/address FIFO unit (206) and a read data FIFO unit (207), respectively.

7. The PLB-AXI bus translation bridge according to claim 6, wherein the PLB protocol parsing unit (201) is adapted to implement the parsing and selection of PLB command/address and read-write data protocols; the write channel unit (202) is used for receiving the write protocol analyzed by the PLB protocol analysis unit (201) and distributing the write protocol to corresponding write channels, wherein the write channels comprise a write command/address channel, a write data channel and a write response channel; the write command/address FIFO unit (203) is used for receiving and buffering command information sent by a write command/address channel in the write channel unit (202); the write data FIFO unit (204) is used for receiving and buffering data sent by a write data channel in the write channel unit (202); the read channel unit (205) is used for receiving the read protocol analyzed by the PLB protocol analysis unit (201) and distributing the read protocol to corresponding read channels, wherein the read channels comprise a read command/address channel, a read data channel and a read response channel; the read command/address FIFO unit (206) is used for receiving and buffering command information sent by a read command/address channel in the buffer (205); a read data FIFO unit (207) for transmitting the data received and buffered from the AXI protocol parsing unit (208) to the read data channel in (202); the AXI protocol analysis unit (208) is used for realizing the analysis and selection of the AXI protocol, and realizing the acquisition of commands or data from the write command/address FIFO unit (203), the write data FIFO unit (204) and the AXI protocol analysis unit (208), and the analysis is carried out to the AXI protocol and the AXI protocol is sent to the AXI main interface unit (300).

8. The PLB-AXI bus conversion bridge of claim 7, wherein the AXI protocol resolution unit (208) receives a data buffer sent by the AXI master interface unit (300) into the read data FIFO unit (207).

9. The PLB-AXI bus conversion bridge of claim 1, characterized in that the AXI master interface unit (300) comprises an address interface (301), a write data interface (302), and a read data interface (303), the address interface (301) being for transmitting address signals, the write data interface (302) being for transmitting write data signals, the read data interface (303) being for receiving read data signals.

10. A method of operating the PLB-AXI bus conversion bridge of claim 1, comprising the steps of: