CN108897696B - Large-capacity FIFO controller based on DDRx memory - Google Patents

Large-capacity FIFO controller based on DDRx memory Download PDF

Info

Publication number
CN108897696B
CN108897696B CN201810622242.2A CN201810622242A CN108897696B CN 108897696 B CN108897696 B CN 108897696B CN 201810622242 A CN201810622242 A CN 201810622242A CN 108897696 B CN108897696 B CN 108897696B
Authority
CN
China
Prior art keywords
module
data
read
memory
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810622242.2A
Other languages
Chinese (zh)
Other versions
CN108897696A (en
Inventor
唐金锋
秦臻
唐雷雷
刘露
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Microelectronics Technology Institute
Original Assignee
Xian Microelectronics Technology Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Microelectronics Technology Institute filed Critical Xian Microelectronics Technology Institute
Priority to CN201810622242.2A priority Critical patent/CN108897696B/en
Publication of CN108897696A publication Critical patent/CN108897696A/en
Application granted granted Critical
Publication of CN108897696B publication Critical patent/CN108897696B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Abstract

The invention discloses a large-capacity FIFO controller based on a DDRx memory, which is characterized in that the memory is packaged with one or more asynchronous FIFO control modules, and the asynchronous FIFO control modules are connected with the memory through a memory interface sequential control module; the asynchronous FIFO control module comprises: the device comprises a write port synchronization module, a read port synchronization module, a write port access request module, a read-write pointer management module and a port scheduling polling module. The memory is packaged into an asynchronous FIFO controller interface, and when the memory is used as a first-in first-out data buffer, the application interface is simplified while the characteristics of large capacity space and high bandwidth of the memory are ensured.

Description

Large-capacity FIFO controller based on DDRx memory
Technical Field
The invention belongs to the technical field of FIFO controller architecture; in particular to a large capacity FIFO controller based on a DDRx memory.
Background
Currently, in the design and implementation processes of most electronic product projects, the data cache architecture of the FPGA plus the DDR2/DDR3 memory is increasingly applied. Although the FPGA manufacturers mostly provide the IP cores of the DDRx controller, for the FPGA designers, a lot of FPGA digital logic circuit design work is still required to complete the functions of data processing and internal interface timing of the DDRx controller, which not only increases the design difficulty of the project but also may affect the project progress.
The scheme provided by the prior art is that an FPGA is connected with two DDRx chips, and data is transmitted uninterruptedly by using a ping-pong operation mode.
The FPGA supplier provides a part of FPGA with a controller IP of a DDRx interface based on an FIFO interface, but the control sequence is complex, and the controller IP can only be applied to a plurality of specific FPGA chips and has no universality.
Disclosure of Invention
The invention provides a large-capacity FIFO controller based on a DDRx memory; the memory is packaged into an asynchronous FIFO controller interface, and when the memory is used as a first-in first-out data buffer, the application interface is simplified while the large capacity and high bandwidth characteristics of the DDRx memory are ensured.
The technical scheme of the invention is as follows: a large-capacity FIFO controller based on a DDRx memory comprises one or more asynchronous FIFO control modules, wherein the asynchronous FIFO control modules are connected with the memory through a port scheduling polling module and a memory interface time sequence control module; the asynchronous FIFO control module comprises: the device comprises a write port synchronization module, a read port synchronization module, a write port access request module, a read port access request module and a read-write pointer management module; the write port synchronization module synchronizes the data written into the FIFO controller to the memory interface timing sequence control module through the port scheduling polling module; the read port synchronization module reads the data of the FIFO controller from the memory interface timing sequence control module through the port scheduling polling module and buffers the data; the write port access request module is used for acquiring the number of data which needs to be written into the memory by the write port synchronization module and initiating a write access request to the port scheduling polling module; the read port access request module is used for acquiring the number of data which can be read in the memory by the read port synchronization module and initiating a read access request to the port scheduling polling module; the port scheduling polling module polls the read-write access request of each asynchronous FIFO control module to the memory; and the memory interface timing control module responds to the read or write operation request of the asynchronous FIFO control module and correspondingly accesses the DDRx storage area.
Furthermore, the invention is characterized in that:
the asynchronous FIFO control module also comprises a read-write pointer management module, and the read-write pointer management module finishes the read-write pointer operation of the FIFO controller and calculates the number of data in the FIFO controller; after the data reading or writing operation is carried out, the reading and writing pointer management module updates the number of the data in the FIFO controller and the reading and writing address of the memory.
The data read out from the read port synchronization module is the data pointed by the read pointer of the read-write pointer management module.
The process of acquiring the number of data which needs to be written into the memory by the write port synchronization module in the write port access request module is as follows: acquiring the number n of data to be transmitted, wherein when the remaining space of the memory can store n data, the number of the data of the write request output by the write port access request module is n; when m data can be stored in the remaining space of the memory, and m is less than n, the number of the data of the write request output by the write port access request module is m.
The specific process of the read port access request module acquiring the number of data which can be written into the read port synchronization module in the memory is as follows: acquiring the number x of data to be transmitted, wherein when the residual space in the read port synchronization module can store x data, the number of the data of the read request output by the read port access request module is x; when the remaining space in the read port synchronization module can store y data, and y < x, the number of data of the read request output by the read port access request module is y.
The memory interface time sequence control module reads out the data in the memory and writes the data into the read port synchronization module when in corresponding read operation.
And the memory interface time sequence control module reads the data in the write port synchronization module and writes the data into the memory during corresponding write operation.
Compared with the prior art, the invention has the beneficial effects that: the FIFO controller is the same as a standard asynchronous FIFO interface, and the interface is universal, simple and convenient to use; the invention adopts burst transmission and pipeline design technology, namely, adopts a memory interface time sequence control module and a port scheduling polling module to realize polling read-write operation on a plurality of asynchronous FIFO control modules, improves the transmission efficiency of data, and ensures the high bandwidth of read-write access of the memory; the FIFO controller is configured into 1 or more asynchronous FIFO control modules, is flexible in configuration and is suitable for use scenes with different bandwidths.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
In the figure: 1 is a write port synchronization module; 2 is a read-write pointer management module; 3 is a write port access request module; 4 is read port access request module; 5 is a read port synchronization module; 6 is a port scheduling polling module; and 7, a memory interface timing control module.
Detailed Description
The technical solution of the present invention is further explained with reference to the accompanying drawings and specific embodiments.
The invention provides a large-capacity FIFO controller based on a DDRx memory, which comprises one or more asynchronous FIFO control modules, wherein the asynchronous FIFO control modules are connected with the memory through a port scheduling polling module 6 and a memory interface time sequence control module 7. As shown in fig. 1, the FIFO controller in this embodiment has two asynchronous FIFO control blocks.
As shown in fig. 1, the asynchronous FIFO control module includes a port synchronization module 1, a read port synchronization module 5, a write port access request module 3, a read port access request module 4, and a read-write pointer management module 2.
The write port synchronization module 1 is used for synchronizing the data written by the FIFO controller to the memory interface timing control module 7 and writing the data into the memory; the module is realized by an asynchronous FIFO control module, when the data needing to be written in by the write port synchronous module 1 meets the condition of writing in DDRx, the port scheduling polling module 6 reads out the data in the write port synchronous module 1 and writes the data into the memory through the memory interface time sequence control module 7.
The read port synchronization module 5 is configured to read out and buffer data (i.e., data pointed by the read pointer) that needs to be read by the FIFO controller from a memory; this module is implemented by an asynchronous FIFO control module, which is operated by the user to read data from the synchronous module 5 when the user needs to read data from the FIFO control.
The write port access request module 3 calculates the number of data that the write port synchronization module 1 needs to write into the memory by judging the number of data in the write port synchronization module 1, the number of data in the memory and the data timeout condition in the write port synchronization module, and initiates a DDRx write access request to the port scheduling polling module 6.
The process of acquiring the number of data to be written into the memory by the write port synchronization module 1 in the write port access request module 3 is as follows: acquiring the number n of data to be transmitted, wherein when the remaining space of the memory can store n data, the number of data of the write request output by the write port access request module 3 is n; when m data can be stored in the remaining space of the memory, and m is less than n, the number of the data of the write request output by the write port access request module 3 is m.
The read port access request module 4 calculates the number of data that can be written into the read port synchronization module 5 in the memory by judging the number of data in the read port synchronization module 5, the number of data in the memory and the data timeout condition in the memory, and initiates a DDRx read access request to the port scheduling polling module 6.
The specific process of the read port access request module 4 acquiring the number of data that can be written into the read port synchronization module 5 in the memory is as follows: acquiring the number x of data to be transmitted, wherein when the residual space in the read port synchronization module 5 can store x data, the number x of data of the read request output by the read port access request module 4 is acquired; when the remaining space in the read port synchronization module 5 can store y data, and y < x, the number of data of the read request output by the read port access request module 4 is y.
The port scheduling polling module 6 is a core control module, polls read/write access requests of each asynchronous FIFO control module to the memory through a state machine, when a certain asynchronous FIFO control module has a read/write access request, jumps to a corresponding processing state to respond to the request, and controls the memory interface timing sequence control module 7 to write the requested data from the write port synchronization module 1 to the address pointed by the write pointer of the FIFO controller in the memory, or read and cache the address data pointed by the read pointer of the FIFO controller in the read port synchronization module 5.
The read-write pointer management module 2 is responsible for realizing the read-write pointer calculation of the FIFO controller and calculating the data number in the asynchronous FIFO control module in real time, and when data is read out from the memory or written into the memory, the read-write address update and the data number update of the DDRx are carried out.
The memory interface timing control module 7 responds to the read-write operation request to complete the read-write access of the memory. When responding to a write data operation request, reading and writing data in the write port synchronization module 1 into a memory; in response to a read data operation, data in the memory is read out and written into the read port synchronization module 5.
Preferably, the memory provided by the invention is a DDR2 memory or a DDR3 memory, and the corresponding memory interface timing control module 7 is a DDR2 or DDR3 interface timing control module, so that the DDR2 or DDR3 memory can be operated correspondingly.
As shown in fig. 1, the FIFO controller of the present invention has two asynchronous FIFO control modules symmetrically distributed on the left and right, and its operation mode is: the write port synchronization module 1 of the same asynchronous FIFO control module (left or right asynchronous FIFO control module) synchronizes the data written by it to the memory interface timing control module 7, and when the data of the write port synchronization module 1 reaches the condition of writing into the memory, the port scheduling polling module 6 reads out and writes the data in the write port synchronization module 1 into the memory. The read-write pointer management module 2 of the same asynchronous FIFO control module is used for realizing the read-write pointer calculation of the asynchronous FIFO control module and calculating the number of data in the asynchronous FIFO control module, and when data is read out from or written into the memory, the read-write address in the memory is updated and the number of data in the memory is updated.
Specifically, when the write port of the write port synchronization module 1 of the asynchronous FIFO control module continuously writes data, the write port access request module 3 will wait until the number of data in the write port synchronization module 1 reaches a set value (for example, set to 64) data, and initiate a request for writing into the memory, which can make the data written into the channel realize burst transmission as much as possible, thereby improving the bus utilization rate and transmission bandwidth of the write channel, when the number of data required to be written into the write port is less than the set value (64), the write port access request module 3 sets a timeout value (for example, 512 ns), and when the time of data stored in the write port synchronization module 1 exceeds 512ns, the write port access request module 3 also initiates a write request for writing data into the memory, thereby ensuring that the data delay from the write port to the read port of the same asynchronous FIFO control module is within a certain range. The calculation mode of the data number of the write-in request is as follows: obtaining the number n of data to be transmitted according to the above manner, and when the remaining space of the memory can store n data, the number of data of the write request of the write port access request module 3 is n; when the remaining space of the memory can store m data, and m < n, the number of data of the write request of the write port access request module 3 is m.
The read port access request module 4 of the same asynchronous FIFO control module calculates the number of data transmitted from the memory to the read port synchronization module 5, when the effective data in the memory continuously increases, the read port access request module 4 will wait until the data in the DDRx cache area of the asynchronous FIFO control module reaches a set value (for example, 64) data, and then initiate a request for reading the data in the memory, and the processing mode can realize burst transmission of the data of the read channel as much as possible, and improve the bus utilization rate and transmission bandwidth of the read channel; when the number of data in the DDRx buffer area of the asynchronous FIFO control module is less than 64, the read port access request module 4 has a settable timeout value (e.g. 512 ns), and when the time for storing the data in the DDRx buffer area exceeds 512ns, the read port access request module 4 will initiate an operation application for reading the data in the memory, thereby ensuring that the data delay from the write port to the read port of the asynchronous FIFO control module is within a certain range. The method for calculating the data number of the read request comprises the following steps: obtaining the number x of data to be transmitted according to the manner of generating the read request, wherein when the remaining space of the read port synchronization module 5 can store x data, the number of data of the read request output by the read port access request module 4 is x; when the remaining space of the read port synchronization module 5 can store y data and y is less than x, the number of data of the read request output by the read port access request module 4 is y.
And a read port synchronous module 5 of the same asynchronous FIFO control module reads out and buffers the data pointed by the read pointer of the asynchronous FIFO control module from the memory, and when a user needs to read out the data from the asynchronous FIFO control module, the user reads out the data by operating the read port.
The port scheduling polling module 6 is a core control module of the FIFO controller, polls read-write access requests to the memory from four ports (2 read ports and 2 write ports) of two asynchronous FIFO control modules through a state machine, and when a certain read-write port has a corresponding access request and the number of data requested to be transmitted is greater than 0, jumps to a corresponding processing state to respond to the request. The module adopts a method of polling one port by one on average when in polling scheduling, the priority of each port is the same, and the data of each port can be ensured to be effectively transmitted and processed within the range allowed by the bandwidth. In the data transmission process, the FIFO is read and written, and meanwhile, the time sequence of the application interface of the memory is generated in a pipeline mode, so that the data transmission efficiency is maximized.
And the memory interface timing control module 7 is used for realizing the timing conversion of data transmission when the port scheduling polling module 6 responds to the read-write operation request. Reading out the data in the write port synchronization module 1 and writing the data into a memory when responding to the write data operation request; in response to a read data operation, data in the memory is read out and written into the read port synchronization module 5.
According to the high-capacity FIFO controller provided by the invention, the logic design of the controller is described by using Verilog HDL language, and the high-capacity FIFO controller is applied to the design of a certain double-channel video acquisition card product and is used for testing the function and the performance of the controller. The test result shows that the invention has good implementability and the performance meets the expectation.

Claims (7)

1. A large capacity FIFO controller based on DDRx memorizer, characterized by that, include one or more asynchronous FIFO control module, and asynchronous FIFO control module dispatches polling module (6) and memorizer interface sequential control module (7) and connects with memorizer through the port;
the asynchronous FIFO control module comprises: the device comprises a write port synchronization module (1), a read port synchronization module (5), a write port access request module (3), a read port access request module (4) and a read-write pointer management module (2);
the write port synchronization module (1) synchronizes the data written into the FIFO controller to the memory interface timing sequence control module (7) through the port scheduling polling module (6);
a read port synchronization module (5) which reads out and buffers the data of the FIFO controller from a memory interface timing sequence control module (7) through a port scheduling polling module (6);
the write port access request module (3) is used for acquiring the number of data which need to be written into the memory by the write port synchronization module (1) and initiating a write access request to the port scheduling polling module (6);
the read port access request module (4) is used for acquiring the number of data in the memory which can be read by the read port synchronization module (5) and initiating a read access request to the port scheduling polling module (6);
the port scheduling polling module (6) polls the read or write access request of each asynchronous FIFO control module to the memory;
and the memory interface timing control module (7) responds to the read or write operation request of the asynchronous FIFO control module and correspondingly accesses the DDRx storage area.
2. A large capacity FIFO controller based on a DDRx memory according to claim 1, wherein said asynchronous FIFO control module further comprises a read-write pointer management module (2), said read-write pointer management module (2) completing pointer operations for reading or writing of the FIFO controller and counting the number of data in the FIFO controller; after the data reading or writing operation is carried out, the reading-writing pointer management module (2) updates the number of data in the FIFO controller and the reading-writing address of the memory.
3. A large capacity FIFO controller in accordance with claim 2, wherein the data read out in the read port synchronizing module (5) is the data pointed to by the read pointer of the read-write pointer management module (2).
4. A large capacity FIFO controller based on a DDRx memory according to claim 1, wherein the process of getting the number of data that needs to be written into the memory by the write port synchronization module (1) in the write port access request module (3) is: acquiring the number n of data to be transmitted, wherein when the remaining space of the memory can store n data, the number of the data of the write request output by the write port access request module (3) is n; when m data can be stored in the remaining space of the memory, and m is less than n, the number of the data of the write request output by the write port access request module (3) is m.
5. A large capacity FIFO controller based on DDRx memory of claim 1 wherein, the specific process of the read port access request module (4) to get the number of data in the memory that can be written into the read port synchronization module (5) is: acquiring the number x of data to be transmitted, wherein when the residual space in the read port synchronization module (5) can store x data, the number of the data of the read request output by the read port access request module (4) is x; when the remaining space in the read port synchronization module (5) can store y data, and y < x, the number of data of the read request output by the read port access request module (4) is y.
6. A large capacity FIFO controller in accordance with claim 1, wherein the memory interface timing control module (7) reads out data in the memory and writes it into the read port synchronization module (5) at the time of the corresponding read operation.
7. A DDRx-memory-based large-capacity FIFO controller according to claim 1, wherein said memory interface timing control module (7) reads out data in the write port synchronization module (1) and writes it into the memory at the time of the corresponding write operation.
CN201810622242.2A 2018-06-15 2018-06-15 Large-capacity FIFO controller based on DDRx memory Active CN108897696B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810622242.2A CN108897696B (en) 2018-06-15 2018-06-15 Large-capacity FIFO controller based on DDRx memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810622242.2A CN108897696B (en) 2018-06-15 2018-06-15 Large-capacity FIFO controller based on DDRx memory

Publications (2)

Publication Number Publication Date
CN108897696A CN108897696A (en) 2018-11-27
CN108897696B true CN108897696B (en) 2022-11-29

Family

ID=64345309

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810622242.2A Active CN108897696B (en) 2018-06-15 2018-06-15 Large-capacity FIFO controller based on DDRx memory

Country Status (1)

Country Link
CN (1) CN108897696B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111581132B (en) * 2020-04-27 2022-03-25 武汉中科牛津波谱技术有限公司 Extensible multiport DDR3 controller based on FPGA
CN112416823B (en) * 2020-11-15 2024-05-03 珠海一微半导体股份有限公司 Sensor data read-write control method, system and chip in burst mode

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103198856A (en) * 2013-03-22 2013-07-10 烽火通信科技股份有限公司 DDR (Double Data Rate) controller and request scheduling method
CN106959929A (en) * 2017-03-17 2017-07-18 数据通信科学技术研究所 Memory and its method of work that a kind of multiport is accessed

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7610433B2 (en) * 2004-02-05 2009-10-27 Research In Motion Limited Memory controller interface

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103198856A (en) * 2013-03-22 2013-07-10 烽火通信科技股份有限公司 DDR (Double Data Rate) controller and request scheduling method
CN106959929A (en) * 2017-03-17 2017-07-18 数据通信科学技术研究所 Memory and its method of work that a kind of multiport is accessed

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
基于FPGA的DDR3 SDRAM控制器设计;董岱岳;《中国优秀硕士学位论文全文数据库（信息科技辑）》;20160215(第2期);I137-30 *
基于FPGA的DDR3多端口读写存储管理设计;吴连慧 等;《单片机与嵌入式系统应用》;20150310(第1期);71-74 *

Also Published As

Publication number Publication date
CN108897696A (en) 2018-11-27

Similar Documents

Publication Publication Date Title
CN112035389B (en) PLB-AXI bus conversion bridge and working method thereof
KR102520983B1 (en) Acceleration control system based on binarization algorithm, chip and robot
CN109800193B (en) Bridging device of SRAM on AHB bus access chip
US20070055813A1 (en) Accessing external memory from an integrated circuit
CN110058816B (en) DDR-based high-speed multi-user queue manager and method
CN114490460B (en) FLASH controller for ASIC and control method thereof
CN108897696B (en) Large-capacity FIFO controller based on DDRx memory
GB2500082A (en) Delaying the transmission of data from a memory device until the output buffer of the memory device contains the data for the transfer
CN115905086A (en) Control method and controller for synchronously reading and writing single-port SRAM (static random Access memory) based on AXI (advanced extensible interface)
CN113900974A (en) Storage device, data storage method and related equipment
CN114827048B (en) Dynamic configurable high-performance queue scheduling method, system, processor and protocol
US20240021239A1 (en) Hardware Acceleration System for Data Processing, and Chip
US7913013B2 (en) Semiconductor integrated circuit
CN116107923B (en) BRAM-based many-to-many high-speed memory access architecture and memory access system
US7774513B2 (en) DMA circuit and computer system
CN112286863B (en) Processing and memory circuit
CN112100098B (en) DDR control system and DDR memory system
CN115237349A (en) Data read-write control method, control device, computer storage medium and electronic equipment
US8301816B2 (en) Memory access controller, system, and method
CN111723027B (en) Dynamic storage buffer area reading control method based on power edge gateway
CN112231261A (en) ID number compression device for AXI bus
KR20210061583A (en) Adaptive Deep Learning Accelerator and Method thereof
Zhao et al. A Novel Design of High-speed Multi-port Memory Interface for Digital Signal Processor
Nguyen et al. A flexible high-bandwidth low-latency multi-port memory controller
CN115328832B (en) Data scheduling system and method based on PCIE DMA

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant