CN112019217B

CN112019217B - Pipelined successive approximation analog-to-digital converter and conversion method

Info

Publication number: CN112019217B
Application number: CN202011106318.XA
Authority: CN
Inventors: 金泽人; 陈华; 王志宇; 郁发新
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2020-10-16
Filing date: 2020-10-16
Publication date: 2021-02-12
Anticipated expiration: 2040-10-16
Also published as: CN112019217A

Abstract

The invention provides a pipeline type successive approximation analog-to-digital converter and a conversion method, comprising the following steps: the system comprises a first-stage successive approximation analog-to-digital conversion module, a second-stage successive approximation analog-to-digital conversion module and a digital code error correction logic module; the first-stage successive approximation analog-to-digital conversion module comprises a first capacitor array unit, an amplifying unit, a latching comparing unit, a first register logic control unit and a control switch, wherein the amplifying unit is multiplexed into a residual error amplifier and a preamplifier of a comparator in the first-stage successive approximation analog-to-digital converter. According to the invention, the input offset voltage mismatch between the two is completely eliminated by multiplexing the residual error amplifier preamplifier, the input swing amplitude of the residual error amplifier is stabilized, the linearity of the residual error amplifier is improved, and the chip area is saved; gain errors are obtained by multiplexing the second-stage successive approximation type analog-to-digital conversion module, the gain errors of the residual error amplifier are reduced, and the conversion accuracy of the whole pipelined successive approximation type analog-to-digital converter is improved.

Description

Pipelined successive approximation analog-to-digital converter and conversion method

Technical Field

The present invention relates to the field of circuit design, and in particular, to a pipeline successive approximation analog-to-digital converter and a conversion method thereof.

Background

The pipelined successive approximation analog-to-digital converter has the characteristics of low power consumption of the successive approximation analog-to-digital converter, high throughput rate and low noise of the pipelined analog-to-digital converter, and is widely applied to the application scenarios of the analog-to-digital converter with medium precision and medium speed.

As shown in fig. 1, a common two-stage pipelined successive approximation analog-to-digital converter 1 generally uses an open-loop operational amplifier as a residual error amplifier 12 behind a first-stage successive approximation analog-to-digital converter 11, amplifies a residual error voltage of the first-stage successive approximation analog-to-digital converter 11, and sends the amplified residual error voltage to a second-stage successive approximation analog-to-digital converter 13; the first-stage successive approximation type analog-to-digital converter 11 and the second-stage successive approximation type analog-to-digital converter 13 both comprise a capacitor array 15, a comparator 16 and a register and logic control unit 17; the output signals of the first successive approximation type analog-to-digital converter 11 and the second successive approximation type analog-to-digital converter 13 are processed by the digital code error correction logic unit 14 to output the final code word.

The structure has two problems, namely, the open-loop operational amplifier is easily influenced by external environment, so that the gain is inaccurate and unstable; secondly, the input offset voltage of the comparator inside the first-stage successive approximation type analog-to-digital converter 11 and the input offset voltage of the residual error amplifier have mismatch, so that the input swing amplitude of the residual error amplifier is increased, and the linearity of the operational amplifier is reduced. This effect on the pipelined successive approximation analog-to-digital converter is quite large because: (1) compared with a closed-loop operational amplifier, the linearity of the open-loop operational amplifier is more sensitive to the input swing amplitude; (2) in order to suppress the non-linear error under the operating condition of the op-amp open loop, the conversion accuracy of the first successive approximation type adc 11 is usually increased to maintain the energy utilization rate of the successive approximation type adc and limit the input swing of the op-amp, thereby reducing the voltage of the minimum quantization unit (LSB) and the effect of gain redundancy.

In the prior art, analog-to-digital converters are grouped, and mismatch of gain and offset voltage between analog-to-digital converter arrays is eliminated through a chain cycle estimation method. However, in this scheme, a complex analog-to-digital converter is integrated, and a Least Mean Square error (LMS) filter bank is added, so that the chip area is still greatly increased, and the LMS filter bank has a slow iteration speed, which affects the performance iteration convergence speed of the analog-to-digital converter.

The prior art also discloses interstage gain calibration methods of some cascaded analog-to-digital converters, which all need a large number of additional circuit modules to realize the calibration function, and have the problem of increased production cost caused by increased chip area.

Therefore, how to eliminate the gain mismatch and the offset voltage mismatch without increasing the chip area by a large area has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pipeline successive approximation analog-to-digital converter and a conversion method thereof, which are used to solve the problems of gain mismatch, offset voltage mismatch, large chip area, etc. in the prior art.

To achieve the above and other related objects, the present invention provides a pipelined successive approximation analog-to-digital converter, comprising:

the first-stage successive approximation analog-to-digital conversion module is used for performing analog-to-digital conversion on the input voltage to obtain a high-order code word;

the second-stage successive approximation analog-to-digital conversion module is connected to the output end of the first-stage successive approximation analog-to-digital conversion module and is used for performing analog-to-digital conversion on the residual voltage of the first-stage successive approximation analog-to-digital conversion module to obtain a low-order code word;

the digital code error correction logic module is connected with the output ends of the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module, and is used for adding the high-order code words and the low-order code words and removing redundant bits to obtain output code words;

the first-stage successive approximation analog-to-digital conversion module comprises a first capacitor array unit, an amplifying unit, a latching comparison unit, a first register logic control unit and a control switch;

the first capacitor array unit is connected with the input voltage, samples the input voltage, and redistributes charges based on the sampled voltage, a first reference voltage and a reference ground connection mode;

the amplifying unit is connected with the output end of the first capacitor array unit, and is used as a preamplifier for amplifying the signal output by the first capacitor array unit in the conversion phase of the first-stage successive approximation analog-to-digital conversion module; in the amplifying phase of the first-stage successive approximation analog-to-digital conversion module, the amplifying unit is used as a residual error amplifier between the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module, and amplifies the residual error voltage converted by the first-stage successive approximation analog-to-digital conversion module;

the latch comparison unit is connected to the output end of the amplification unit, compares the output signal of the amplification unit with a reference signal and outputs a first comparison result;

the first register logic control unit is connected with the output end of the latch comparison unit and the control end of the first capacitor array, controls each capacitor in the first capacitor array to be connected with the input voltage, the first reference voltage or the reference ground based on the first comparison result, and outputs the high-order code word;

one end of the control switch is connected with the output end of the amplifying unit, the other end of the control switch is used as the output end of the first-stage successive approximation analog-to-digital conversion module, the control switch is switched off when the first-stage successive approximation analog-to-digital conversion module works, and the control switch is switched on after the work is finished.

Optionally, the amplifying unit includes a differential flipped voltage follower circuit and a common-source amplifying circuit, and the common-source amplifying circuit is connected to an output end of the differential flipped voltage follower circuit.

More optionally, the differential flip voltage follower circuit includes first, second, third, fourth, fifth, and sixth transistors, first and second resistors, and first and second capacitors; the grid electrodes of the first transistor and the second transistor respectively receive differential signals output by the first capacitor array unit; the source electrode of the first transistor is grounded through the third transistor, the drain electrode of the first transistor is connected with a power supply voltage through the fifth transistor, and the drain electrode of the first transistor is used as a first output end and is connected with the grid electrode of the third transistor; the source electrode of the second transistor is grounded through the fourth transistor, the drain electrode of the second transistor is connected with a power supply voltage through the sixth transistor, and the drain electrode of the second transistor is used as a second output end and is connected with the grid electrode of the fourth transistor; the grid electrodes of the fifth transistor and the sixth transistor are connected with a common-mode feedback voltage; the first resistor and the second resistor are connected in series and then connected between the source electrodes of the first transistor and the second transistor, the first capacitor and the second capacitor are connected in series and then connected between the source electrodes of the first transistor and the second transistor, and the connection node of the first resistor and the second resistor is connected with the connection node of the first capacitor and the second capacitor.

More optionally, the amplifying unit further includes a common mode feedback circuit, where the common mode feedback circuit is connected to the output end of the common source amplifying circuit to obtain a fixed output common mode voltage and stabilize the voltage of each node of the amplifying unit.

More optionally, the second-stage successive approximation analog-to-digital conversion module includes a second capacitor array unit, a comparison unit, and a second register logic control unit;

the second capacitor array unit is connected with the output end of the first-stage successive approximation analog-to-digital conversion module, samples a signal obtained by amplifying a residual voltage output by the first-stage successive approximation analog-to-digital conversion module by a residual error amplifier, and redistributes charges based on the voltage obtained by sampling, a second reference voltage and a reference ground connection mode;

the comparison unit is connected with the output end of the second capacitor array unit, compares the signals output by the second capacitor array unit and outputs a second comparison result;

the second register logic control unit is connected to the output end of the comparison unit and the control end of the second capacitor array unit, controls each capacitor in the second capacitor array to be connected with the second reference voltage or reference ground based on the second comparison result, and outputs the low-order code word.

More optionally, the pipelined successive approximation analog-to-digital converter further includes an inter-stage coupling capacitor and a calibration capacitor DAC module;

the interstage coupling capacitor is connected between the output end of the first capacitor array unit and the input end of the amplifying unit;

the calibration capacitor DAC module is connected between the interstage coupling capacitor and the amplifying unit, the control end of the calibration capacitor DAC module is connected with the output end of the second register logic control unit, a gain calibration control signal generated based on the difference value of the highest bit voltage in the second capacitor array unit and the output voltage of the amplifying unit is obtained from the second register logic control unit, the capacitance value of the calibration capacitor DAC module is adjusted based on the gain calibration control signal, and then gain calibration is achieved.

More optionally, the calibration capacitor DAC module includes a first set of capacitors and a second set of capacitors, and the first set of capacitors and the second set of capacitors each include k capacitors; one end of each capacitor in the first group of capacitors and the second group of capacitors is connected between the interstage coupling capacitor and the amplifying unit, and the other end of each capacitor is grounded through a switch; the control end of each switch is connected with the gain calibration control signal; wherein k depends on the allowed gain error range of the residual amplifier, the value of k determining the gain adjustment range of the residual amplifier.

To achieve the above and other related objects, the present invention further provides a pipelined successive approximation analog-to-digital conversion method, which at least includes:

the first-stage successive approximation analog-to-digital conversion module performs analog-to-digital conversion on input voltage through sampling conversion to obtain a high-order code word, and at the moment, the amplifying unit is used as a preamplifier of a latch comparison unit in the first-stage successive approximation analog-to-digital conversion module;

after the first-stage successive approximation analog-to-digital conversion module completes analog-to-digital conversion, the amplifying unit is used as a residual error amplifier to amplify and output residual voltage of the first-stage successive approximation analog-to-digital conversion module;

the second-stage successive approximation analog-to-digital conversion module performs analog-to-digital conversion on the residual voltage output by the amplifying unit to obtain a low-order code word;

and the digital code error correction logic module adds the high-order code words and the low-order code words and removes redundant bits to obtain output code words.

Optionally, the pipelined successive approximation analog-to-digital conversion method further includes performing gain adjustment on the amplifying unit by adjusting a capacitance value at an input end of the amplifying unit, and satisfying the following relation:

A=（Ca/（Ccal+Ca））A₀；

wherein A is the actual gain of the amplification unit; ca is the capacitance value of an interstage coupling capacitor connected in series with the input end of the amplifying unit; ccal is a capacitance value of a calibration capacitor, one end of the calibration capacitor is connected between the interstage coupling capacitor and the input end of the amplifying unit, and the other end of the calibration capacitor is grounded; a. the₀Is the initial gain of the amplification unit.

More optionally, the method for adjusting the gain includes:

1) grounding a first group of capacitors in a calibration capacitor DAC module, suspending a second group of capacitors, and connecting the other ends of the capacitors in the first group of capacitors and the second group of capacitors to the input end of the amplifying unit;

2) resetting the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module;

3) obtaining the product of the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module and the actual gain of the amplifying unit through the output voltage of the amplifying unit;

4) acquiring a difference value between the output voltage of the amplifying unit and the highest bit voltage of the second-stage successive approximation analog-to-digital conversion module, grounding the capacitor of the highest bit in the second group of capacitors if the difference value is greater than zero to increase the value of the calibration capacitor, otherwise suspending the capacitor of the highest bit in the first group of capacitors to reduce the value of the calibration capacitor;

5) and repeating the steps 2), 3) and 4) to sequentially adjust the connection relation of the capacitors in the calibration capacitor DAC module according to the difference value and the weight from large to small, thereby realizing gain calibration.

More optionally, the resetting of the first-stage successive approximation analog-to-digital conversion module includes: the input voltage is short-circuited, and all capacitors in the first-stage successive approximation analog-to-digital conversion module are connected with a reference ground; the step of resetting the second-stage successive approximation analog-to-digital conversion module comprises the following steps: and all capacitors in the second-stage successive approximation type analog-to-digital converter are connected with a second reference voltage.

More optionally, the method for obtaining the product of the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module and the actual gain of the amplifying unit includes:

connecting the lowest-order capacitor in the capacitor array connected to the positive-phase input end of the amplifying unit in the first-stage successive approximation type analog-to-digital conversion module to a first reference voltage, and connecting the rest capacitors to a reference ground to obtain the lowest-order voltage of the first-stage successive approximation type analog-to-digital conversion module;

and amplifying the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module by the amplifying unit to obtain the product of the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module and the actual gain of the amplifying unit.

More optionally, the method for obtaining the difference between the output voltage of the amplifying unit and the highest bit voltage of the second stage successive approximation analog-to-digital conversion module includes:

and connecting the capacitor of the highest bit in the second-stage successive approximation type analog-to-digital conversion module with a second reference voltage, and connecting the rest capacitors with a reference ground to obtain the difference value between the output voltage of the amplifying unit and the voltage of the highest bit of the second-stage successive approximation type analog-to-digital conversion module.

As described above, the pipeline successive approximation analog-to-digital converter and the conversion method according to the present invention have the following advantageous effects:

the pipeline successive approximation analog-to-digital converter and the conversion method completely eliminate input offset voltage mismatch between the residual error amplifier and the preamplifier in the comparator of the first-stage successive approximation analog-to-digital conversion module, stabilize the input swing amplitude of the residual error amplifier, improve the linearity of the residual error amplifier, save the chip area and reduce the power consumption to a certain extent. Compared with the prior pipeline successive approximation analog-to-digital converter, the invention can improve the Spurious-Free Dynamic range (SFDR) of about 5dB and the effective number of bits (ENOB) of 0.5 bit.

In addition, the pipeline successive approximation analog-to-digital converter and the conversion method thereof do not need to input extra calibration signals, gain errors are obtained by multiplexing the second-stage successive approximation analog-to-digital conversion module, and the gain of the residual error amplifier can be accurately calibrated only by adding one gain calibration DAC, so that the gain errors of the residual error amplifier are reduced, and the conversion accuracy of the whole pipeline successive approximation analog-to-digital converter is improved. Compared with the existing gain calibration method, the circuit area of the invention is greatly reduced; compared with the circuit without the calibration method, the invention can improve the signal-to-noise ratio (SNR) by about 12dB and the spurious-free dynamic range by 10 dB.

Drawings

Fig. 1 is a schematic diagram of a two-stage pipelined successive approximation analog-to-digital converter in the prior art.

Fig. 2 is a block diagram of a pipeline successive approximation adc according to the present invention.

Fig. 3 is a schematic diagram of a pipeline successive approximation adc according to the present invention.

Fig. 4 is a schematic structural diagram of an amplifying unit according to the present invention.

Fig. 5 is a schematic structural diagram of the common mode feedback circuit according to the present invention.

Fig. 6 is a schematic diagram showing the operation timing of the pipeline successive approximation adc according to the present invention.

Fig. 7 is a schematic diagram illustrating a structure of a calibration capacitor DAC module according to the present invention.

Fig. 8 is a flow chart of the pipeline successive approximation analog-to-digital conversion method according to the present invention.

FIG. 9 is a timing diagram illustrating a gain calibration method according to the present invention.

Description of the element reference numerals

1-a two-stage pipelined successive approximation analog-to-digital converter; 11-a first stage successive approximation type analog-to-digital converter; 12-a residual amplifier; 13-second order successive approximation type analog-to-digital converter; 14-digital code error correction logic; 15-a capacitor array; 16-a comparator; 17-register and logic control unit;

2-a pipelined successive approximation analog-to-digital converter; 21-a first-stage successive approximation analog-to-digital conversion module; 211-a first capacitive array unit; 211 a-first upper capacitor array; 211 b-first lower capacitor array; 212-an amplifying unit; 212 a-differential flip voltage follower circuit; 212 b-common source stage amplification circuit; 212 c-common mode feedback circuit; 213-latching the comparison unit; 214-first register logic control unit; 22-a second-stage successive approximation analog-to-digital conversion module; 221-a second capacitive array unit; 221a, 221b — upper and lower capacitor arrays of the second capacitor array unit; 222-a comparison unit; 223-a second register logic control unit; 23-digital code error correction logic; 24-calibrating the capacitive DAC module.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 2 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 2, the present embodiment provides a pipelined successive approximation analog-to-digital converter 2, where the pipelined successive approximation analog-to-digital converter 2 includes:

a first-stage successive approximation analog-to-digital conversion module 21, a second-stage successive approximation analog-to-digital conversion module 22 and a digital code error correction logic module 23.

As shown in fig. 2, the first-stage successive approximation analog-to-digital conversion module 21 performs analog-to-digital conversion on the input voltage to obtain a high-order codeword D1.

Specifically, as shown in fig. 3, the first-stage successive approximation analog-to-digital conversion module 21 includes a first capacitor array unit 211, an amplifying unit 212, a latch comparing unit 213, a first register logic control unit 214 and a control switch.

More specifically, the first capacitor array unit 211 is connected to the input voltage, samples the input voltage, and redistributes charges based on the sampled voltage magnitude, the first reference voltage, and the ground reference connection. In this embodiment, the first capacitor array unit 211 has a differential structure, and includes a first upper capacitor array 211a, a first lower capacitor array 211b, a first switch k2a, and a second switch k2 b. The upper electrode of each capacitor in the first upper capacitor array 211a is connected to the positive-phase input voltage Vinp via the first switch K2a, the first switch K2a is controlled by the sampling clock clkS, and the lower electrode of each capacitor in the first upper capacitor array 211a is connected to the common-mode voltage Vcm, the first reference voltage Vref1 or the reference ground gnd via a single-pole-three-throw switch (or three separate switches), respectively; as an example, the first upper capacitor array 211a includes 7 capacitors with capacitance values of 32C, 16C, 8C, 4C, 2C, C, C, respectively, where C is a unit capacitance value; the first 6 capacitors represent 2 respectively^-1Vref1、2^-2Vref1、2^-3Vref1、2^-4Vref1、2^-5Vref1、2^-6Vref1, the 7 th capacitor is a dummy capacitor, which is used to adjust the weights so that the sum of the weights of the other capacitors is an integer power of 2. The upper electrode of each capacitor in the first lower capacitor array 211b is connected to the negative phase input voltage Vinn via the second switch k2b, the second switch k2b is controlled by the sampling clock clkS, and the lower electrode of each capacitor in the first lower capacitor array 211b is connected to the common mode voltage Vcm, the first reference voltage Vref1 or the reference ground gnd via a single-pole-three-throw switch (or three separate switches), respectively; the first lower capacitor array 211b and the first upper capacitor array 211a have the same structure, which is not repeated herein.

It should be noted that, in the present embodiment, a capacitor array with a differential structure is adopted to obtain better noise performance; in practical use, a single-ended structure may be adopted, which is not limited to this embodiment.

More specifically, the amplifying unit 212 is connected to the output end of the first capacitor array unit 211, and amplifies the signal output by the first capacitor array unit 211. As shown in fig. 3, in this embodiment, the non-inverting input terminal of the amplifying unit 212 is connected to the upper plate of each capacitor in the first upper capacitor array 211a, and the inverting input terminal is connected to each capacitor in the first lower capacitor array 211bAnd (4) an upper polar plate. When the first-stage successive approximation analog-to-digital conversion module 21 works (samples, converts), the amplifying unit 212 serves as a preamplifier of the latching comparing unit 213; after the first-stage successive approximation analog-to-digital conversion module 21 finishes working, the amplifying unit 212 serves as a residual error amplifier. As an example, the amplifying unit 212 adopts a broadband amplifier in consideration of the speed requirement of the whole pipelined successive approximation analog-to-digital converter 2; as shown in fig. 4, the amplifying unit 212 includes a differential flip-flop voltage follower circuit 212a and a common-source amplifying circuit 212 b; the differential flip-flop voltage follower circuit 212a includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2, wherein the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are NMOS transistors, and the fifth transistor M5 and the sixth transistor M6 are PMOS transistors; the first transistor M1 has a gate connected to the output signal Vip of the first upper capacitor array 211a, a source connected to the ground VSS via the third transistor M3, and a drain connected to the power supply voltage VDD via the fifth transistor M5; the connection node of the first transistor M1 and the fifth transistor M5 is used as a first output end and is connected with the gate of the third transistor M3; the gate of the fifth transistor M5 is connected to a common-mode feedback voltage Vcmfb; the gate of the second transistor M2 is connected to the output signal Vin of the first lower capacitor array 211b, the source is connected to the ground VSS via the fourth transistor M4, and the drain is connected to the power supply voltage VDD via the sixth transistor M6; the connection node of the second transistor M2 and the sixth transistor M6 is used as a second output end and is connected with the gate of the fourth transistor M4; the gate of the sixth transistor M6 is connected to the common mode feedback voltage Vcmfb; the first resistor R1 and the second resistor R2 are connected in series and then connected between the sources of the first transistor M1 and the second transistor M2, the first capacitor C1 and the second capacitor C2 are connected in series and then connected between the sources of the first transistor M1 and the second transistor M2, and the first resistor R1 and the second resistor R2 are connectedThe node is connected with the connecting node of the first capacitor C1 and the second capacitor C2. The common-source stage amplifying circuit 212b comprises a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a third resistor R3 and a fourth resistor R4, wherein the seventh transistor M7 and the eighth transistor M8 are NMOS transistors, and the ninth transistor M9 and the tenth transistor M10 are PMOS transistors; the gate of the seventh transistor M7 is connected to the first output terminal of the differential inverted voltage follower circuit 212a, the source thereof is grounded, and the drain thereof is connected to the power supply voltage VDD via the ninth transistor M9; a connection node of the seventh transistor M7 and the ninth transistor M9 outputs a non-inverted output signal Voutp of the amplification unit 212; the gate of the ninth transistor M9 is connected to a bias voltage Vb; the gate of the eighth transistor M8 is connected to the second output terminal of the differential inverted voltage follower circuit 212a, the source thereof is grounded, and the drain thereof is connected to the power supply voltage VDD via the tenth transistor M10; a connection node of the eighth transistor M8 and the tenth transistor M10 outputs an inverted output signal Voutn of the amplifying unit 212; the gate of the tenth transistor M10 is connected to the bias voltage Vb; the third resistor R3 and the fourth resistor R4 are connected in series and then connected between the non-inverted output signal Voutp and the inverted output signal Voutn of the amplifying unit 212, and the connection node of the third resistor R3 and the fourth resistor R4 is connected to the common mode level Vcom output by the amplifying unit 212. The first stage of differential flip voltage follower circuit 212a is used for improving the bandwidth, the second stage of common source stage amplification circuit 212b is used for providing the required gain, which can be obtained by small signal analysis, and the first stage of low-frequency gain is Av 1= -1/gm₃R_SThe second stage low frequency gain is Av2= -gm₇R_LWherein g is_m3Is the transconductance of the third transistor M3 and the fourth transistor M4, g_m7The transconductance, R, of the seventh transistor M7 and the eighth transistor M8_SIs the resistance value of the first resistor R1 and the second resistor R2, R_LThe overall gain of the amplifying unit 212 is equal to the resistance of the third resistor R3 and the fourth resistor R4

Av=Av1*Av2= g_m7R_L /g_m3R_S （1）

As can be seen from equation (1), when the sizes of the third transistor M3 and the fourth transistor M4 are not greatly different from those of the seventh transistor M7 and the eighth transistor M8, g is larger_m7≈g_m3Therefore, the gain of the circuit can be increased by R_LAnd R_SAnd (5) controlling. The frequency response of the amplifying unit 212 at high frequency is:

Av=Vout(s)/Vin(s)= g_m7R_L（1+sR_S C_S）/（g_m3R_S（1+sR_LC_L）（1+s2R_SC_S/（2+g_m1R_S）））（2）

wherein, C_LIs a load capacitance, C_SIs the capacitance value, g, of the first capacitor C1 and the second capacitor C2_m1Is the transconductance of the first transistor M1 and the second transistor M2. In the amplifying unit 212, the first-stage pole has a very high frequency, which may not be considered; as can be seen from the formula (2), a zero point Z = -1/R of the left half plane is generated_SC_SThe dominant pole is p1= -1/R_LC_L. Thus, R can be replaced by_SC_S= R_LC_LThe zero and the dominant pole are offset, so that the bandwidth is greatly widened, and the speed of the circuit is improved.

As an implementation manner of the present invention, the amplifying unit 212 further includes a common mode feedback circuit 212c, and the common mode feedback circuit 212c is connected to the output end of the common source stage amplifying circuit 212b to obtain a fixed output common mode voltage and stabilize the voltages of the nodes of the amplifying unit 212. As an example, as shown in fig. 5, the common mode feedback circuit 212c is a switched capacitor type common mode feedback circuit, and in practical use, any common mode feedback circuit structure that can obtain a fixed output common mode voltage and stabilize the voltages of the nodes of the amplifying unit 212 is applicable to the present invention, and is not limited to this embodiment. The switch capacitor type common mode feedback circuit comprises a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a third capacitor C3 and a fourth capacitor C4; the first end of the third switch K3 is connected to the non-inverted output signal Voutp of the amplifying unit 212, and the second end is sequentially connected to the common mode voltage Vcm through the first end and the second end of the fourth switch K4 (in this embodiment, the common mode voltage is the same as the common mode voltage Vcm connected to the first upper capacitor array 211a and the first lower capacitor array 211b, and another voltage may be set as the common mode voltage in the common mode feedback circuit 212c in actual use, which is not limited in this embodiment); a first terminal of the fifth switch K5 is connected to the inverted output signal Voutn of the amplifying unit 212, and a second terminal thereof is connected to the common mode voltage Vcm through a first terminal and a second terminal of the sixth switch K6 in sequence; a first end of the seventh switch K7 is connected to the common mode feedback voltage Vcmfb, and a second end thereof is connected to the bias voltage Vbias through a first end and a second end of the eighth switch K8 in sequence; one end of the third capacitor C3 is connected to the second end of the third switch K3, and the other end is connected to the second end of the seventh switch K7; one end of the fourth capacitor C4 is connected to the second end of the fourth switch K4, and the other end is connected to the second end of the eighth switch K8; one end of the fifth capacitor C5 is connected to the second end of the fifth switch K5, and the other end is connected to the second end of the seventh switch K7; one end of the sixth capacitor C6 is connected to the second end of the sixth switch K6, and the other end is connected to the second end of the first switch K8. The switched capacitor type common mode feedback circuit is extremely low in power consumption and has no influence on the output swing of the residual error amplifier. The principle of charge conservation can be used: when the fourth switch K4, the sixth switch K6 and the eighth switch K8 are closed, the total charge amount Q1 of the common mode feedback circuit is: q1= (Voutp-Vcmfb) C3+ (Voutn-Vcmfb) C5+ (Vcm-Vbias) (C4 + C6), and when the third switch K3, the fifth switch K5, and the seventh switch K7 are closed, the total charge amount Q2 of the common mode feedback circuit is: q2= (Voutp-Vcmfb) (C3 + C4) + (Voutn-Vcmfb) (C5 + C6), wherein C3= C4= C5= C6. From charge conservation, (Voutp + Voutn)/2= Vcm + Vcmfb-Vbias can be derived. It can be seen that if a suitable said bias voltage Vbias is chosen, said common mode level Vcom = (Voutp + Voutn)/2= Vcm of the output can be made. Namely, when the residual error amplifier works, the output level can be stabilized at the common-mode voltage Vcm, so that the effect of inhibiting common-mode drift is achieved, and the common-mode rejection ratio of the circuit is improved.

More specifically, when the amplifying unit 212 is used as a residual error amplifier, the amplifying unit is used in an open loop to provide an inter-stage gain between two stages of analog-to-digital converters, and the gain provided by the open loop of the operational amplifier is not stable and accurate enough due to external factors such as a process, so that the gain calibration of the operational amplifier is required. Assuming that the conversion precision of the pipelined successive approximation analog-to-digital converter 2 is N bits (N =12 in this embodiment), the conversion precision of the first-stage successive approximation analog-to-digital conversion module 21 is M bits (M =7 in this embodiment), and there is 1-bit redundancy, then the conversion precision of the second-stage successive approximation analog-to-digital conversion module 22 is N-M +1 bits (N-M +1=6 in this embodiment). Let the quantization range of the first-stage successive approximation analog-to-digital conversion module 21 be V_FS,1Then the Least Significant Bit (LSB) voltage of the first stage is V_FS,1/2^M. In consideration of equivalent interstage gain A and 1-bit redundancy, the full swing voltage of the second-stage successive approximation analog-to-digital conversion module 22 is V_FS,2=AV_FS,1/2^M-1. If the reference voltages of the two stages of analog to digital conversion modules match, the second stage successive approximation analog to digital conversion module 22 should have the Most Significant Bit (MSB) voltage of V_MSB,2=1/2V_FS,2= AV_FS,1/2^M=AV_LSB,1. The gain error of the operational amplifier should meet the following requirements:

AV_LSB,1*|Δ|<1/2V_LSB,2，

wherein, Delta is the gain error percentage of the operational amplifier, V_LSB,2Is the minimum quantization voltage of the second stage successive approximation analog-to-digital conversion module 22. Since the conversion precision of the second-stage successive approximation analog-to-digital conversion module 22 is N-M +1, |. DELTA.. sup. +1 can be obtained by the above formula<1/2^N-M+1(in this example, Δ is required<1.5625%）。

It should be noted that, when the control switch is turned off, the amplifying unit 212 is used as a preamplifier of the latch comparing unit 213 in the first-stage successive approximation analog-to-digital conversion module 21; when the control switch is closed, the residual error amplifier is used. The amplifying unit 212 is used in an open loop mode when being used as a residual error amplifier, and compared with a residual error amplifier with a traditional closed loop operational amplifier structure, the open loop residual error amplifier avoids an additional non-dominant pole, and the additional non-dominant pole can reduce the bandwidth of the amplifier, so that the voltage conversion speed of the amplifier is reduced. In addition, under the application of a high-speed analog-to-digital converter, a larger bandwidth is needed, so that an extra current needs to be added to improve the bandwidth of the operational amplifier under the influence of a non-dominant pole of a residual error amplifier of a traditional closed-loop operational amplifier structure, so that the power consumption of the operational amplifier is increased, and the power consumption of the residual error amplifier can be reduced.

More specifically, the latch comparing unit 213 is connected to an output terminal of the amplifying unit 212, compares an output signal of the amplifying unit 212 with a reference signal, and outputs a first comparison result. The latch comparing unit 213 is controlled by the operating clock clk1 of the first successive approximation analog-to-digital conversion module 21, and rapidly increases the output voltage to the power supply voltage VDD or the reference ground gnd in an operating state, and as the first comparison result, when the output signal of the amplifying unit 212 is greater than a preset reference signal, the first comparison result is at a high level (the power supply voltage VDD), and when the output signal of the amplifying unit 212 is less than the preset reference signal, the first comparison result is at a low level (the reference ground gnd). The amplifying unit 212 and the latch comparing unit 213 form a comparator of the first-stage successive approximation analog-to-digital conversion module 21 when the first-stage successive approximation analog-to-digital conversion module 21 operates.

More specifically, the first register logic control unit 214 is connected to the output terminal of the latch comparing unit 213 and the control terminal of the first capacitor array 211, controls each capacitor in the first capacitor array 211 to connect the input voltage, the first reference voltage or the ground based on the first comparison result, and outputs the high-order codeword D1. The first register logic control unit 214 generates an M-bit code word (constituting the high-bit code word D1) based on the first comparison result and controls on and off (switching) of each switch in the first capacitor array 211 to redistribute charges to the output terminals of the first upper capacitor array 211a and the first lower capacitor array 211 b.

More specifically, one end of the control switch is connected to the output end of the amplifying unit 212, and the other end of the control switch is used as the output end of the first-stage successive approximation analog-to-digital conversion module 21, the control switch is turned off when the first-stage successive approximation analog-to-digital conversion module 21 works, and the control switch is turned on after the work is finished. As shown in fig. 3, in the present embodiment, the successive approximation analog-to-digital conversion circuit includes a first control switch K1a and a second control switch K1b, the first control switch K1a and the second control switch K1b are respectively connected to the non-inverting output terminal and the inverting output terminal of the amplifying unit 212, and the control terminal is connected to a residual amplifier operating clock clkA.

When the first-stage successive approximation analog-to-digital conversion module 21 is in operation, the amplifying unit 212 serves as a preamplifier of the latching comparing unit 213. Under the clock control, the working state of the first stage successive approximation analog-to-digital conversion module 21 is divided into a sampling phase (when the clock clkS is at a high level) and a conversion phase (when the clock clkS is at a low level, and when the sampling phase is performed, the first register logic control unit 214 controls the first switch k2a and the second switch k2b to be closed, the input end of the amplifying unit 212 (preamplifier) is connected with Vinp/Vinn, and the lower plates of all capacitors are connected with a first reference voltage Vref 1. At this time, the input of the preamplifier is Vinp-Vinn, and at the same time, the preamplifier amplifies Vinp-Vinn and transmits the amplified Vinp-Vinn to the latch comparing unit 213, and the latch comparing unit 213 rapidly increases the output to VDD or decreases the output to gnd, and then transmits a signal to the first register logic control unit 214, so as to obtain the highest output codeword d 1. After sampling is finished, switching phases; if Vinp > Vinn, the highest bit d1=1 is outputted, and in the first switching phase, the first register logic control unit 214 controls the first switch k2a and the second switch k2b to be turned off, and controls the highest bit capacitor (32C) in the first upper capacitor array 211a to be grounded gnd, and the first lower capacitor array 211b is unchanged. At this time, the preamplifier input voltage vx = vip-vin = Vinp-1/2 vref1 can be derived from charge conservation. The comparison of the input voltage with 1/2Vref1 is complete, yielding d 2. Similarly, in the next stage, d3 is obtained. If d2=1, i.e. the next higher stage vx >0, then the second highest capacitance (16C) in the first upper capacitor array 211a is gnd, and the first lower capacitor array 211b is unchanged. At this time, as can be obtained by charge conservation, the preamplifier input voltage vx = vip-vin = Vinp-Vinn-3/4 Vref; if d2=0, i.e. the last phase vx is <0, then the second highest bit of the first upper capacitor array 211a is unchanged and the second highest bit of the first lower capacitor array 211b is gnd, at which point the preamplifier input voltage vx = vip-vin = Vinp-Vinn-1/4Vref, which is obtained from the law of conservation of charge. The comparison of the third bit is completed. The first-stage successive approximation analog-to-digital conversion module 21 repeats the operation until the lowest bit capacitor (C) is converted to complete the comparison of the lowest bit. To this end, the high-order codeword D1 composed of 7-order digital codewords is output to the digital code error correction logic module 23, and a residual voltage after conversion is left at the input terminal of the amplifying unit 212.

After the first successive approximation analog-to-digital conversion module 21 finishes working, the first successive approximation analog-to-digital conversion module 21 stops working, the first control switch K1a and the second control switch K1b are closed, and a residual error amplifier amplification stage is started, at this time, the amplification unit 212 is used as a residual error amplifier, and a residual voltage left at the input end of the amplification unit 212 after the conversion of the first successive approximation analog-to-digital conversion module 21 is finished is amplified and then is supplied to the second successive approximation analog-to-digital conversion module 22, and is used as an input voltage of the second successive approximation analog-to-digital conversion module 22, so that a digital code (a low-bit code word D2) of the residual bit is obtained.

Compared with the traditional successive approximation analog-to-digital converter, the structure and the conversion mode of the first-stage successive approximation analog-to-digital conversion module 21 have the advantages that the size of the total capacitance is reduced by half, the first conversion does not need switching action, only one switch is involved in each conversion, and the chip area and the switching action power consumption are effectively reduced. Compared with the traditional successive approximation analog-to-digital converter, the switching action average consumption of the structure is saved by 81.3%.

As shown in fig. 2, the second-stage successive approximation analog-to-digital conversion module 22 is connected to the output end of the first-stage successive approximation analog-to-digital conversion module 21, and performs analog-to-digital conversion on the residual voltage of the first-stage successive approximation analog-to-digital conversion module 21 to obtain a low-bit codeword D2.

Specifically, as shown in fig. 3, the second-stage successive approximation analog-to-digital conversion module 22 includes a second capacitor array unit 221, a comparison unit 222 and a second register logic control unit 223.

More specifically, the second capacitor array unit 221 is connected to the output end of the first stage successive approximation analog-to-digital conversion module 21, samples the residual voltage output by the first stage successive approximation analog-to-digital conversion module 21, and redistributes charges based on the sampled voltage magnitude, the second reference voltage Vref2, and the reference ground gnd connection manner. For example, in this embodiment, the second capacitor array unit 221 is a differential structure, the upper and lower capacitor arrays 221a and 221b each include 6 capacitors, and the capacitance values are 16C, 8C, 4C, and 2C, C, C, which are similar to the first capacitor array unit 211 in specific connection and operation principles and are not repeated herein.

More specifically, the comparing unit 222 is connected to the output end of the second capacitor array unit 221, compares signals output by the second capacitor array unit 221, and outputs a second comparison result. The comparison unit 222 is controlled by an operation clock clk2 of the second stage successive approximation analog-to-digital conversion module 22. The comparing unit 222 may adopt a comparator circuit with any differential structure, which is not described in detail herein.

More specifically, the second register logic control unit 223 is connected to the output terminal of the comparison unit 222 and the control terminal of the second capacitor array unit 221, controls the lower plate of each capacitor in the second capacitor array unit 221 to be connected to the second reference voltage Vref2 or the reference ground gnd based on the second comparison result, and outputs the low-level codeword D2, where the low-level codeword D2 includes a 6-bit digital code. The working principle of the second register logic control unit 223 is similar to that of the first register logic control unit 214, and is not repeated herein.

As shown in fig. 2, the digital code error correction logic module 23 is connected to the output ends of the first-stage successive approximation analog-to-digital conversion module 21 and the second-stage successive approximation analog-to-digital conversion module 22, and adds the high-order codeword D1-and the low-order codeword D2, and removes redundant bits to obtain an output codeword Dout.

Specifically, as an example, in this embodiment, taking a 12-bit pipelined successive approximation analog-to-digital converter 2 as an example, the high-order codeword D1 includes a 7-bit digital code, the low-order codeword D2 includes a 6-bit digital code, and the digital code error correction logic module 23 adds the 7-bit digital code and the 6-bit digital code and removes a redundant bit to obtain a 12-bit output codeword Dout.

Fig. 6 shows the normal operation timing of the pipeline successive approximation adc 2 according to the present invention. When the sampling clock clkS is at a high level, the first switch K2a and the second switch K2b are closed, the lower plates of all capacitors in the first stage successive approximation analog-to-digital conversion module 21 are connected to the first reference voltage Vref1, and the upper plates are connected to Vinp/Vinn. The working clock clk1 of the first successive approximation analog-to-digital conversion module 21 controls the output of the latch comparing unit 213, the latch comparing unit 213 outputs a high or low level to the first register logic control unit 214, and the first register logic control unit 214 controls the single-pole three-throw switches in the first capacitor array unit 211 to switch and output the output codeword of the first successive approximation analog-to-digital conversion module 21. When the residual amplifier operating clock clkA is at a low level, the first control switch K1a and the second control switch K1b are turned off, and the amplifying unit 212 functions as a preamplifier. After the first-stage successive approximation analog-to-digital conversion module 21 finishes working, the residual error amplifier working clock clkA jumps to a high level, the first control switch K1a and the second control switch K1b are closed, and the amplification unit 212 serves as a residual error amplifier; the amplifying unit 212 amplifies the voltage of the remaining stage of the first-stage successive approximation analog-to-digital conversion module 21 and then transmits the amplified voltage to the second-stage successive approximation analog-to-digital conversion module 22. Since the capacitance value of the capacitor array in the second-stage successive approximation analog-to-digital conversion module 22 is usually small and the available time is long, the working timing of the second-stage successive approximation analog-to-digital conversion module 22 is well arranged, and the conversion of the second-stage successive approximation analog-to-digital conversion module 22 is completed only after the sampling clock clkS jumps to a low level and before the residual error amplifier working clock clkA jumps to a high level.

As shown in fig. 3, as another implementation manner of the present invention, the pipelined successive approximation analog-to-digital converter 2 further includes an inter-stage coupling capacitor and calibration capacitor DAC module 24.

Specifically, as shown in fig. 3, the inter-stage coupling capacitor is connected between the output terminal of the first capacitor array unit 211 and the input terminal of the amplifying unit 212. In the embodiment, the first inter-stage coupling capacitor Co1 and the second inter-stage coupling capacitor Co2 are included; one end of the first inter-stage coupling capacitor Co1 is connected to the upper plate of each capacitor in the first upper capacitor array 211a, and the other end is connected to the non-inverting input end of the amplifying unit 212; one end of the second inter-stage coupling capacitor Co2 is connected to the upper plate of each capacitor in the first lower capacitor array 211b, and the other end is connected to the inverting input terminal of the amplifying unit 212.

Specifically, as shown in fig. 3, the calibration capacitor DAC module 24 is connected between the inter-stage coupling capacitor and the amplifying unit 212, the control terminal is connected to the output terminal of the second register logic control unit 223, the calibration capacitor DAC module 24 obtains a gain calibration control signal generated based on the difference between the voltage of the highest bit in the second capacitor array unit 221 and the output voltage of the amplifying unit 212 from the second register logic control unit 223, and adjusts the capacitance value of the calibration capacitor DAC module 24 based on the gain calibration control signal, thereby implementing gain calibration.

More specifically, the second register logic control unit 223 obtains a difference between the most significant bit voltage in the second capacitor array unit 221 and the output voltage of the amplification unit 212 (the product of the least significant bit voltage of the first stage successive approximation analog-to-digital conversion module 211 and the gain of the amplification unit 212), and generates a gain calibration control signal based on the difference. The calibration capacitor DAC module 24 adjusts the gain of the amplifying unit 212 under the control of the gain calibration control signal.

More specifically, as shown in fig. 3, the present embodiment includes upper and lower calibration capacitor DAC modules respectively connected to the differential input terminals of the amplifying unit 212. As an example, as shown in fig. 7, the calibration capacitance DAC module 24 includes a first set of capacitances and a second set of capacitances, each of which includes 6 capacitances; one end of each capacitor in the first group of capacitors and the second group of capacitors is connected between the interstage coupling capacitor and the amplifying unit 212, and the other end of each capacitor is grounded through a switch; and the control end of each switch is connected with the gain calibration control signal. The number of the capacitors in the first group of capacitors and the number of the capacitors in the second group of capacitors are respectively set to k, wherein k depends on an allowable gain error range of the residual error amplifier, and the value of k determines a gain adjustment range of the residual error amplifier. In this embodiment, the operational amplifier gain error requires Δ<1.5625% (i.e. the allowable gain error range of the residual amplifier is 1.5625%), in order to obtain a sufficiently small gain step to accurately control the gain of the amplifying unit, k is taken to be 6, i.e. 1/2 in this embodiment^kLess than or equal to 1.5625 percent, and k is a natural number not less than 6.

More specifically, the gain can be accurately controlled by the calibration capacitor DAC module 24, and an additional calibration circuit (calibration logic control circuit) is not required, so that the circuit area is not increased. As shown in fig. 7, in the present embodiment, the adjustment of one side of the inverting input terminal of the amplifying unit 212 is taken as an example, and the principle of the other side is the same, which is not repeated herein. Let the initial gain of the amplifying unit 212 be A₀The residual voltage after the conversion of the first-stage successive approximation analog-to-digital conversion module 21 is Vres. Due to the inter-stage coupling capacitance (the first inter-stage coupling capacitance Co1 and the second inter-stage coupling capacitance Co2 both having capacitance values of Ca) and the calibration capacitance DAC module 24 (on)The values of the calibration capacitances adjusted by the partial calibration capacitance DAC module Ccala and the lower calibration capacitance DAC module Ccalb are both Ccal), and the input voltage of the amplifying unit 212 is (Ca/(Ccal + Ca)). times Vres, so that the equivalent gain is:

A=（Ca/（Ccal+Ca））A₀ （3）

the gain of the amplifying unit 212 can be adjusted by adjusting the size of the capacitance value of the calibration capacitance DAC module. In addition, as can be seen from the above analysis, the voltage of the Most Significant Bit (MSB) of the second-stage successive approximation analog-to-digital conversion module 22 is equal to a times the voltage of the Least Significant Bit (LSB) of the first-stage successive approximation analog-to-digital conversion module 21, i.e., V_MSB,2=AV_LSB,1. Therefore, the difference AV between the two_LSB,1- V_MSB,2The calibration capacitor DAC module is controlled by detecting the error, so as to adjust the value Ccal of the calibration capacitor to calibrate the gain of the amplifying unit 212. As shown in equation (3), the actual open-loop op-amp gain a of the amplifying unit 212 must be smaller than the initial gain a of the amplifying unit 212₀Therefore, the gain is slightly increased when the amplification unit 212 is designed, and as an example, the initial amplification factor of the residual amplifier is 16 times, and the amplification factor of the residual amplifier is slightly increased to 20 when the residual amplifier is actually designed. The calibration capacitor DAC module 24 controls the value Ccal of the calibration capacitor to be 0-3.2 pF by taking Ca =3pF and taking 50fF as the unit capacitor in Ccal, and the adjustable gain range of the residual error amplifier is 9.68-20 times and the step is 0.16 times under the control of the calibration capacitor DAC module 24, and the operational amplifier error can be controlled to be 0.8%, which meets the design requirement of the allowable error.

More specifically, in the present embodiment, the calibration capacitor DAC module 24 has a setting accuracy of 6 bits, that is, the calibration capacitor DAC module is composed of 64 unit capacitors, which are respectively 16C, 8C, 4C, and 2C, C, C, and is divided into a first group of capacitors and a second group of capacitors, where the first group of capacitors is located in the upper row, and the second group of capacitors is located in the lower row, where C is a unit capacitor. In an initial state, switches corresponding to all capacitors in the first group of capacitors are closed, namely grounded; all capacitors in the second group of capacitors correspond toThe switch of (1) is open, i.e. the capacitor is floating. At this time Ccal = 32C. The error voltage AV is obtained from the second register logic control unit 223 as described above_LSB,1- V_MSB,2If AV_LSB,1- V_MSB,2If the value is larger than 0, namely A is larger than a preset value, the gain calibration control signal controls the highest-order capacitor (16C) in the second group of capacitors to be grounded, and then the next calibration is carried out. In the same way, if AV_LSB,1- V_MSB,2And when the value is less than 0, namely A is smaller, the gain calibration control signal controls the highest capacitor (16C) in the first group of capacitors to suspend, and then the next calibration is carried out. And so on, and the gain calibration mode is skipped until all the 6 capacitors in the calibration capacitor DAC module 24 are configured.

Example two

As shown in fig. 8 and fig. 9, this embodiment provides a pipelined successive approximation analog-to-digital conversion method, which is implemented based on the pipelined successive approximation analog-to-digital converter 2 of the first embodiment, and any hardware circuit or software code that can implement this method is suitable for this invention in practical use. The pipelined successive approximation analog-to-digital conversion method comprises the following steps:

the first-stage successive approximation analog-to-digital conversion module 21 performs analog-to-digital conversion on the input voltage through sampling conversion to obtain a high-order code word D1, and at this time, the amplifying unit 212 serves as a preamplifier of the latch comparing unit 213 in the first-stage successive approximation analog-to-digital conversion module 21;

after the first-stage successive approximation analog-to-digital conversion module 21 completes analog-to-digital conversion, the amplifying unit 212 is used as a residual error amplifier to amplify and output the residual voltage of the first-stage successive approximation analog-to-digital conversion module 21;

the second-stage successive approximation analog-to-digital conversion module 22 performs analog-to-digital conversion on the residual voltage output by the amplifying unit 212 to obtain a low-order codeword D2;

the digital code error correction logic module 23 adds the high-order codeword D1 and the low-order codeword D2, and then removes redundant bits to obtain an output codeword Dout.

Specifically, the amplifying unit 212 is used as a preamplifier of the latch comparing unit 213 in the first stage successive approximation analog-to-digital conversion module 21 when the control switch is turned off; when the control switch is closed, the residual error amplifier is used. The working principle of the first-stage successive approximation analog-to-digital conversion module 21, the second-stage successive approximation analog-to-digital conversion module 22 and the digital code error correction logic module is referred to in the first embodiment, which is not repeated herein.

Specifically, as another implementation manner of the present invention, the pipelined successive approximation analog-to-digital conversion method further includes performing gain adjustment on the amplifying unit 212 by adjusting a capacitance value at an input end of the amplifying unit 212, and satisfying the following relation:

A=（Ca/（Ccal+Ca））A₀。

as shown in fig. 8 and 9, the method of gain adjustment specifically includes:

1) the first group of capacitors in the calibration capacitor DAC module 24 is grounded, the second group of capacitors is floating, and the other end of each capacitor in the first group of capacitors and the second group of capacitors is connected to the input end of the amplifying unit 212.

As an example, first, the gain calibration enable clock clkc jumps high, enters gain calibration mode, and shorts the inputs, i.e., Vinn = Vinp. The first group of capacitors in the calibration capacitor DAC module 24 is grounded, and the second group of capacitors is suspended, so that the value Ccal of the calibration capacitor adjusted by the calibration capacitor DAC module 24 is the middle value of the adjustable range.

2) And resetting the first-stage successive approximation analog-to-digital conversion module 21 and the second-stage successive approximation analog-to-digital conversion module 22.

As an example, at the first high level of the control clock clkc1 of the first-stage successive approximation analog-to-digital conversion module 21, the first-stage successive approximation analog-to-digital conversion module 21 is in the reset phase, the lower plates of all capacitors in the first-stage successive approximation analog-to-digital conversion module 21 are connected to the reference ground, and the upper plates are connected to Vinn/Vinp. When the control clock clkc3 of the second-stage successive approximation analog-to-digital conversion module 22 and the calibration capacitor DAC module 24 is at a low level, the lower plates of all capacitors in the second-stage successive approximation analog-to-digital conversion module 22 are connected to a second reference voltage Vref2, and the upper plates are connected to the input end of the comparison unit 222, so that the second-stage successive approximation analog-to-digital conversion module 22 is reset.

3) Obtaining the product AV of the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module and the actual gain of the amplifying unit through the output voltage of the amplifying unit_LSB,1。

As an example, at the second high level of the control clock clkc1 of the first-stage successive approximation analog-to-digital conversion module 21, by connecting the lower plate of the Least Significant Bit (LSB) capacitor of the first upper capacitor array 211a in the first-stage successive approximation analog-to-digital conversion module 21 to the first reference voltage Vref1 and grounding the rest capacitors, V = Vinp-Vinn +1/64Vref1= V can be obtained by charge conservation_LSB,1. Controlling the first-stage successive approximation analog-to-digital conversion module 21 to obtain V at a control clock clkc1 of the first-stage successive approximation analog-to-digital conversion module 21_LSB,1Thereafter, the operation clock clkc2 of the amplifying unit 212 jumps to the high level, and V is set to be_LSB,1Amplifying to obtain AV_LSB,1。

4) And acquiring a difference value between the output voltage of the amplifying unit and the highest bit voltage of the second-stage successive approximation analog-to-digital conversion module, grounding the capacitor of the highest bit in the second group of capacitors if the difference value is greater than zero to increase the value of the calibration capacitor, otherwise suspending the capacitor of the highest bit in the first group of capacitors to reduce the value of the calibration capacitor.

As an example, AV is obtained_LSB,1Then, the control clock clkc3 of the second successive approximation analog-to-digital conversion module 22 and the calibration capacitor DAC module 24 changes to high level, at this time, the capacitor bottom plate of the Most Significant Bit (MSB) in the second successive approximation analog-to-digital conversion module 22 is connected to the second reference voltage Vref2, and the rest is connected to the reference ground gnd, so that the difference AV between the output voltage of the amplification unit and the most significant bit voltage of the second successive approximation analog-to-digital conversion module can be obtained_LSB,1- V_MSB,2(i.e., Gain cal) as the required error voltage.

By way of example, the comparing unit 222 in the second-stage successive approximation analog-to-digital conversion module 22 may determine whether the error voltage is positive or negative, so as to control the size of the calibration capacitor through the calibration capacitor DAC module 24. If AV_LSB,1- V_MSB,2If the value is greater than 0, the output of the comparing unit 222 is 1, and the highest bit 16C in the second group of capacitors is grounded, and the next calibration is performed. In the same way, if AV_LSB,1- V_MSB,2And if the output of the comparison unit 222 is less than 0, the highest bit 16C in the first group of capacitors is suspended, and then the next calibration is performed until the configuration of the five-bit capacitors in the calibration capacitor DAC module 24 is completed, the calibration is completed, the gain calibration enable clock clkc jumps to a low level, the gain calibration is completed, and the gain calibration mode is skipped.

The residual error amplifier and the preamplifier are shared, the offset voltage mismatch between the residual error amplifier and the preamplifier is completely eliminated, an additional circuit structure is not added, and the complexity of an original circuit is reduced; meanwhile, the improved foreground calibration method can obtain error gain by multiplexing the second-stage successive approximation type analog-to-digital conversion module under the condition of not using an additional calibration signal, and only one calibration capacitor DAC module is added to finish the accurate calibration of the operational amplifier gain.

To sum up, the present invention provides a pipelined successive approximation analog-to-digital converter and a conversion method thereof, including: the first-stage successive approximation analog-to-digital conversion module is used for performing analog-to-digital conversion on the input voltage to obtain a high-order code word; the second-stage successive approximation analog-to-digital conversion module is connected to the output end of the first-stage successive approximation analog-to-digital conversion module and is used for performing analog-to-digital conversion on the residual voltage of the first-stage successive approximation analog-to-digital conversion module to obtain a low-order code word; the digital code error correction logic module is connected with the output ends of the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module, and is used for adding the high-order code words and the low-order code words and removing redundant bits to obtain output code words; the first-stage successive approximation analog-to-digital conversion module comprises a first capacitor array unit, an amplifying unit, a latching comparison unit, a first register logic control unit and a control switch; the first capacitor array unit is connected with the input voltage, samples the input voltage, and redistributes charges based on the sampled voltage, a first reference voltage and a reference ground connection mode; the amplifying unit is connected with the output end of the first capacitor array unit, and is used as a preamplifier for amplifying the signal output by the first capacitor array unit in the conversion phase of the first-stage successive approximation analog-to-digital conversion module; in the amplifying phase of the first-stage successive approximation analog-to-digital conversion module, the amplifying unit is used as a residual error amplifier between the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module, and amplifies the residual error voltage converted by the first-stage successive approximation analog-to-digital conversion module; the latch comparison unit is connected to the output end of the amplification unit, compares the output signal of the amplification unit with a reference signal and outputs a first comparison result; the first register logic control unit is connected with the output end of the latch comparison unit and the control end of the first capacitor array, controls each capacitor in the first capacitor array to be connected with the input voltage, the first reference voltage or the reference ground based on the first comparison result, and outputs the high-order code word; one end of the control switch is connected with the output end of the amplifying unit, the other end of the control switch is used as the output end of the first-stage successive approximation analog-to-digital conversion module, the control switch is switched off when the first-stage successive approximation analog-to-digital conversion module works, and the control switch is switched on after the work is finished. The first-stage successive approximation analog-to-digital conversion module performs analog-to-digital conversion on input voltage through sampling conversion to obtain a high-order code word, and at the moment, the amplifying unit is used as a preamplifier of a latch comparison unit in the first-stage successive approximation analog-to-digital conversion module; after the first-stage successive approximation analog-to-digital conversion module completes analog-to-digital conversion, the amplifying unit is used as a residual error amplifier to amplify and output residual voltage of the first-stage successive approximation analog-to-digital conversion module; the second-stage successive approximation analog-to-digital conversion module performs analog-to-digital conversion on the residual voltage output by the amplifying unit to obtain a low-order code word; and the digital code error correction logic module adds the high-order code words and the low-order code words and removes redundant bits to obtain output code words. According to the pipeline successive approximation analog-to-digital converter and the conversion method, the residual error amplifier and the preamplifier in the comparator of the first-stage successive approximation analog-to-digital conversion module are multiplexed, so that input offset voltage mismatch between the residual error amplifier and the preamplifier is completely eliminated, the input swing amplitude of the residual error amplifier is stabilized, the linearity of the residual error amplifier is improved, the chip area is saved, and the power consumption is reduced to a certain extent; and no additional calibration signal is needed to be input, the gain error is obtained by multiplexing the second-stage successive approximation type analog-to-digital conversion module, and the gain of the residual error amplifier can be accurately calibrated only by adding one gain calibration DAC, so that the gain error of the residual error amplifier is reduced, and the conversion accuracy of the whole pipelined successive approximation type analog-to-digital converter is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A pipelined successive approximation analog-to-digital converter, the pipelined successive approximation analog-to-digital converter comprising at least:

the first-stage successive approximation analog-to-digital conversion module is used for performing analog-to-digital conversion on the input voltage to obtain a high-order code word; the first-stage successive approximation analog-to-digital conversion module comprises a first capacitor array unit, an amplifying unit, a latching comparison unit, a first register logic control unit and a control switch; the first capacitor array unit is connected with the input voltage, samples the input voltage, and redistributes charges based on the sampled voltage, a first reference voltage and a reference ground connection mode; the amplifying unit comprises a differential turnover voltage follower circuit and a common-source amplifying circuit, the common-source amplifying circuit is connected to the output end of the differential turnover voltage follower circuit, the amplifying unit is connected with the output end of the first capacitor array unit, and the amplifying unit is used as a preamplifier for amplifying signals output by the first capacitor array unit in a conversion phase of the first successive approximation analog-to-digital conversion module; in the amplifying phase of the first-stage successive approximation analog-to-digital conversion module, the amplifying unit is used as a residual error amplifier between the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module, and amplifies the residual error voltage converted by the first-stage successive approximation analog-to-digital conversion module; the latch comparison unit is connected to the output end of the amplification unit, compares the output signal of the amplification unit with a reference signal and outputs a first comparison result; the first register logic control unit is connected with the output end of the latch comparison unit and the control end of the first capacitor array, controls each capacitor in the first capacitor array to be connected with the input voltage, the first reference voltage or the reference ground based on the first comparison result, and outputs the high-order code word; one end of the control switch is connected with the output end of the amplifying unit, the other end of the control switch is used as the output end of the first-stage successive approximation analog-digital conversion module, the control switch is switched off when the first-stage successive approximation analog-digital conversion module works, and the control switch is switched on after the work is finished;

the second-stage successive approximation analog-to-digital conversion module is connected to the output end of the first-stage successive approximation analog-to-digital conversion module and is used for performing analog-to-digital conversion on the residual voltage of the first-stage successive approximation analog-to-digital conversion module to obtain a low-order code word; the second-stage successive approximation analog-to-digital conversion module comprises a second capacitor array unit, a comparison unit and a second register logic control unit; the second capacitor array unit is connected with the output end of the first-stage successive approximation analog-to-digital conversion module, samples a signal obtained by amplifying a residual voltage output by the first-stage successive approximation analog-to-digital conversion module by a residual error amplifier, and redistributes charges based on the voltage obtained by sampling, a second reference voltage and a reference ground connection mode; the comparison unit is connected with the output end of the second capacitor array unit, compares the signals output by the second capacitor array unit and outputs a second comparison result; the second register logic control unit is connected to the output end of the comparison unit and the control end of the second capacitor array unit, controls each capacitor in the second capacitor array to be connected with the second reference voltage or reference ground based on the second comparison result, and outputs the low-order code word;

an inter-stage coupling capacitor connected between the output end of the first capacitor array unit and the input end of the amplifying unit;

and the calibration capacitor DAC module is connected between the interstage coupling capacitor and the amplifying unit, the control end of the calibration capacitor DAC module is connected with the output end of the second register logic control unit, a gain calibration control signal generated based on the difference value of the highest bit voltage in the second capacitor array unit and the output voltage of the amplifying unit is acquired from the second register logic control unit, and the capacitance value of the calibration capacitor DAC module is adjusted based on the gain calibration control signal, so that gain calibration is realized.

2. The pipelined successive approximation analog-to-digital converter of claim 1, wherein: the differential turnover voltage following circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, a second resistor, a first capacitor and a second capacitor; the grid electrodes of the first transistor and the second transistor respectively receive differential signals output by the first capacitor array unit; the source electrode of the first transistor is grounded through the third transistor, the drain electrode of the first transistor is connected with a power supply voltage through the fifth transistor, and the drain electrode of the first transistor is used as a first output end and is connected with the grid electrode of the third transistor; the source electrode of the second transistor is grounded through the fourth transistor, the drain electrode of the second transistor is connected with a power supply voltage through the sixth transistor, and the drain electrode of the second transistor is used as a second output end and is connected with the grid electrode of the fourth transistor; the grid electrodes of the fifth transistor and the sixth transistor are connected with a common-mode feedback voltage; the first resistor and the second resistor are connected in series and then connected between the source electrodes of the first transistor and the second transistor, the first capacitor and the second capacitor are connected in series and then connected between the source electrodes of the first transistor and the second transistor, and the connection node of the first resistor and the second resistor is connected with the connection node of the first capacitor and the second capacitor.

3. The pipelined successive approximation analog-to-digital converter of claim 2, wherein: the amplifying unit further comprises a common mode feedback circuit, and the common mode feedback circuit is connected to the output end of the common source amplifying circuit to obtain fixed output common mode voltage and stabilize the voltage of each node of the amplifying unit.

4. The pipelined successive approximation analog-to-digital converter of claim 1, wherein: the calibration capacitor DAC module comprises a first group of capacitors and a second group of capacitors, and the first group of capacitors and the second group of capacitors comprise k capacitors; one end of each capacitor in the first group of capacitors and the second group of capacitors is connected between the interstage coupling capacitor and the amplifying unit, and the other end of each capacitor is grounded through a switch; the control end of each switch is connected with the gain calibration control signal; wherein k depends on the allowed gain error range of the residual amplifier, the value of k determining the gain adjustment range of the residual amplifier.

5. A pipelined successive approximation analog-to-digital conversion method based on the pipelined successive approximation analog-to-digital converter according to any one of claims 1 to 4, characterized in that: the pipelined successive approximation analog-to-digital conversion method at least comprises the following steps:

the digital code error correction logic module adds the high-order code words and the low-order code words and removes redundant bits to obtain output code words;

the calibration capacitor DAC module performs gain adjustment on the amplifying unit by adjusting the capacitance value of the input end of the amplifying unit, and comprises the following steps: 1) grounding a first group of capacitors in a calibration capacitor DAC module, suspending a second group of capacitors, and connecting the other ends of the capacitors in the first group of capacitors and the second group of capacitors to the input end of the amplifying unit; 2) resetting the first-stage successive approximation analog-to-digital conversion module and the second-stage successive approximation analog-to-digital conversion module; 3) obtaining the product of the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module and the actual gain of the amplifying unit through the output voltage of the amplifying unit; 4) acquiring a difference value between the output voltage of the amplifying unit and the highest bit voltage of the second-stage successive approximation analog-to-digital conversion module, grounding the capacitor of the highest bit in the second group of capacitors if the difference value is greater than zero to increase the value of the calibration capacitor, otherwise suspending the capacitor of the highest bit in the first group of capacitors to reduce the value of the calibration capacitor; 5) repeating the steps 2), 3) and 4) to sequentially adjust the connection relation of the capacitors in the calibration capacitor DAC module according to the difference value and the weight from large to small, so as to realize gain calibration; satisfies the following relation:

A=（Ca/（Ccal+Ca））A₀；

6. The pipelined successive approximation analog-to-digital conversion method of claim 5, wherein: the step of resetting the first-stage successive approximation analog-to-digital conversion module comprises the following steps: the input voltage is short-circuited, and all capacitors in the first-stage successive approximation analog-to-digital conversion module are connected with a reference ground; the step of resetting the second-stage successive approximation analog-to-digital conversion module comprises the following steps: and all capacitors in the second-stage successive approximation analog-to-digital conversion module are connected with a second reference voltage.

7. The pipelined successive approximation analog-to-digital conversion method of claim 5, wherein: the method for acquiring the product of the lowest bit voltage of the first-stage successive approximation analog-to-digital conversion module and the actual gain of the amplifying unit comprises the following steps:

8. The pipelined successive approximation analog-to-digital conversion method according to claim 5 or 7, characterized in that: the method for acquiring the difference value between the output voltage of the amplifying unit and the highest bit voltage of the second-stage successive approximation analog-to-digital conversion module comprises the following steps: