CN111753486B - Layout method of multi-die structure FPGA - Google Patents

Layout method of multi-die structure FPGA Download PDF

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CN111753486B
CN111753486B CN202010613230.0A CN202010613230A CN111753486B CN 111753486 B CN111753486 B CN 111753486B CN 202010613230 A CN202010613230 A CN 202010613230A CN 111753486 B CN111753486 B CN 111753486B
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fpga
die
bare chip
fpga bare
connection point
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CN111753486A (en
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单悦尔
虞健
徐彦峰
惠锋
闫华
张艳飞
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CETC 58 Research Institute
Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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    • G06F30/30—Circuit design
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Abstract

The invention discloses a layout method of a multi-die structure FPGA, relating to the technical field of FPGA, the method cuts a large user input netlist into a plurality of small sub-netlists, ensures that each bare chip can have enough resources to arrange each small sub-netlist, and after the positions of all IO ports are fixed, the single-die layout is performed for each die in turn, and when the layout is performed for each die starting from the second die, a virtual stress point is selected on the die to be placed according to the connection relation between the die and all the dies which are already placed and the connection relation between the sub-netlists, under the action of the virtual stress point, the point which has connection relation with the laid bare chip is close to and pulled, so as to achieve the purpose of optimizing the connection relation between the bare chips, the layout method provides a technical basis for realizing a large-scale large-area FPGA chip by cascading a plurality of small-scale small-area bare chips so as to meet the requirement of large logic resources.

Description

Layout method of multi-die structure FPGA
Technical Field
The invention relates to the technical field of FPGA, in particular to a layout method of an FPGA with a multi-die structure.
Background
A Field Programmable Gate Array (FPGA) is a general-purpose Programmable logic device, and a user can flexibly configure the FPGA as required to implement different circuit functions. When designing the FPGA circuit, a user firstly writes a circuit hardware description language according to the circuit function to be realized and converts the circuit hardware description language into a corresponding user input netlist, and then performs layout and wiring on the FPGA chip according to the user input netlist. The number of logic resources of the FPGA chip needs to meet the logic resource requirement of the user input netlist, so that along with the continuous expansion of the user design, the scale of the logic resources of the FPGA chip must be correspondingly increased, but along with the increase of the scale of the chip, the processing difficulty of the chip is higher and higher, and the growth yield of the chip is lower and lower.
Disclosure of Invention
The invention provides a layout method of a multi-die structure FPGA aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
a layout method of a multi-die structure FPGA comprises a silicon connection layer and a plurality of FPGA dies which are arranged on the silicon connection layer in a stacking mode, wherein each FPGA die is provided with a plurality of connection point leading-out ends connected with signal paths inside the FPGA die, the connection point leading-out ends in each FPGA die are connected with the connection point leading-out ends of any other FPGA die through cross-die connection lines in the silicon connection layer to achieve interconnection among the FPGA dies, and the method comprises the following steps:
acquiring a user input netlist, and cutting the user input netlist into a plurality of connected sub-netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub-netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub-netlists;
arranging IO ports on the FPGA bare chips at specified positions according to the sub netlist corresponding to each FPGA bare chip;
for a first FPGA bare chip, the first FPGA bare chip is laid out according to a sub netlist corresponding to the first FPGA bare chip by utilizing a force-oriented layout algorithm model based on the traction action of an IO port at a specified position, and logic units with connection relations between the sub netlists corresponding to other FPGA bare chips on the first FPGA bare chip are arranged at an optimal position and form a connection point on the first FPGA bare chip;
for the (i + 1) th FPGA bare chip, determining that the layout position of a logic unit connected with the connection point on the first i FPGA bare chip through a silicon connection layer on the (i + 1) th FPGA bare chip is the connection point connected with the first i FPGA bare chip on the (i + 1) th FPGA bare chip, adding a virtual stress point corresponding to the p connection point to any p connection point on the (i + 1) th FPGA bare chip according to the selected connection point leading-out end of the q connection point connected with the p connection point on the first i FPGA bare chip, wherein the starting value of i is 1;
according to a sub netlist corresponding to the (i + 1) th FPGA bare chip, laying out the (i + 1) th FPGA bare chip by using a force-oriented layout algorithm model based on the traction action of a virtual force application point on the (i + 1) th FPGA bare chip on a corresponding connection point and the traction action of an IO port at an appointed position;
and i is made to be i +1, and the logic unit layout position connected with the connection point on the first i FPGA bare chips through the silicon connection layer on the i +1 th FPGA bare chip is determined to be the connection point connected with the first i FPGA bare chips on the i +1 th FPGA bare chip again, and the layout is completed until i +1 is N.
The further technical scheme is that the (i + 1) th FPGA bare chip is an FPGA bare chip adjacent to the ith FPGA bare chip.
The further technical scheme is that the (i + 1) th FPGA bare chip is the FPGA bare chip corresponding to the sub-netlist which has the most connection relation with the sub-netlist corresponding to the ith FPGA bare chip.
According to a further technical scheme, a selected connection point leading-out end on the (i + 1) th FPGA bare chip is added with a virtual stress point corresponding to the p connection point according to the q connection point connected with the p connection point on the first i FPGA bare chips, and the method comprises the following steps:
and selecting a connection point leading-out end closest to the qth connection point on the (i + 1) th FPGA die, and adding a virtual stress point corresponding to the pth connection point.
The further technical scheme is that the method also comprises the following steps:
when the (i + 1) th FPGA bare chip is laid out, connecting points connected with the sub netlists corresponding to the subsequent FPGA bare chips on the (i + 1) th FPGA bare chip are randomly arranged at the optimal positions on the (i + 1) th FPGA bare chip, and the subsequent FPGA bare chips comprise the (i + 2) th to the Nth FPGA bare chips.
The further technical scheme is that the method also comprises the following steps:
when the (i + 1) th FPGA bare chip is laid out, connecting points connected with the sub netlists corresponding to the subsequent FPGA bare chips on the (i + 1) th FPGA bare chip are arranged at the optimal positions on the (i + 1) th FPGA bare chip according to the preset sequence, and the subsequent FPGA bare chips comprise the (i + 2) th to the Nth FPGA bare chips.
The further technical scheme is that the preset sequence comprises the following steps:
taking a predetermined position on the (i + 1) th FPGA bare chip as a starting point, and carrying out the sequence of the determinant structure along the transverse direction and the longitudinal direction of the (i + 1) th FPGA bare chip;
or, with a preset preferred position on the (i + 1) th FPGA die as a starting point, the I +1 th FPGA die is arranged along the transverse direction and the longitudinal direction according to the sequence of the S-shaped structure;
or, taking a preset preferred position on the (i + 1) th FPGA die as a starting point, and sequentially arranging the annular structures from outside to inside or from inside to outside along the clockwise or anticlockwise direction.
The further technical scheme is that the arranging of the IO ports on the FPGA bare chip at the designated positions comprises: and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.
The further technical scheme is that the arranging of the IO ports on the FPGA bare chip at the designated positions comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.
The further technical scheme is that the arranging of the IO ports on the FPGA bare chip at the designated positions comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.
According to the further technical scheme, the i +1 th FPGA bare chip is laid out according to the sub-netlist corresponding to the i +1 th FPGA bare chip by using a force-oriented layout algorithm model based on the traction action of a virtual force application point on the i +1 th FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position, and the method comprises the following steps:
regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist;
solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state;
breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure;
and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition.
The beneficial technical effects of the invention are as follows:
the application discloses a layout method of multi-die structure FPGA, which cuts a large user input net list into a plurality of small sub net lists to ensure that each FPGA die can have enough resources to layout each small sub net list, when the single-die layout is performed on each FPGA die in turn, and the single-die layout is performed on each die starting from the second FPGA die, a virtual stress point is selected on the FPGA bare chip according to the connection relation between the FPGA bare chip and all the arranged FPGA bare chips and the connection relation between the sub-netlists, under the action of the virtual stress point, the points which have connection relation with the FPGA bare chips which are already arranged are close to traction, so that the purpose of optimizing the connection relation between the bare chips is achieved, the layout method provides a technical basis for realizing a large-scale and large-area FPGA chip by cascading a plurality of small-scale and small-area FPGA bare chips so as to meet the requirement of large logic resources.
Drawings
FIG. 1 is a simplified side view of the structure of a multi-die architecture FPGA to which the method of the present application is directed.
Fig. 2 is a top view of the corresponding structure of fig. 1.
Fig. 3 is another block diagram of a multi-die architecture FPGA to which the method of the present application is directed.
Fig. 4 is a flow chart of a layout method of the present application.
FIG. 5 is a schematic diagram of connection points and virtual stress points on an FPGA die during a layout process according to the method of the present application.
FIG. 6 is a schematic diagram of a selected sequence of the present application in selecting connection points on an FPGA die.
FIG. 7 is a schematic diagram of another selection sequence for selecting connection points on an FPGA die according to the present application.
FIG. 8 is a schematic diagram of another selection sequence for selecting connection points on an FPGA die according to the present application.
FIG. 9 is a schematic diagram of one of the force guidance placement algorithms.
FIG. 10 is another schematic diagram in a force guidance placement algorithm.
FIG. 11 is another schematic diagram in a force guidance placement algorithm.
FIG. 12 is another schematic diagram in a force guidance placement algorithm.
Fig. 13 is a side view in structural detail of a portion of the structure of fig. 1.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a layout method of a multi-die structure FPGA, which is a layout method for the multi-die structure FPGA, namely the FPGA does not only have one FPGA die but also comprises a plurality of FPGA dies, please refer to the structural schematic diagrams shown in figures 1 and 2, the FPGA dies are all stacked on the same silicon connection layer 1, the silicon connection layer 1 covers all the FPGA dies, figures 1 and 2 show schematic diagrams comprising three FPGA dies, which are respectively represented by a die 1, a die 2 and a die 3. Each FPGA bare chip is provided with a plurality of connection point leading-out terminals 2 connected with the internal signal path of the FPGA bare chip. The silicon connection layer 1 is internally provided with the cross-bare-chip connecting wires 3, the cross-bare-chip connecting wires 3 are distributed in the whole area or partial area of the silicon connection layer 1, and the cross-bare-chip connecting wires 3 are arranged in the silicon connection layer 1 in a layered and crossed manner, so that the cross-bare-chip connecting wires 3 are not influenced with each other. Since the silicon connection layer 1 covers all the FPGA dies, each FPGA die can be connected to any other FPGA die through the cross-die connection 3 according to the circuit requirement, the circuit interconnection between the dies is almost unlimited in space, each FPGA die can be connected to the adjacent FPGA die through the cross-die connection 3, or can be connected to the FPGA die at intervals through the cross-die connection 3, for example, in fig. 1 and 2, the die 1 can be connected to the die 2, and the die 1 can be connected to the die 3.
It should be noted that, in actual implementation, the internal structure of the multi-die FPGA may have a plurality of variations, for example, the plurality of FPGA dies may be arranged on the silicon connection layer 1 in a one-dimensional manner as shown in fig. 2, or may be arranged in a two-dimensional stacking manner, that is, arranged along two directions, i.e., a horizontal direction and a vertical direction, on a horizontal plane, as shown in fig. 3, at this time, a cross-die connection line inside the silicon connection layer 1 is arranged in a crossing manner along the two directions. However, no matter how the structure of the multi-die structure FPGA is deformed, as long as it forms the above-mentioned interconnect structure, it can be laid out by using the method of the present application, and for the convenience of understanding of those skilled in the art, the present application will add to the description of one implementation structure of the multi-die structure FPGA, but first, the present application describes the layout method as follows, and the layout method includes the following steps, please refer to fig. 4:
1. and acquiring a user input netlist, wherein the user input netlist is specific to the whole multi-die structure FPGA, and the total logic resource requirement of the user input netlist exceeds the number of logic resources on any one FPGA die but is less than or equal to the sum of the numbers of logic resources of all FPGA dies.
Firstly, cutting a user input netlist according to the number of logic resources contained in each FPGA bare chip, cutting the user input netlist into a plurality of sub netlists, wherein the sub netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists, so that each FPGA bare chip can have enough resource layout. The cut sub netlists have connection relations, and each sub netlist is connected with one or more other sub netlists, and one or more groups of preset connection relations are included between every two sub netlists.
2. After cutting the user input netlist, arranging the IO ports on the FPGA bare chips at the specified positions according to the sub netlist corresponding to each FPGA bare chip, and fixing the positions of all the IO ports. For each FPGA die, the method for fixing the IO port position according to the sub netlist includes but is not limited to the following methods:
(1) and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.
(2) And arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.
(3) And arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.
3. After all the IO port positions are fixed, for the first FPGA bare chip, the first FPGA bare chip is laid out according to the sub netlist corresponding to the first FPGA bare chip and the traction effect of the IO port at the designated position based on the force-oriented layout algorithm model.
As described above, the sub netlists corresponding to the two FPGA dies have a predetermined connection relationship, and when the first FPGA die is subjected to single-die layout, the logic units on the first FPGA die having the predetermined connection relationship with the sub netlists corresponding to the other FPGA dies are arranged at the preferred positions and formed as connection points on the first FPGA die. As shown in the example of FIG. 5, after the first FPGA die completes the layout of the single die, 4 connection points q having connection relationship with other FPGA dies are formed1,1、q1,2、q1,3And q is1,4. The logic for arranging the logic units as the connection points includes, but is not limited to, the following two types:
(1) and randomly arranging, namely randomly selecting a position of each logic unit with a connection relation between the sub netlists corresponding to other FPGA bare chips on the FPGA bare chips as a preferred position of the logic unit.
(2) Arranging in a preset order, and selecting a position as a preferred position of each logic unit with connection relation between the sub netlists corresponding to other FPGA bare chips on the FPGA bare chip according to the preset order, wherein the preset order comprises but is not limited to the following steps:
(2-1) starting from a predetermined preferred position on the FPGA die, the order of the determinant structures along the lateral and longitudinal directions of the FPGA die. The predetermined positions are typically four corner positions of the FPGA die, and may be any other predetermined position on the FPGA die. The FPGA die comprises the following components in the order of the determinant structure along the transverse direction and the longitudinal direction of the FPGA die: and sequentially selecting each layout position in the current line from the starting point in the transverse direction as a preferred position, and returning to the next line at the starting point to continue to be sequentially selected in the transverse direction after all the layout positions in the current line are selected. Or, sequentially selecting each layout position in the current column from the starting point in the longitudinal direction as a preferred position, and after all the layout positions in the current column are selected, returning to the next column at the starting point to continue the longitudinal sequential selection. The next row may be a row adjacent to the current row, or may be a row spaced several rows apart from the current row, and the same holds true for the definition of the next column. For example, taking the starting point as the upper left corner of the FPGA die as an example, the selected sequence is shown in fig. 6 when the starting point is selected according to the rank-based structure sequence along the horizontal direction and the next row is the adjacent row of the current row.
(2-2) taking a preset preferred position on the FPGA bare chip as a starting point, and sequentially arranging the preset preferred position on the FPGA bare chip along the transverse direction and the longitudinal direction of the FPGA bare chip according to the S-shaped structure, wherein the preset preferred position is usually four vertex angles of the FPGA bare chip, and can also be any other preset position on the FPGA bare chip. The FPGA die comprises the following steps in the order of S-shaped structures along the transverse direction and the longitudinal direction of the FPGA die: and sequentially selecting each layout position in the current line from the starting point in the transverse direction as a preferred position, and after all the layout positions in the current line are selected, continuously and sequentially selecting in the transverse direction from the next line at the last layout position in the current line in the reverse direction. Or, sequentially selecting each layout position in the current column from the starting point in the longitudinal direction as a preferred position, and after all the layout positions in the current column are selected, continuously and sequentially selecting the layout positions in the reverse direction from the next column at the last layout position of the current column. The definition of the next row and the next column is as above, and the detailed description of the present application is omitted. With reference to fig. 6, under the same setting, when the sequence of the S-shaped structure is adopted, please refer to fig. 7 for a schematic sequence diagram.
(2-3) taking a preset preferred position on the FPGA bare chip as a starting point, and sequentially arranging the circular structures from outside to inside or from inside to outside along a clockwise or anticlockwise direction, wherein the preset preferred position is generally four top corner positions of the FPGA bare chip, and can also be any other preset position on the FPGA bare chip. Each ring may be directly adjacent to the previous ring or may be spaced apart. For example, the starting point is the upper left corner of the FPGA die, and the sequence of the ring structures from the outside to the inside along the clockwise direction is selected, please refer to fig. 8.
The principle of the quadratic algorithm used in the single die layout is described as follows:
(1) and (4) building a Quadratic netlist model.
In the placement netlist, all logic cell placement positions can be regarded as nodes, and the signal relationship among all nodes is established as a point-to-point edge relationship. As shown in FIG. 9, there are 5 nodes in the netlist, node A, B, C, D, E, and signal 1 is output from node A to 4 destinations on node B, C, D, E. During modeling, signal 1 is converted into edge 1, edge 2, edge 3 and edge 4 in the graph, and a point- > edge- > point model is formed. Thus, when the layout is performed with the line length as the constraint condition, the shortest line length from the source end a to the destination end B, C, D, E of the signal 1 can be equivalently regarded as the shortest sum of the side lengths of the side 1, the side 2, the side 3 and the side 4. Then the layout optimization goal is to minimize the sum of the lengths of all edges in the netlist for the entire netlist.
As shown in FIG. 9, assume node A (x)1,y1)，B(x2,y2) If the sizes of the nodes A and B are ignored, and the weight of the edge 1 is assumed to be 1, the length of the edge 1 is
Figure GDA0003365948740000071
From the expression of the length of the edge 1, the length of the edge 1 is positively correlated to the expression (x)2-x1)2+(y2-y1)2I.e. length is in (x)2-x1)2+(y2-y1)2Taking the minimum value is to obtain the minimum value.
And (3-2) constructing a solving matrix.
For the entire netlist, assuming n nodes, the optimization objective function can be equivalent to:
Figure GDA0003365948740000072
from the quadratic property of the objective function, the minimum value is obtained when its partial derivative is 0, i.e.:
Figure GDA0003365948740000073
in the form of written matrix equations AX ═ B and AY ═ B. To illustrate by way of an example, as shown in fig. 10, assume A, B, E, F is 4 fixed points in the netlist, wherein the X coordinates of A, B are all 10, the X coordinates of E, F are all 40, and C, D is the layout target point, and the positions need to be determined so that the line length of the whole netlist is minimal. The objective function in the X-direction can be established as:
φ＝(xc-10)2+2(xc-10)2+(xd-xc)2+(xd-40)2+2(xd-40)2
for the target function respectively at xc、xdThe partial derivative is obtained by the above calculation:
Figure GDA0003365948740000074
Figure GDA0003365948740000081
obtaining a minimum value from its partial derivative as 0 to obtain a matrix equation
Figure GDA0003365948740000082
Solved and obtained xc＝16,xdIn this case, the net length is set to 34, i.e., the minimum value. During layout, the X coordinate of the node C is determined to be 16, the X coordinate of the node D is determined to be 34, and the Y-direction coordinate is solved in the similar X direction.
Again in the example above, the X coordinate of the solution knowable node C is 16, D has an X coordinate of 34, then the fixed point A, B can be considered to produce a leftward pull on C in the X direction, as viewed from the C node. The movable point D pair C can be considered to generate a rightward pulling force in the X direction, and the magnitude is as follows: forceright＝wcd(xd-xc) 1 (34-16) ═ 18. It can be seen that point C is in a force balance state in the X direction, and similarly, D is also in a force balance state. After the netlist structure is built by the force model, when the position of the movable point is changed in the layout, the target node can be added with a fixed force according to the force balance model.
(3-3) a congested area spreading method.
The layout positions of the logic units obtained by the method for obtaining the extreme value according to the partial derivative of the quadratic function have logic unit overlap to a large extent, and the premise condition of the legal layout is that the logic units cannot overlap. Therefore, the solved result needs to be expanded, so that the continuous overlapping is reduced.
As shown in fig. 11, there are 1, 2, 3, 4, 5 nodes in the 5 blocks from left to right in sequence, and it is assumed that the maximum capacity of each block in the figure is 3 nodes. The dotted line in the figure is used as a cutting line, and if the number of nodes in unit squares on the left and right sides of the cutting line is the same, a plurality of nodes need to be moved from the left side to the right side of the cutting line or from the right side to the left side of the cutting line. Assuming that the movement from the left to the right of the cut line is positive, how the equation can be established:
Figure GDA0003365948740000083
wherein L isnRepresenting the number of nodes to the left of the cutting line, RnRepresenting the number of nodes to the right of the cutting line, LcRepresenting the sum of the volumes of the squares to the left of the cutting line, RcRepresents the sum of the volumes of the squares to the right of the cut line and P represents the number of nodes that need to be moved to the right. Can be derived from the equation
Figure GDA0003365948740000084
Namely, it is
Figure GDA0003365948740000085
Wherein T iscRepresenting the sum of the capacities of all the squares.
Assuming that the capacity of a square is proportional to the length of the square, we can convert the movement of the node into the movement of the square edge where the cutting line is located, as shown in fig. 11. Assuming that the right movement is positive, the movement of the square edge on which the cutting line is located
Figure GDA0003365948740000086
Where P is the number of nodes that need to be moved to the right, WbIs the width of a single square grid, CbThe capacity of a single square. Assuming the width of the square is 1, then
Figure GDA0003365948740000091
Figure GDA0003365948740000092
According to the solution result, the square edge where the cutting line is located needs to be moved to the left
Figure GDA0003365948740000093
Distance.
In calculating XmThen, the squares representing the left and right sides of the cut line need to be compressed or expanded by a distance XmAnd equivalently, the nodes on the left side and the right side of the cutting line stretch respectively according to the frame. That is, the equation may hold for the node to the left of the cut line:
Figure GDA0003365948740000094
the node to the right of the cut line may be formed as an equation
Figure GDA0003365948740000095
Where min represents the x coordinate of the left boundary of the full row of tiles, max represents the x coordinate of the right boundary of the full row of tiles, LlRepresents the sum of the lengths of the squares to the left of the cutting line, LrRepresenting the sum of the lengths of the squares to the right of the cutting line, xoriRepresenting the original x-coordinate value, x, of the nodenewRepresenting the new coordinates of the required nodes. Through the above equation, the target position of the node can be obtained, and if the positive direction is represented by the rightward direction, it can be obtained that the node needs to move the distance x rightwardnew-xori。
By the method, the cutting line is sequentially moved to the right by one square grid, and the new positions of all the nodes based on node density balance can be obtained by recalculation. After a plurality of iterations, the nodes in the target range can be pulled more uniformly. According to the force model described above, if a node needs to be moved a certain distance in the netlist, how to equivalently think that a force is applied in the moving direction to bring the node to a new equilibrium state. As shown in fig. 12, point D is originally in a force equilibrium state of a, B, and C, and it is now necessary to move D to the position of D ', a fixed point E may be added to the right of point D to generate a force pulling D toward D ', i.e., a pulling force of f ═ D ' -D |. At point E, the weight of the force added can be considered to be
Figure GDA0003365948740000096
Where w represents the weight of the link between D, E, LdeRepresents the distance of D, E in the X direction.
Therefore, when the single-die layout is performed on the first FPGA die based on the algorithm model, the method includes: taking the layout position of the logic unit in the sub-netlist corresponding to the first FPGA bare chip as a node, establishing a signal relation between the nodes into a point-to-point edge relation, establishing a force-oriented layout algorithm model according to the sub-netlist, solving the force-oriented layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state to obtain an initial layout structure, and uniformly spreading the initial layout structure until iteration reaches an iteration termination condition.
4. After the layout of the single bare chip of the ith FPGA bare chip is finished, determining a connection point on the (i + 1) th FPGA bare chip, which is connected with the first i FPGA bare chips which are already laid out, wherein the starting value of i is 1, namely in the first cycle, after the layout of the single bare chip of the first FPGA bare chip is finished, determining a connection point on the second FPGA bare chip, which is connected with the first FPGA bare chip. In a second cycle, after completing the single die layout of the second FPGA die, connection points on the third FPGA die to the first FPGA die and the second FPGA die are determined.
In this application, the first FPGA die may be any one of the FPGAs in the multi-die structure, and for the ith FPGA die that has been laid out, the (i + 1) th FPGA die corresponding to the first FPGA die may be a die closest to the ith FPGA die in the layout position, and it is common to take the (i + 1) th FPGA die as a die adjacent to the ith FPGA die. Or, the common i +1 th FPGA die is the one FPGA die which corresponds to the sub netlist having the most connection relation with the sub netlist corresponding to the i FPGA die and which is not laid out yet. Of course, the (i + 1) th FPGA die may also be a randomly selected one, which is not limited in this application. In the example shown in fig. 5, the layout order is determined according to the layout positions, that is, the first, second, third, and fourth FPGA dies are sequentially subjected to single-die layout according to the adjacent relationship of the layout positions.
As described above, in a designed FPGA with a multi-die structure, two FPGA dies have a certain physical connection relationship, which is represented by: the connection point leading-out terminals 2 in the two FPGA bare chips are connected through cross-bare chip connecting wires 3, and the connection point leading-out terminals are connected in signal paths inside the FPGA bare chips, namely the connection point leading-out terminals are connected with logic unit layout positions inside the FPGA bare chips. Therefore, a physical transmission path is formed by the logic unit layout position a, the connection point leading-out end a, the cross-die connection line, the connection point leading-out end b and the logic unit layout position b, wherein the logic unit layout position a and the connection point leading-out end a are arranged on one FPGA die, and the connection point leading-out end b and the logic unit layout position b are arranged on the other FPGA die. For a multi-die structure FPGA internally comprising N FPGA dies, any one FPGA die in the multi-die structure FPGA has the physical connection relation with all or part of the rest N-1 FPGA dies. On the other hand, the sub-netlist of any one FPGA die has signal connection relation with all or part of the sub-netlists in the rest N-1 FPGA dies in the signal connection relation between the sub-netlists corresponding to the two FPGA dies.
When the multi-die structure FPGA is laid out, the signal connection relationship also exists between the sub netlists corresponding to the FPGA dies which need to be considered and formed, and the essence is that the signal connection relationship between the FPGA dies needs to be formed by utilizing the physical connection paths between the FPGA dies. When the first FPGA die is subjected to single-die layout, the positions of connection points connected with other dies are already arranged on the first FPGA die, such as q in FIG. 51,1、q1,2、q1,3And q is1,4And each connection point has a fixed physical connection relationship with the logic unit layout position of other FPGA dies through a silicon connection layer, such as q in the example shown in FIG. 51,1And p on the second FPGA die2,1Through the cross-die wiring connection of the silicon connection layer, q1,2And p on the second FPGA die2,2Connected by cross-die wiring, q1,3And p on the third FPGA die3,1Connected by cross-die wiring, q1,4And p on the fourth FPGA die4,1Connected by cross-die wires. Therefore, the signal connection relationship between the first FPGA die and other FPGA dies is actually determined, and other circulation processes are similar. Therefore, for the (i + 1) th FPGA die, the logic unit layout position on the (i + 1) th FPGA die connected to the determined connection point on the previous i FPGA die through the silicon connection layer is determined as the connection point on the (i + 1) th FPGA die connected to the previous i FPGA die, for example, in fig. 5, p in the second FPGA die2,1And p2,2I.e. p in the third FPGA die, which is the two connection points to the previous FPGA die3,1And p3,2I.e., the connection point to the first two FPGA dies, p in the fourth FPGA die4,1、p4,2And p4,3I.e., the connection points to the first three FPGA dies, and from this it can be seen that starting with the third FPGA die, it is necessary to determine the connection points to which it is connected to the preceding plurality of FPGA dies.
5. Add virtual stress point respectively for each tie point that links to each other with preceding i FPGA bare chip on i +1 FPGA bare chip, to any one of them pth tie point, select the tie point to draw forth the end and add the corresponding virtual stress point of pth tie point on i +1 FPGA bare chip according to the pth tie point that links to each other with pth tie point on preceding i FPGA bare chip, it is concrete: and selecting a connection point leading-out end closest to the qth connection point on the (i + 1) th FPGA die, and adding a virtual stress point corresponding to the pth connection point. For example, in FIG. 5, the AND-q is selected on the second FPGA die1,1Adding p to the nearest connection point leading-out terminal2,1Corresponding virtual stress point s2,1Selecting and q on the second FPGA die1,2Adding p to the nearest connection point leading-out terminal2,2Corresponding virtual stress point s2,2. As another example, select on the third FPGA die and q1,3Adding p to the nearest connection point leading-out terminal3,1Corresponding virtual stress point s3,1And q is selected on the third FPGA die2,1Adding p to the nearest connection point leading-out terminal3,2Corresponding virtual stress point s3,2，
6. After the virtual force points are added on the (i + 1) th FPGA bare chip, the (i + 1) th FPGA bare chip is laid out according to the sub-netlist corresponding to the (i + 1) th FPGA bare chip by using a force-oriented layout algorithm model based on the traction action of the virtual force points on the (i + 1) th FPGA bare chip on the corresponding connection points and the traction action of the IO port at the specified position.
The single-die layout method for any (i + 1) th FPGA die is similar to the method for performing single-die layout on the first FPGA die, except that the (i + 1) th FPGA die is also dragged by the previous (i) FPGA die based on the virtual stress point, so that the single-die layout method is as follows: regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist; solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state; breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure; and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition. The design of the virtual stress point can lead the points with the connection relation between the (i + 1) th FPGA bare chip and the first i FPGA bare chips to be pulled by the first i FPGA bare chips, thereby achieving the purpose of optimizing the connection relation between the bare chips.
Besides the connection relationship with the first i FPGA bare chips, the (i + 1) th FPGA bare chip also has a connection relationship with each FPGA bare chip which is not laid out subsequently, and each subsequent FPGA bare chip is the (i + 2) th FPGA bare chip to the Nth FPGA bare chip which are not laid out yet. Therefore, when the (i + 1) th FPGA die is laid out, the connection points on the (i + 1) th FPGA die connected to the sub-netlists corresponding to the subsequent FPGA dies are arranged at the preferred positions, for example, in fig. 5, q on the second FPGA die2,1Q on the second FPGA die for its connection point in connection with the third FPGA die2,2Connection points for connection with a fourth FPGA die, e.g. q on a third FPGA die3,1A connection point for which a connection relationship exists with the fourth FPGA die. The specific arrangement logic is the same as that of the first FPGA die, and may be randomly arranged or arranged according to a predetermined order, where the predetermined order may be a horizontal or vertical determinant structure order, or a horizontal or vertical S-type structure order, or a clockwise or counterclockwise direction according to an order of a ring structure from outside to inside or from inside to outside, and it may specifically refer to the above contents, and this application is not described in detail.
7. After finishing the layout of the single die of the (i + 1) th FPGA die, if i +1 is less than N, making i equal to i +1 and repeatedly executing the above steps 4-6 to layout the next FPGA die, and if i +1 equal to N, determining that the layout is finished.
Therefore, having described the layout method for the multi-die FPGA provided in the present application, in order to make those skilled in the art have a clearer understanding of the physical connection relationship between the PFGA dies and thus better understand the layout method of the present application, the present application describes a structure of the multi-die FPGA in detail as follows, please refer to fig. 13, in which the multi-die FPGA includes, in addition to the silicon connection layer 1 and the plurality of dies, a substrate 4 disposed below the silicon connection layer 1, and actually further includes a package housing for protecting each component packaged outside the substrate 4, the silicon connection layer 1 and the FPGA dies, and further includes pins and the like connected to the substrate for signal extraction.
Each FPGA bare chip is provided with a connection point leading-out end 2, the interior of each FPGA bare chip also comprises a logic unit, and the connection point leading-out end 2 is connected with the logic unit in the FPGA bare chip through a top layer metal wire in a redistribution layer (RDL layer). In practical application, the logic unit in the FPGA die includes a conventional logic unit and a silicon stacking connection point 5, the conventional logic unit is a CLB, a PLBs, an IOB, a BRAM, a DSP, a PC, etc., and the silicon stacking connection point is a special logic unit designed specifically inside the die for meeting the signal interconnection requirement between the dies. All logic cells have an interconnection resource distributed around the logic cells, and the logic cells are connected via the interconnection resource such that the silicon stack connection point 5 is connected to other conventional logic cells. And the silicon stack connection point is connected with the connection point leading-out terminal 2 through a top layer metal wire in the RDL layer.
The micro-convex ball grows on the FPGA bare chip, the connection point leading-out end 2 is connected with the silicon connection layer 1 through the micro-convex ball and is connected to other FPGA bare chips through a cross bare chip connection wire 3 inside the silicon connection layer 1, and the micro-convex ball structure at the bottom of the FPGA bare chip can be seen in figure 13. Micro convex balls grow on one side of the silicon connecting layer 1, which is far away from the FPGA bare chip, and the silicon connecting layer 1 is connected with the substrate 4 through the micro convex balls. In addition, a through silicon via 6 is further formed in the silicon connection layer 1, and the IOB on the FPGA bare chip is connected to the substrate 1 through the through silicon via 6 on the silicon connection layer 1 so as to finally lead out a signal.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (10)

1. A layout method of a multi-die structure FPGA is characterized in that the multi-die structure FPGA comprises a silicon connection layer and a plurality of FPGA dies which are stacked on the silicon connection layer, each FPGA die is provided with a plurality of connection point leading-out ends connected with internal signal paths of the FPGA dies, and the connection point leading-out end in each FPGA die is connected with the connection point leading-out end of any other FPGA die through a cross-die connection line in the silicon connection layer to realize interconnection among the FPGA dies, and the method comprises the following steps:
the method comprises the steps of obtaining a user input netlist, cutting the user input netlist into a plurality of connected sub netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub netlists are in one-to-one correspondence with the FPGA bare chips, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists;
arranging IO ports on the FPGA bare chips at specified positions according to the sub netlist corresponding to each FPGA bare chip;
for a first FPGA bare chip, laying out the first FPGA bare chip according to a sub netlist corresponding to the first FPGA bare chip by using a force-oriented layout algorithm model based on the traction action of an IO port at a specified position, wherein logic units with connection relations between the sub netlists corresponding to other FPGA bare chips on the first FPGA bare chip are arranged at a preferred position and form connection points on the first FPGA bare chip;
for the (i + 1) th FPGA bare chip, determining that the layout position of a logic unit connected with the connection point on the (i) th FPGA bare chip through the silicon connection layer on the (i) th FPGA bare chip is the connection point connected with the (i) th FPGA bare chip on the (i + 1) th FPGA bare chip, and for any p-th connection point, selecting a connection point leading-out end on the (i + 1) th FPGA bare chip according to the q-th connection point connected with the p-th connection point on the (i) th FPGA bare chip to add a virtual stress point corresponding to the p-th connection point, wherein the starting value of i is 1;
according to a sub netlist corresponding to the (i + 1) th FPGA bare chip, laying out the (i + 1) th FPGA bare chip by using a force-oriented layout algorithm model based on the traction action of a virtual force application point on the (i + 1) th FPGA bare chip on a corresponding connection point and the traction action of an IO port at a specified position; the method comprises the following steps: taking the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and constructing a force-oriented layout algorithm model according to the sub netlist; solving the force-oriented layout algorithm model under the traction action of the IO port to obtain the position of each node in a force balance state; breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure; uniformly spreading the initial layout structure until iteration reaches an iteration termination condition;
and i is made to be i +1, and the step of determining the layout position of the logic unit connected with the connection point on the first i FPGA bare chips through the silicon connection layer on the i +1 th FPGA bare chip is performed again to be the connection point connected with the first i FPGA bare chips on the i +1 th FPGA bare chip until the layout is completed when i +1 is N.
2. The method of claim 1, wherein the (i + 1) th FPGA die is an FPGA die adjacent to the (i) th FPGA die.
3. The method according to claim 1, wherein the i +1 th FPGA die is the FPGA die corresponding to the sub-netlist having the most connection relation with the sub-netlist corresponding to the i-th FPGA die.
4. The method of claim 1, wherein adding a virtual stress point corresponding to a pth connection point to a selected connection point outlet on an i +1 th FPGA die according to a pth connection point on the first i FPGA die connected to the pth connection point comprises:
and selecting a connection point leading-out end closest to the q-th connection point on the (i + 1) -th FPGA die, and adding a virtual stress point corresponding to the p-th connection point.
5. The method of claim 1, further comprising:
when the (i + 1) th FPGA bare chip is laid out, connecting points connected with the sub netlist corresponding to each subsequent FPGA bare chip on the (i + 1) th FPGA bare chip are randomly arranged at an optimal position on the (i + 1) th FPGA bare chip, and each subsequent FPGA bare chip comprises the (i + 2) th to the Nth FPGA bare chips.
6. The method of claim 1, further comprising:
when the (i + 1) th FPGA bare chip is laid out, connecting points connected with the sub netlists corresponding to the subsequent FPGA bare chips on the (i + 1) th FPGA bare chip are arranged at the optimal positions on the (i + 1) th FPGA bare chip according to the preset sequence, and the subsequent FPGA bare chips comprise the (i + 2) th FPGA bare chip to the Nth FPGA bare chip.
7. The method of claim 6, wherein the predetermined order comprises:
taking a predetermined position on the (i + 1) th FPGA bare chip as a starting point, and arranging the (i + 1) th FPGA bare chip in a sequence of determinant structures along the transverse direction and the longitudinal direction;
or, with a preset preferred position on the (i + 1) th FPGA die as a starting point, the I +1 th FPGA die is arranged along the transverse direction and the longitudinal direction of the (i + 1) th FPGA die according to the sequence of the S-shaped structure;
or, with a preset preferred position on the (i + 1) th FPGA die as a starting point, sequentially arranging the ring structures from outside to inside or from inside to outside along the clockwise or anticlockwise direction.
8. The method of any of claims 1-7, wherein the arranging the IO ports on the FPGA die in the designated locations comprises: and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.
9. The method of any of claims 1-7, wherein the arranging the IO ports on the FPGA die in the designated locations comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.
10. The method of any of claims 1-7, wherein the arranging the IO ports on the FPGA die in the designated locations comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.
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