CN111753483B - Layout method of multi-die structure FPGA - Google Patents

Layout method of multi-die structure FPGA Download PDF

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CN111753483B
CN111753483B CN202010611928.9A CN202010611928A CN111753483B CN 111753483 B CN111753483 B CN 111753483B CN 202010611928 A CN202010611928 A CN 202010611928A CN 111753483 B CN111753483 B CN 111753483B
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fpga
die
connection
bare chip
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CN111753483A (en
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单悦尔
虞健
徐彦峰
惠锋
闫华
张艳飞
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CETC 58 Research Institute
Wuxi Zhongwei Yixin Co Ltd
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Wuxi Zhongwei Yixin Co Ltd
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Abstract

The invention discloses a layout method of a multi-die structure FPGA, relating to the technical field of FPGA, the method cuts a large user input netlist into a plurality of small sub-netlists, ensures that each die has enough resources to lay out each small sub-netlist, after the positions of all IO ports are fixed, selecting a connection point and a virtual stress point on the bare chip according to the connection relation between the bare chips and the connection relation between the sub netlists, then, single-die layout is carried out on each die based on the traction action of a virtual stress point on the die on the corresponding connection point and the traction action of an IO port at a specified position, when the multiple bare chips are separately arranged, the points with the connection relationship among the bare chips are pulled close to one direction, so as to achieve the purpose of optimizing the connection relationship among the bare chips, the layout method provides a technical basis for realizing a large-scale large-area FPGA chip by cascading a plurality of small-scale small-area bare chips so as to meet the requirement of large logic resources.

Description

Layout method of multi-die structure FPGA
Technical Field
The invention relates to the technical field of FPGA, in particular to a layout method of an FPGA with a multi-die structure.
Background
A Field Programmable Gate Array (FPGA) is a general-purpose Programmable logic device, and a user can flexibly configure the FPGA as required to implement different circuit functions. When designing the FPGA circuit, a user firstly writes a circuit hardware description language according to the circuit function to be realized and converts the circuit hardware description language into a corresponding user input netlist, and then performs layout and wiring on the FPGA chip according to the user input netlist. The number of logic resources of the FPGA chip needs to meet the logic resource requirement of the user input netlist, so that along with the continuous expansion of the user design, the scale of the logic resources of the FPGA chip must be correspondingly increased, but along with the increase of the scale of the chip, the processing difficulty of the chip is higher and higher, and the growth yield of the chip is lower and lower.
Disclosure of Invention
The invention provides a layout method of a multi-die structure FPGA aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
a layout method of a multi-die structure FPGA comprises a silicon connection layer and a plurality of FPGA dies which are arranged on the silicon connection layer in a stacking mode, wherein each FPGA die is provided with a plurality of connection point leading-out ends connected with signal paths inside the FPGA die, the connection point leading-out ends in each FPGA die are connected with the connection point leading-out ends of any other FPGA die through cross-die connection lines in the silicon connection layer to achieve interconnection among the FPGA dies, and the method comprises the following steps:
acquiring a user input netlist, and cutting the user input netlist into a plurality of connected sub-netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub-netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub-netlists;
arranging IO ports on the FPGA bare chips at specified positions according to the sub netlist corresponding to each FPGA bare chip;
for any group of preset connection relations between two sub netlists corresponding to any two FPGA bare chips, respectively selecting logic unit layout positions on the two FPGA bare chips as connection points to form a group of connection points corresponding to the preset connection relations, and respectively selecting connection point leading-out ends on the two FPGA bare chips according to the group of connection points to add virtual stress points to form a group of virtual stress points;
after the configuration of the IO port, the connection point and the virtual stress point of each FPGA bare chip is completed, for each FPGA bare chip, the FPGA bare chip is distributed based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position according to the sub-netlist corresponding to the FPGA bare chip and the force-oriented layout algorithm model.
The further technical scheme is that the arranging of the IO ports on the FPGA bare chip at the designated positions comprises: and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.
The further technical scheme is that the arranging of the IO ports on the FPGA bare chip at the designated positions comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.
The further technical scheme is that the arranging of the IO ports on the FPGA bare chip at the designated positions comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.
The further technical scheme is that logic unit layout positions are respectively selected on two FPGA bare chips to serve as connection points to form a group of connection points for forming a preset connection relation, and the method comprises the following steps:
randomly selecting a logic unit layout position on the mth FPGA bare chip as an mth connection point, determining the logic unit layout position on the nth FPGA bare chip, which has a connection relation with the mth connection point through a silicon connection layer, as the nth connection point on the nth FPGA bare chip, wherein the mth connection point and the nth connection point form a group of connection points for forming a preset connection relation.
The further technical scheme is that logic unit layout positions are respectively selected on two FPGA bare chips to serve as connection points to form a group of connection points for forming a preset connection relation, and the method comprises the following steps:
selecting a logic unit layout position on the mth FPGA die as an mth connection point according to a preset selection order, determining that the logic unit layout position on the nth FPGA die, which has a connection relation with the mth connection point through a silicon connection layer, is the nth connection point on the nth FPGA die, and forming a group of connection points for forming a preset connection relation by the mth connection point and the nth connection point;
the further technical scheme is that the preset selection sequence is as follows:
taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip;
or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip;
or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction.
A further technical scheme is that the multi-die structure FPGA comprises T FPGA dies with a preset die sequence, and then the method further comprises the following steps:
selecting a logic unit layout position on the ith FPGA bare chip and each subsequent FPGA bare chip, and respectively forming a preset connection relation between sub netlists corresponding to the ith FPGA bare chip and each subsequent FPGA bare chip, wherein the starting value of i is 1, and each subsequent FPGA bare chip comprises the (i + 1) th FPGA bare chip to the (T) th FPGA bare chip;
and when i is less than T, i is equal to i +1, and the step of selecting the logic unit layout position on the ith FPGA die and the subsequent FPGA dies is executed again.
The further technical scheme is that at least one logic unit layout position is selected on an FPGA bare chip as a connection point in a mode of assisting manual allocation by a software tool.
According to a further technical scheme, the method for forming the group of virtual stress points by respectively selecting the connection point leading-out ends on the two FPGA bare chips according to the group of connection points and adding the virtual stress points comprises the following steps:
adding an mth virtual stress point corresponding to the mth connection point at a connection point leading-out end, which is closest to the mth connection point, on the mth FPGA die for a group of connection points formed by the mth connection point on the mth FPGA die and the nth connection point on the nth FPGA die; and adding an nth virtual stress point corresponding to the nth connection point at the connection point leading-out end closest to the mth virtual stress point on the nth FPGA bare chip, wherein the mth virtual stress point and the nth virtual stress point form a group of virtual stress points.
According to the further technical scheme, the FPGA bare chip is distributed based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position according to the sub netlist corresponding to the FPGA bare chip by using a force-oriented layout algorithm model, and the method comprises the following steps:
regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist;
solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state;
breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure;
and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition.
The beneficial technical effects of the invention are as follows:
the application discloses a layout method of multi-die structure FPGA, which cuts a large user input net list into a plurality of small sub net lists to ensure that each FPGA die can have enough resources to layout each small sub net list, after fixing the positions of all IO ports, selecting a connection point and a virtual stress point on the FPGA bare chip according to the connection relation between the FPGA bare chips and the connection relation between the sub netlists, then, single-die layout is carried out on each FPGA bare chip based on the traction action of a virtual force application point on the FPGA bare chip on the corresponding connection point and the traction action of an IO port at the designated position, when the multiple bare chips are separately arranged, the points with the connection relationship among the bare chips are pulled close to one direction, so as to achieve the purpose of optimizing the connection relationship among the bare chips, the layout method provides a technical basis for realizing a large-scale and large-area FPGA chip by cascading a plurality of small-scale and small-area FPGA bare chips so as to meet the requirement of large logic resources.
Drawings
FIG. 1 is a simplified side view of the structure of a multi-die architecture FPGA to which the method of the present application is directed.
Fig. 2 is a top view of the corresponding structure of fig. 1.
Fig. 3 is another block diagram of a multi-die architecture FPGA to which the method of the present application is directed.
Fig. 4 is a flow chart of a layout method of the present application.
FIG. 5 is a schematic diagram of a selected sequence of the present application in selecting connection points on an FPGA die.
FIG. 6 is a schematic diagram of another selected sequence of the present application in selecting connection points on an FPGA die.
FIG. 7 is a schematic diagram of another selection sequence for selecting connection points on an FPGA die according to the present application.
FIG. 8 is a schematic diagram of connection points and virtual stress points on two FPGA dies in the present application.
FIG. 9 is a schematic flow chart of a force-directed placement algorithm as used herein.
FIG. 10 is a schematic diagram of one of the force guidance placement algorithms.
FIG. 11 is another schematic diagram in a force guidance placement algorithm.
FIG. 12 is another schematic diagram in a force guidance placement algorithm.
FIG. 13 is another schematic diagram in a force guidance placement algorithm.
Fig. 14 is a side view in structural detail of a portion of the structure of fig. 1.
Detailed Description
The application discloses a layout method of a multi-die structure FPGA, which is a layout method for the multi-die structure FPGA, namely the FPGA does not only have one FPGA die but also comprises a plurality of FPGA dies, please refer to the structural schematic diagrams shown in figures 1 and 2, the FPGA dies are all stacked on the same silicon connection layer 1, the silicon connection layer 1 covers all the FPGA dies, figures 1 and 2 show schematic diagrams comprising three FPGA dies, which are respectively represented by a die 1, a die 2 and a die 3. Each FPGA bare chip is provided with a plurality of connection point leading-out terminals 2 connected with the internal signal path of the FPGA bare chip. The silicon connection layer 1 is internally provided with the cross-bare-chip connecting wires 3, the cross-bare-chip connecting wires 3 are distributed in the whole area or partial area of the silicon connection layer 1, and the cross-bare-chip connecting wires 3 are arranged in the silicon connection layer 1 in a layered and crossed manner, so that the cross-bare-chip connecting wires 3 are not influenced with each other. Since the silicon connection layer 1 covers all the FPGA dies, each FPGA die can be connected to any other FPGA die through the cross-die connection 3 according to the circuit requirement, the circuit interconnection between the dies is almost unlimited in space, each FPGA die can be connected to the adjacent FPGA die through the cross-die connection 3, or can be connected to the FPGA die at intervals through the cross-die connection 3, for example, in fig. 1 and 2, the die 1 can be connected to the die 2, and the die 1 can be connected to the die 3.
It should be noted that, in actual implementation, the internal structure of the multi-die FPGA may have a variety of variations, for example, the plurality of FPGA dies may be arranged on the silicon connection layer 1 in a one-dimensional manner as shown in fig. 1 and 2, or may be arranged in a two-dimensional stacking manner, that is, arranged along two directions, i.e., a horizontal direction and a vertical direction, on a horizontal plane, as shown in fig. 3, at this time, a cross-die connection line inside the silicon connection layer 1 is arranged in a cross manner along the two directions. However, no matter how the structure of the multi-die structure FPGA is deformed, as long as it forms the above-mentioned interconnect structure, it can be laid out by using the method of the present application, and for the convenience of understanding of those skilled in the art, the present application will add to the description of one implementation structure of the multi-die structure FPGA, but first, the present application describes the layout method as follows, and the layout method includes the following steps, please refer to fig. 4:
1. and acquiring a user input netlist, wherein the user input netlist is specific to the whole multi-die structure FPGA, and the total logic resource requirement of the user input netlist exceeds the number of logic resources on any one FPGA die but is less than or equal to the sum of the numbers of logic resources of all FPGA dies.
Firstly, cutting a user input netlist according to the number of logic resources contained in each FPGA bare chip, cutting the user input netlist into a plurality of sub netlists, wherein the sub netlists correspond to the FPGA bare chips one to one, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists, so that each FPGA bare chip can have enough resource layout. The cut sub netlists have connection relations, and each sub netlist is connected with one or more other sub netlists, and one or more groups of preset connection relations are included between every two sub netlists.
2. After cutting the user input netlist, arranging the IO ports on the FPGA bare chips at the specified positions according to the sub netlist corresponding to each FPGA bare chip, and fixing the positions of all the IO ports. For each FPGA die, the method for fixing the IO port position according to the sub netlist includes but is not limited to the following methods:
(1) and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.
(2) And arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.
(3) And arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.
3. After all IO port positions are fixed, selecting a connection point on each FPGA bare chip according to the connection relation among all the sub netlists:
as described above, in a designed FPGA with a multi-die structure, two FPGA dies have a certain physical connection relationship, which is represented by: the connection point leading-out terminals 2 in the two FPGA bare chips are connected through cross-bare chip connecting wires 3, and the connection point leading-out terminals are connected in signal paths inside the FPGA bare chips, namely the connection point leading-out terminals are connected with logic unit layout positions inside the FPGA bare chips. Therefore, a physical transmission path is formed by the logic unit layout position a, the connection point leading-out end a, the cross-die connection line, the connection point leading-out end b and the logic unit layout position b, wherein the logic unit layout position a and the connection point leading-out end a are arranged on one FPGA die, and the connection point leading-out end b and the logic unit layout position b are arranged on the other FPGA die.
And the sub netlists corresponding to the two FPGA bare chips also have a signal connection relation, so that the signal connection relation is realized by selecting a physical transmission path in the process of selecting a connection point, namely: and for any group of preset connection relations between any two sub netlists, selecting a physical transmission path between the two corresponding FPGA bare chips, wherein the physical transmission path forms a group of connection points corresponding to the preset connection relations at the layout positions of the two logic units on the two FPGA bare chips, and the physical transmission path formed between the group of connection points is used for forming the preset connection relations.
For any mth FPGA bare chip and nth FPGA bare chip, after the logic unit layout position selected by the mth FPGA bare chip is used as the mth connection point, the mth connection point is fixedly connected with one logic unit layout position on the nth FPGA bare chip through the silicon connection layer 1, so that the logic unit layout position on the nth FPGA bare chip, which is in connection with the mth connection point, is correspondingly determined as the nth connection point. Thus, when selecting a set of connection points on two FPGA dies, only one connection point needs to be actually selected on one of the FPGA dies, and the corresponding other connection point is naturally determined. When selecting a connection point, at least one logic cell layout position is selected as the connection point on the FPGA die by means of manual allocation assisted by a software tool, and the selected logic includes, but is not limited to, the following two types:
(1) and (4) selecting in a random order. Randomly selecting a logic unit layout position on the mth FPGA bare chip as an mth connection point, correspondingly determining the nth connection point on the nth FPGA bare chip, and completing the selection of a group of connection points.
(2) And selecting according to a preset selection order. And selecting a logic unit layout position on the mth FPGA die as an mth connection point according to a preset selection order, and correspondingly determining the nth connection point on the nth FPGA die to finish the selection of a group of connection points. The predetermined selection order includes, but is not limited to, the following:
(2-1) starting from a predetermined position on the FPGA die, in the order of the determinant structure along the lateral and longitudinal directions of the FPGA die. The predetermined positions are typically four corner positions of the FPGA die, and may be any other predetermined position on the FPGA die. The FPGA die comprises the following components in the order of the determinant structure along the transverse direction and the longitudinal direction of the FPGA die: and sequentially selecting logic unit layout positions in the current row from the starting point in the transverse direction as an m-th connection point, and returning to the next row at the starting point to continue to be sequentially selected in the transverse direction after all the logic unit layout positions in the current row are selected. Or, sequentially selecting logic unit layout positions in the current column from the starting point in the longitudinal direction as the mth connection point, and after all the logic unit layout positions in the current column are selected, returning to the next column at the starting point to continue to be sequentially selected in the longitudinal direction. The next row may be a row adjacent to the current row, or may be a row spaced several rows apart from the current row, and the same holds true for the definition of the next column. For example, taking the starting point as the upper left corner of the FPGA die as an example, the selected sequence is shown in fig. 5 when the starting point is selected according to the rank-based structure sequence along the horizontal direction and the next row is the adjacent row of the current row.
And (2-2) taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the predetermined positions along the transverse direction and the longitudinal direction of the FPGA bare chip according to an S-shaped structure, wherein the predetermined positions are usually four vertex angles of the FPGA bare chip and can be any other predetermined position on the FPGA bare chip. The FPGA die comprises the following steps in the order of S-shaped structures along the transverse direction and the longitudinal direction of the FPGA die: and sequentially selecting logic unit layout positions in the current row from the starting point in the transverse direction as an m-th connection point, and after all the logic unit layout positions in the current row are selected, continuously and sequentially selecting the logic unit layout positions in the reverse direction from the next row at the last logic unit layout position in the current row in the transverse direction. Or, sequentially selecting logic unit layout positions in the current column from the starting point in the longitudinal direction as the m-th connection point, and after all the logic unit layout positions in the current column are selected, continuously and sequentially selecting in the reverse direction from the next column at the last logic unit layout position in the current column. The definition of the next row and the next column is as above, and the detailed description of the present application is omitted. With reference to fig. 5, under the same setting, when the sequence of the S-shaped structure is adopted, please refer to fig. 6 for a schematic sequence diagram.
(2-3) taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the annular structures from outside to inside or from inside to outside along a clockwise or anticlockwise direction, wherein the predetermined position is usually four vertex angles of the FPGA bare chip, and can also be any other predetermined position on the FPGA bare chip. Each ring may be directly adjacent to the previous ring or may be spaced apart. For example, the starting point is the upper left corner of the FPGA die, and the sequence of the ring structures from the outside to the inside along the clockwise direction is selected, please refer to fig. 7.
It should be noted that, in the structure shown in fig. 1, when a group of connection points are selected on the die 1 and the die 2, the connection points may be selected on the die 1 to correspondingly determine the connection points on the die 2, or the connection points may be selected on the die 2 to correspondingly determine the connection points on the die 1. And besides the predefined connection relationship between the sub-netlists corresponding to the die 1 and the die 2, the predefined connection relationship may also exist between the sub-netlists corresponding to the die 2 and the die 3, provided that the connection point is selected by using a first selected logic on the die 1 so as to correspondingly determine the connection point on the die 2, and the connection point is defined by using a second selected logic on the die 2 so as to correspondingly determine the connection point on the die 3, the first selected logic and the second selected logic may be the same or different, for example, when the first selected logic is selected in a random order, the second selected logic may be selected in a random order, or may be selected in a sequence of a column structure from a starting point along the transverse direction and the longitudinal direction of the FPGA die. In addition, the die 1 may have a predetermined connection relationship with the sub-netlist corresponding to the die 2 and may also have a predetermined connection relationship with the sub-netlist corresponding to the die 3, and in this case, the connection points on the die 2 and the die 3 are determined by selecting the connection points on the die 1. The method comprises the steps of obtaining a plurality of FPGA dies with a preset die sequence, selecting logic unit layout positions on the ith FPGA die and the subsequent FPGA dies, forming a preset connection relation between sub netlists corresponding to the ith FPGA die and the subsequent FPGA dies respectively, wherein the starting value of i is 1, the subsequent FPGA dies comprise the (i + 1) th FPGA die to the (T) th FPGA die, and when i is less than T, enabling i to be i +1 and executing the step of selecting the logic unit layout positions on the ith FPGA die and the subsequent FPGA dies again. In actual operation, it is assumed that the multi-die FPGA includes 10 FPGA dies, the predetermined die sequence is assumed to be a sequence from die 1 to die 10, further it is assumed that die 1 is connected to die 2, die 3, die 5, and die 9, die 2 is connected to die 1, die 3, die 5, and die 6, and other examples are not detailed, and the general method is as follows: the connection points between the die 2, the die 3, the die 5 and the die 9 are sequentially selected on the die 1 by the first selected logic, so that the connection points on the die 2, the die 3, the die 5 and the die 9 are correspondingly determined, after the connection points on the die 1 are all selected, the connection points between the die 3, the die 5 and the die 6 are sequentially selected on the die 2 by the second selected logic, so that the connection points on the die 3, the die 5 and the die 6 are correspondingly determined, and the like, and the same first selected logic and second selected logic can be the same or different.
4. After selecting the sets of connection points, selecting a corresponding virtual force application point for each set of connection points: and respectively selecting connection point leading-out ends on the two FPGA bare chips to add virtual stress points to form a group of virtual stress points. Because the sub netlists are connected, the connection relation between the FPGA bare chip and other FPGA bare chips needs to be taken into consideration when a certain FPGA bare chip is subjected to single-die layout, and therefore the connection relation between different sub netlists is taken into consideration by adding a virtual stress point on the FPGA bare chip. For a group of connection points formed by an mth connection point on an mth FPGA die and an nth connection point on an nth FPGA die, a method for adding a group of virtual stress points to the group of connection points is as follows: an mth virtual stress point (m 'in the figure) corresponding to the mth connection point is added at the connection point leading-out end closest to the mth connection point (m in the figure) on the mth FPGA die, an nth virtual stress point (n' in the figure) corresponding to the nth connection point (n in the figure) is added at the connection point leading-out end closest to the mth virtual stress point on the nth FPGA die, and the mth virtual stress point and the nth virtual stress point form a group of virtual stress points. As shown in FIG. 8, although FIG. 8 shows the m-th FPGA die and the n-th FPGA die being arranged adjacently, this is also true in the case where the two are not actually adjacent.
5. After the configuration of the IO port, the connection point and the virtual stress point of each FPGA bare chip is completed, for each FPGA bare chip, the FPGA bare chip is distributed based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position according to the sub-netlist corresponding to the FPGA bare chip and the force-oriented layout algorithm model.
Referring to fig. 9, a flow chart of the algorithm of the quadratic algorithm used in the single die layout is shown, and the principle of the quadratic algorithm is described as follows:
and (5-1) establishing a Quadratic netlist model.
In the placement netlist, all logic cell placement positions can be regarded as nodes, and the signal relationship among all nodes is established as a point-to-point edge relationship. As shown in FIG. 10, there are 5 nodes in the netlist, namely A, B, C, D, E, and signal 1 is output from node A to 4 destinations on node B, C, D, E. During modeling, signal 1 is converted into edge 1, edge 2, edge 3 and edge 4 in the graph, and a point- > edge- > point model is formed. Thus, when the layout is based on the wire length as the constraint condition, the shortest wire length from the source end a to the destination end B, C, D, E of the signal 1 can be equivalently regarded as the shortest sum of the side lengths of the side 1, the side 2, the side 3 and the side 4. Then the layout optimization goal is to minimize the sum of the lengths of all edges in the netlist for the entire netlist.
As shown in FIG. 10, assume node A (x)1,y1)，B(x2,y2) If the sizes of the nodes A and B are ignored, and the weight of the edge 1 is assumed to be 1, the length of the edge 1 is
Figure GDA0003351554220000091
From the expression of the length of the edge 1, the length of the edge 1 is positively correlated to the expression (x)2-x1)2+(y2-y1)2I.e. length is in (x)2-x1)2+(y2-y1)2Taking the minimum value is to obtain the minimum value.
(5-2) constructing a solving matrix.
For the entire netlist, assuming n nodes, the optimization objective function can be equivalent to:
Figure GDA0003351554220000092
from the quadratic property of the objective function, the minimum value is obtained when its partial derivative is 0, i.e.:
Figure GDA0003351554220000093
in the form of written matrix equations AX ═ B and AY ═ B. To illustrate, as shown in fig. 11, assuming A, B, E, F are 4 fixed points in the netlist, wherein the X coordinates of A, B are all 10, the X coordinates of E, F are all 40, and C, D is the layout target point, the positions need to be determined so that the line length of the whole netlist is minimal. The objective function in the X-direction can be established as:
φ＝(xc-10)2+2(xc-10)2+(xd-xc)2+(xd-40)2+2(xd-40)2 (1)
for the target function respectively at xc、xdThe partial derivative is obtained by the above calculation:
Figure GDA0003351554220000101
Figure GDA0003351554220000102
obtaining a minimum value from its partial derivative as 0 to obtain a matrix equation
Figure GDA0003351554220000103
Solved and obtained xc＝16,xdIn this case, the net length is set to 34, i.e., the minimum value. During layout, the X coordinate of the node C is determined to be 16, the X coordinate of the node D is determined to be 34, and the Y-direction coordinate is solved in the similar X direction.
Also in the above example, solving for the X coordinate of node C to be 16 and the X coordinate of D to be 34, then, as seen from node C, the fixed point A, B can be considered to produce a leftward pulling force on C in the X direction. The movable point D pair C can be considered to generate a rightward pulling force in the X direction, and the magnitude is as follows: forceright＝wcd(xd-xc) 1 (34-16) ═ 18. It can be seen that point C is in a force balance state in the X direction, and similarly, it can be found that D is also in a force balance stateIs in a force equilibrium state. After the netlist structure is built by the force model, when the position of the movable point is changed in the layout, the target node can be added with a fixed force according to the force balance model.
(5-3) a congested area spreading method.
The logic unit positions obtained by the method for obtaining the extreme value according to the partial derivative of the quadratic function have logic unit overlapping to a large extent, and the premise condition of legal layout is that the logic units cannot be overlapped. Therefore, the solved result needs to be expanded, so that the continuous overlapping is reduced.
As shown in fig. 12, there are 1, 2, 3, 4, 5 nodes in the 5 blocks from left to right in sequence, and it is assumed that the maximum capacity of each block in the figure is 3 nodes. The dotted line in the figure is used as a cutting line, and if the number of nodes in unit squares on the left and right sides of the cutting line is the same, a plurality of nodes need to be moved from the left side to the right side of the cutting line or from the right side to the left side of the cutting line. Assuming that the movement from the left to the right of the cut line is positive, how the equation can be established:
Figure GDA0003351554220000104
wherein L isnRepresenting the number of nodes to the left of the cutting line, RnRepresenting the number of nodes to the right of the cutting line, LcRepresenting the sum of the volumes of the squares to the left of the cutting line, RcRepresents the sum of the volumes of the squares to the right of the cut line and P represents the number of nodes that need to be moved to the right. Can be derived from the equation
Figure GDA0003351554220000105
Namely, it is
Figure GDA0003351554220000106
Wherein T iscRepresenting the sum of the capacities of all the squares.
Assuming that the capacity of a square is proportional to the length of the square, we can convert the movement of the node into the movement of the square edge where the cutting line is located, as shown in fig. 12. Assuming that the right movement is positive, the movement of the square edge on which the cutting line is located
Figure GDA0003351554220000107
Where P is the number of nodes that need to be moved to the right, WbIs the width of a single square grid, CbThe capacity of a single square. Assuming the width of the square is 1, then
Figure GDA0003351554220000111
Figure GDA0003351554220000112
According to the solution result, the square edge where the cutting line is located needs to be moved to the left
Figure GDA0003351554220000113
Distance.
In calculating XmThen, the squares representing the left and right sides of the cut line need to be compressed or expanded by a distance XmAnd equivalently, the nodes on the left side and the right side of the cutting line stretch respectively according to the frame. That is, the equation may hold for the node to the left of the cut line:
Figure GDA0003351554220000114
the node to the right of the cut line may be formed as an equation
Figure GDA0003351554220000115
Where min represents the x coordinate of the left boundary of the full row of tiles, max represents the x coordinate of the right boundary of the full row of tiles, LlRepresents the sum of the lengths of the squares to the left of the cutting line, LrRepresenting the sum of the lengths of the squares to the right of the cutting line, xoriRepresenting the original x-coordinate value, x, of the nodenewRepresenting the new coordinates of the required nodes. Through the above equation, the target position of the node can be obtained, and if the positive direction is represented by the rightward direction, it can be obtained that the node needs to move the distance x rightwardnew-xori。
By the method, the cutting lines are sequentially moved to the right by one square grid and recalculated to obtain all nodes based on node density balanceThe new position of the point. After a plurality of iterations, the nodes in the target range can be pulled more uniformly. According to the force model described above, if a node needs to be moved a certain distance in the netlist, how to equivalently think that a force is applied in the moving direction to bring the node to a new equilibrium state. As shown in fig. 13, point D is originally in a force equilibrium state of a, B, and C, and it is now necessary to move D to the position of D ', a fixed point E may be added to the right of point D to generate a force pulling D toward D ', i.e., a pulling force of f ═ D ' -D |. At point E, the weight of the force added can be considered to be
Figure GDA0003351554220000116
Wherein w represents the weight of the link between D, E, LdeRepresenting D, E distance in the X direction.
Therefore, when the single-die layout is performed on each FPGA die based on the algorithm model, the method comprises the following steps: regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-directed layout algorithm model according to the sub netlist; solving a force guidance layout algorithm model under the traction action of an IO port to obtain the position of each node in a force balance state; breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure; and uniformly spreading the initial layout structure until the iteration reaches an iteration termination condition.
Based on the layout method, in the example shown in fig. 8, when the mth FPGA die layout is solved, the mth virtual stress point pulls the mth connection point to approach to the mth virtual stress point, and when the nth FPGA die layout is solved, the nth virtual stress point pulls the nth connection point to approach to the nth virtual stress point. Therefore, when the multiple bare chips are separately arranged, the points with the connection relation among the bare chips can be pulled close to one direction, and the purpose of optimizing the connection relation among the bare chips is achieved.
Thus, having described the layout method for the multi-die FPGA provided in the present application, in order to make the skilled person have a clearer understanding of the physical connection relationship between the PFGA dies and thus better understand the layout method of the present application, the present application describes a structure of the multi-die FPGA in detail as follows, please refer to fig. 14, the multi-die FPGA includes, in addition to the silicon connection layer 1 and the plurality of dies, a substrate 4 disposed below the silicon connection layer 1, and actually further includes a package housing packaged outside the substrate 4, the silicon connection layer 1 and the FPGA dies for protecting each component, and further includes pins and the like connected to the substrate for signal extraction.
Each FPGA bare chip is provided with a connection point leading-out end 2, the interior of each FPGA bare chip also comprises a logic unit, and the connection point leading-out end 2 is connected with the logic unit in the FPGA bare chip through a top layer metal wire in a redistribution layer (RDL layer). In practical application, the logic unit in the FPGA die includes a conventional logic unit and a silicon stacking connection point 5, the conventional logic unit is a CLB, a PLBs, an IOB, a BRAM, a DSP, a PC, etc., and the silicon stacking connection point is a special logic unit designed specifically inside the die for meeting the signal interconnection requirement between the dies. All logic cells have an interconnection resource distributed around the logic cells, and the logic cells are connected via the interconnection resource such that the silicon stack connection point 5 is connected to other conventional logic cells. And the silicon stack connection point is connected with the connection point leading-out terminal 2 through a top layer metal wire in the RDL layer.
The micro-convex ball grows on the FPGA bare chip, the connection point leading-out end 2 is connected with the silicon connection layer 1 through the micro-convex ball and is connected to other FPGA bare chips through a cross bare chip connection wire 3 inside the silicon connection layer 1, and the micro-convex ball structure at the bottom of the FPGA bare chip can be seen in figure 14. Micro convex balls grow on one side of the silicon connecting layer 1, which is far away from the FPGA bare chip, and the silicon connecting layer 1 is connected with the substrate 4 through the micro convex balls. In addition, a through silicon via 6 is further formed in the silicon connection layer 1, and the IOB on the FPGA bare chip is connected to the substrate 1 through the through silicon via 6 on the silicon connection layer 1 so as to finally lead out a signal.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (9)

1. A layout method of a multi-die structure FPGA is characterized in that the multi-die structure FPGA comprises a silicon connection layer and a plurality of FPGA dies which are stacked on the silicon connection layer, each FPGA die is provided with a plurality of connection point leading-out ends connected with internal signal paths of the FPGA dies, and the connection point leading-out end in each FPGA die is connected with the connection point leading-out end of any other FPGA die through a cross-die connection line in the silicon connection layer to realize interconnection among the FPGA dies, and the method comprises the following steps:
the method comprises the steps of obtaining a user input netlist, cutting the user input netlist into a plurality of connected sub netlists according to the number of logic resources contained in each FPGA bare chip, wherein the sub netlists are in one-to-one correspondence with the FPGA bare chips, and the number of the logic resources on each FPGA bare chip meets the logic resource requirements of the corresponding sub netlists;
arranging IO ports on the FPGA bare chips at specified positions according to the sub netlist corresponding to each FPGA bare chip;
for any group of preset connection relations between two sub netlists corresponding to any two FPGA bare chips, respectively selecting logic unit layout positions on the two FPGA bare chips as connection points to form a group of connection points corresponding to the preset connection relations, and respectively selecting connection point leading-out ends on the two FPGA bare chips according to the group of connection points to add virtual stress points to form a group of virtual stress points;
after the configuration of the IO port, the connection point and the virtual stress point of each FPGA bare chip is completed, for each FPGA bare chip, the FPGA bare chip is distributed according to a sub-netlist corresponding to the FPGA bare chip by using a force-oriented distribution algorithm model based on the traction action of the virtual stress point on the FPGA bare chip on the corresponding connection point and the traction action of the IO port at the specified position;
wherein the selecting logic cell layout positions on the two FPGA dies respectively as connection points to form a group of connection points for forming the predetermined connection relationship comprises:
randomly selecting a logic unit layout position on an mth FPGA bare chip as an mth connection point, and determining that the logic unit layout position on the nth FPGA bare chip, which has a connection relation with the mth connection point through the silicon connection layer, is the nth connection point on the nth FPGA bare chip, wherein the mth connection point and the nth connection point form a group of connection points for forming the preset connection relation;
or, selecting a logic unit layout position on the mth FPGA die as an mth connection point according to a predetermined selection order, determining that the logic unit layout position on the nth FPGA die, which has a connection relationship with the mth connection point through the silicon connection layer, is the nth connection point on the nth FPGA die, and the mth connection point and the nth connection point form a group of connection points for forming the predetermined connection relationship.
2. The layout method of claim 1, wherein the arranging the IO ports on the FPGA die at designated locations comprises: and manually arranging at least one IO port on the FPGA bare chip at a specified position by using an IO EDITOR software tool.
3. The layout method of claim 1, wherein the arranging the IO ports on the FPGA die at designated locations comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to any sequence.
4. The layout method of claim 1, wherein the arranging the IO ports on the FPGA die at designated locations comprises: and arranging at least one IO port on the FPGA bare chip at a specified position according to an IO automatic arrangement algorithm.
5. The layout method according to claim 1, wherein the predetermined selection order is:
taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the FPGA bare chip in a determinant structure along the transverse direction and the longitudinal direction of the FPGA bare chip;
or, taking a predetermined position on the FPGA bare chip as a starting point, and sequentially arranging the S-shaped structures along the transverse direction and the longitudinal direction of the FPGA bare chip;
or, starting from a predetermined position on the FPGA die, the order of the ring structures from outside to inside or from inside to outside along the clockwise or counterclockwise direction.
6. The layout method according to claim 1, wherein the multi-die structure FPGA includes T FPGA dies having a predetermined die order, the method further comprising:
selecting a logic unit layout position on the ith FPGA bare chip and each subsequent FPGA bare chip, and respectively forming a preset connection relation between sub netlists corresponding to the ith FPGA bare chip and each subsequent FPGA bare chip, wherein the starting value of i is 1, and each subsequent FPGA bare chip comprises the (i + 1) th FPGA bare chip to the (T) th FPGA bare chip;
and when i is less than T, i is equal to i +1, and the step of selecting the logic unit layout position on the ith FPGA die and the subsequent FPGA dies is executed again.
7. The layout method according to claim 1, wherein at least one logic cell layout position is selected as a connection point on the FPGA die by means of manual assignment assisted by a software tool.
8. The layout method according to any one of claims 1 to 7, wherein the adding of the virtual stress points to the connection point outlets respectively selected on the two FPGA dies according to the set of connection points to form a set of virtual stress points comprises:
adding an mth virtual stress point corresponding to an mth connection point at a connection point leading-out end closest to the mth connection point on the mth FPGA die for a group of connection points formed by the mth connection point on the mth FPGA die and the nth connection point on the nth FPGA die; adding an nth virtual stress point corresponding to the nth connection point at a connection point leading-out end closest to the mth virtual stress point on the nth FPGA die, wherein the mth virtual stress point and the nth virtual stress point form a group of virtual stress points.
9. The layout method according to any one of claims 1 to 7, wherein the step of laying out the FPGA die according to the sub netlist corresponding to the FPGA die by using a force-oriented layout algorithm model based on a traction effect of a virtual force application point on the FPGA die on a corresponding connection point and a traction effect of an IO port at a specified position comprises the following steps:
regarding the layout positions of the logic units in the sub netlist as nodes, establishing a signal relationship between the nodes into a point-to-point edge relationship, and establishing a force-oriented layout algorithm model according to the sub netlist;
solving the force-oriented layout algorithm model under the traction action of the IO port to obtain the position of each node in a force balance state;
breaking the force balance state under the traction action of the virtual stress point on the corresponding node serving as the connection point, and solving the force-oriented layout algorithm model again to obtain an initial layout structure;
and uniformly spreading the initial layout structure until iteration reaches an iteration termination condition.
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