CN111745531B - Curved surface grinding device and chip extraction method - Google Patents
Curved surface grinding device and chip extraction method Download PDFInfo
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- CN111745531B CN111745531B CN202010625113.6A CN202010625113A CN111745531B CN 111745531 B CN111745531 B CN 111745531B CN 202010625113 A CN202010625113 A CN 202010625113A CN 111745531 B CN111745531 B CN 111745531B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/11—Lapping tools
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/34—Accessories
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L21/67092—Apparatus for mechanical treatment
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
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- H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/7855—Mechanical means, e.g. for severing, pressing, stamping
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention provides a curved surface grinding device and a chip extraction method, wherein the device is used for grinding the curved surface of a chip and comprises the following steps: the grinding surface supporting cylinder and the grinding sleeve are sleeved outside the grinding surface supporting cylinder, and the grinding sleeve is used for rotating the grinding surface supporting cylinder as an axis to grind the curved surface of the chip. Like this, it is rotatory to grind the sleeve through lapping surface support cylinder control, grinds the chip curved surface, and at the in-process of grinding, because the surface that grinds the sleeve is the curved surface to make grind the sleeve and can be in good contact with the position selectivity of waiting to grind of chip curved surface, and then can grind the position of waiting to grind of chip curved surface selectively, the metal contact of lapping before avoiding grinding the interconnect line.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a curved surface grinding device and a chip extraction method.
Background
When the chip in the package body fails, the failed chip, i.e., the target chip, needs to be extracted from the package body, and then the target chip is detected.
The existing method for extracting the target chip mainly adopts a plane grinding device to grind the interconnection line of the target chip until the metal contact of the target chip is exposed so as to electrically disconnect the target chip from other chips in the packaging body, and then the target chip is extracted from the packaging body.
However, in the process of grinding the interconnection line of the target chip, because the surface of the chip is uneven or the curvature of the chip is large, metal contact can be ground before the interconnection line is ground, so that the metal contact is damaged, and a follow-up probe cannot be effectively connected with the metal contact, thereby affecting the detection of the target chip.
Disclosure of Invention
In view of the above, the present invention provides a curved surface polishing apparatus and a chip extracting method, which can prevent metal contacts from being damaged.
In order to achieve the purpose, the invention has the following technical scheme:
the utility model provides a curved surface grinder, the device is used for the chip curved surface to grind, includes:
a lapping surface support cylinder and a lapping sleeve;
the grinding sleeve is sleeved outside the grinding surface supporting cylinder;
and the grinding sleeve is used for grinding the curved surface of the chip by taking the grinding surface supporting cylinder as an axis to rotate.
Optionally, the length of the grinding sleeve is less than the length of the grinding surface support cylinder.
Optionally, an adhesive layer is disposed between the grinding sleeve and the grinding surface supporting cylinder.
Optionally, the radius of the grinding surface support cylinder is determined according to the size of the curved surface of the chip.
A method of chip extraction using the apparatus of any one of the above, comprising:
grinding the interconnection line of the target chip in the chip stack by using the grinding sleeve sleeved on the grinding surface supporting cylinder in the curved surface grinding device until the metal contact of the target chip is exposed so as to disconnect the electric connection between the target chip and other chips in the chip stack;
extracting the target chip from the chip stack.
Optionally, the first surface of the target chip is coated with a protective layer;
the extracting the target chip from the chip stack specifically includes:
and corroding the protective layer and extracting the target chip from the chip stack.
Optionally, the etching the protection layer and extracting the target chip from the chip stack specifically include:
and placing the stacked chip in an organic solvent for heating, and corroding the protective layer to extract the target chip from the chip stack.
Optionally, before the grinding the interconnection line of the target chip in the chip stack by using the curved surface grinding device, the method further includes:
and grinding other chips in the chip stack by adopting a plane grinding device until the interconnecting wire of the target chip is exposed.
Optionally, the method further includes:
and adhering the second surface of the target chip on the glass slide, and detecting the first surface of the target chip.
Optionally, a chip connection film is adhered to the second surface of the target chip;
after the extracting the target chip from the chip stack, the method further includes:
and adhering the first surface of the target chip on the glass slide, removing the chip connecting film on the second surface of the target chip, and detecting the second surface of the target chip.
The embodiment of the invention provides a curved surface grinding device, which is used for grinding the curved surface of a chip and comprises: the grinding surface supporting cylinder and the grinding sleeve are sleeved outside the grinding surface supporting cylinder, and the grinding sleeve is used for rotating the grinding surface supporting cylinder as an axis to grind the curved surface of the chip. Like this, it is rotatory to grind the sleeve through lapping surface support cylinder control, grinds the chip curved surface, and at the in-process of grinding, because the surface that grinds the sleeve is the curved surface to make grind the sleeve and can be in good contact with the position selectivity of waiting to grind of chip curved surface, and then can grind the position of waiting to grind of chip curved surface selectively, the metal contact of lapping before avoiding grinding the interconnect line.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic view showing a structure of a curved surface grinding apparatus according to an embodiment of the present invention;
FIG. 2 shows a schematic top view of a curved surface grinding apparatus according to an embodiment of the present invention;
fig. 3-7 show schematic structural diagrams of chip extraction according to embodiments of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background art, in the process of grinding the interconnection line of the target chip, the existing plane grinding device can grind metal contact before grinding the interconnection line due to the uneven surface of the chip or the large curvature of the chip, so that the metal contact is damaged, and the subsequent probe cannot be effectively connected with the metal contact, thereby affecting the detection of the target chip.
For this reason, this application provides a curved surface grinder, and the device is used for the chip curved surface to grind, includes: the grinding surface supporting cylinder and the grinding sleeve are sleeved outside the grinding surface supporting cylinder, and the grinding sleeve is used for rotating the grinding surface supporting cylinder as an axis to grind the curved surface of the chip. Like this, it is rotatory to grind the sleeve through lapping surface support cylinder control, grinds the chip curved surface, and at the in-process of grinding, because the surface that grinds the sleeve is the curved surface to make grind the sleeve and can be in good contact with the position selectivity of waiting to grind of chip curved surface, and then can grind the position of waiting to grind of chip curved surface selectively, the metal contact of lapping before avoiding grinding the interconnect line.
In order to facilitate understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
The embodiment of the present application provides a curved surface grinding device, refer to fig. 1 and fig. 2, is used for the grinding of chip curved surface, includes: abrasive surface support cylinder 120 and abrasive sleeve 100;
the polishing sleeve 100 is sleeved outside the polishing surface supporting cylinder 120;
the grinding sleeve 100 is used for grinding the curved surface of the chip by rotating around the grinding surface supporting cylinder 120.
In the embodiment of the present application, the grinding surface supporting cylinder 120 is used for controlling the grinding sleeve 100 to rotate, and the grinding surface supporting cylinder 120 can be rotated to further drive the grinding sleeve 100 to rotate, and in the process of rotating the grinding surface supporting cylinder 120 and the grinding sleeve 100, the grinding surface supporting cylinder 120 and the grinding sleeve 100 can be in a relatively static state, that is, the rotation speeds of the grinding surface supporting cylinder 120 and the grinding sleeve 100 can be the same. In a specific application, the grinding surface supporting cylinder 120 and the grinding sleeve 100 may be an integral structure, and the grinding surface supporting cylinder 120 and the grinding sleeve 100 may also be a non-integral structure, and the grinding surface supporting cylinder 120 and the grinding sleeve 100 may be adhered together by the adhesive layer 110.
In this embodiment, the radius of the grinding surface supporting cylinder 120 can be determined according to the size of the curved surface of the chip, and usually sand paper or polishing cloth is selected as the grinding sleeve 100 adhered on the surface of the grinding surface supporting cylinder 120, and the size of the curved surface of the chip basically determines the radius of the grinding supporting cylinder 120 due to the smaller thickness of the sand paper or polishing cloth. The radius of the grinding surface supporting cylinder 120 is set according to the size of the curved surface of the chip, so that the grinding sleeve 100 is in good contact with the curved surface of the chip, and the grinding effect of the grinding sleeve 100 on the curved surface of the chip is improved. In a specific application, sandpaper or polishing cloth can be adhered to the surface of the abrasive surface support cylinder 120 through the adhesive layer 110, and the adhesive layer 110 can be, for example, an adhesive such as a double-sided tape.
In this embodiment, the length of the polishing sleeve 100 may be smaller than the length of the polishing surface supporting cylinder 120, and it can be understood that the polishing sleeve 100 is only sleeved on a certain portion of the polishing surface supporting cylinder 120, and then the polishing sleeve is controlled to rotate to polish the curved surface of the chip by controlling a portion of the polishing surface supporting cylinder 120 not sleeved by the polishing sleeve 100. For example, the polishing sleeve 100 can be sleeved on a first end of the polishing surface support cylinder 120, the first end of the polishing sleeve 100 is flush with the first end of the polishing surface support cylinder 120, and then the polishing sleeve 100 is controlled to rotate by controlling a second end of the polishing surface support cylinder 120. In other embodiments, a central shaft may be disposed at the center of the polishing surface supporting cylinder 120, and the polishing surface supporting cylinder 120 is driven to rotate by the central shaft, so as to drive the polishing sleeve 100 to rotate, thereby polishing the curved surface of the chip.
The curved surface polishing apparatus provided by the embodiments of the present application is described above in detail, and the embodiments of the present application also provide a method for extracting a chip by using the curved surface polishing apparatus, which will be described in detail below with reference to the accompanying drawings and specific embodiments.
In step S01, the grinding sleeve 100 sleeved on the grinding surface supporting cylinder 120 in the curved surface grinding device is used to grind the interconnection line of the target chip in the chip stack until the metal contact of the target chip is exposed, so as to disconnect the electrical connection between the target chip and other chips in the chip stack, as shown in fig. 3-6.
In the embodiment of the present application, the chip stack may include two or more chips, each chip in the chip stack may be formed with a device structure and an interconnection structure electrically connected to the device structure, the device structure is formed on the substrate, and the device structure may include a MOS device, a sensing device, a memory device, or other passive devices other than capacitors. The interconnect structure may include contact plugs, vias, and wiring levels, which may include one or more layers, and may be a metal material, which may be, for example, tungsten, aluminum, copper, etc. The individual chips may have the same or different device structures, and the different device structures may be different types of devices or the same type of devices having different operating voltages.
In the embodiment of the application, the chip stacking can be the chip stacking in the packaging body, and due to the fact that the chip possibly fails in the packaging process, the failed chip needs to be electrically disconnected with other chips after the specific position of the failed chip in the chip stacking is determined, so that the failed chip can be detected and analyzed, and the failed chip is the target chip.
Taking an example that the chip stack includes four chips as an example, the chip stack includes a first chip 210, a second chip 220, a third chip 230, and a fourth chip 240, and referring to fig. 3, a process of packaging the chip stack to form a package may be to stack the first chip 210, the second chip 220, the third chip 230, and the fourth chip 240 on the substrate 200 in sequence. Specifically, the first chip 210 may be stacked on the substrate 200, the second surface of the first chip 210 is in contact with the substrate 200, the second surface is an opposite surface of the first surface, the first metal contact 212 is formed on the first surface of the first chip 210, and the first metal contact 212 in the first chip 210 and an interconnection line (not shown) in the substrate 200 are connected by the first interconnection line 211 to electrically connect the first chip 210 and the substrate 200. And then stacking a second chip 220 on the first surface of the first chip 210, wherein a second metal contact 222 is formed on the first surface of the second chip 220, and the first metal contact 212 in the first chip 210 and the second metal contact 222 in the second chip 220 are connected through a second interconnection line 221, so that the first chip 210 and the second chip 220 are electrically connected. And then stacking a third chip 230 on the first surface of the second chip 220, wherein a third metal contact 234 is formed on the first surface of the third chip 220, and the second metal contact 222 in the second chip 220 and the third metal contact 234 in the third chip 230 are connected through a third interconnection line 233, so as to electrically connect the second chip 220 and the third chip 230. Subsequently, a fourth chip 240 is stacked on the first surface of the third chip 230, a fourth metal contact 242 is formed on the first surface of the fourth chip 240, the third metal contact 234 and the fourth metal contact 242 are connected by a fourth interconnecting line 235, and the third chip 230 and the fourth chip 240 are electrically connected, so that the electrical connection between the respective chips is achieved through the interconnecting line and the metal contact. Finally, the chip stack is encapsulated by the encapsulation resin 202 to form a package. The encapsulation resin 202 may prevent the chip stack from suffering damage. In this embodiment, after the first chip 210, the second chip 220, the third chip 230, and the fourth chip 240 are stacked to form a chip stack, the chip stack may be electrically connected to the substrate 200, and then the chip stack may be encapsulated by the encapsulation resin 202. In a specific embodiment, the first surface of each chip may be formed with a chip attachment film (die attachment film), and the chips may be attached together through the die attachment film. The second surface of each chip may be formed with a protective layer to prevent the chips from being damaged during the stacking process. The protective layer may be, for example, polyimide (polyimide).
In this embodiment, taking the target chip as the third chip 230 for example, the other chips in the chip stack may be ground by using a plane grinding apparatus until the third interconnection lines 233 of the third chip 230 are exposed, as shown in fig. 4. Specifically, the encapsulation resin 240 and the fourth chip 240 may be ground by a plane grinding apparatus until the top of the third interconnection line 233 of the third chip 230. Since the target chip is the third chip 230, the fourth chip 240 on the first surface of the third chip 230 needs to be removed, and the fourth chip 240 can be removed by grinding faster by the plane grinding apparatus. Specifically, the fourth chip 240 may be removed by grinding with 320-360 mesh sandpaper. However, for the third chip 230, in the process of removing the fourth chip 240 by polishing with the plane polishing apparatus, unevenness such as pits may be generated on the polished surface, or in the process of packaging, the chip may be bent due to thermal expansion and cold contraction, so that the height of the third metal contact 234 in the third chip 230 is higher than the height of a part of the third interconnection line 233, and in the process of polishing the third interconnection line 233, the third metal contact 234 may be polished first, or the third interconnection line 233 on the third metal contact 234 after polishing the third interconnection line 233 is too long, so that the needle platform on the target chip is uneven, and poor contact of the probe is caused.
Therefore, in the embodiment of the present application, the interconnection line 233 of the third chip 230, which is the target chip in the chip stack, is ground by using the curved surface grinding device until the metal contact 234 of the third chip 230 is exposed, so as to disconnect the electrical connection between the third chip 230 and other chips in the chip stack, as shown in fig. 5. Specifically, after the fourth chip 240 is removed until the top of the third interconnection line 233 of the third chip 230, the grinding surface supporting cylinder 120 in the curved surface grinding device is rotated to drive the grinding sleeve 100 sleeved outside the grinding surface supporting cylinder 120 to rotate, the grinding sleeve 100 is in contact with the third interconnection line 233, and the grinding sleeve 100 rubs against the third interconnection line 233 in the rotating process, so as to grind the third interconnection line 233. Because grinding sleeve 100 is cylindric, can be with the chip curved surface treat the position of grinding good contact, play fine grinding effect, because the surface of grinding sleeve 100 is the curved surface moreover for grinding sleeve 100 can grind the position of treating grinding selectively. For example, the grinding sleeve 100 is in contact with the third interconnect 233, the surface of the grinding sleeve 100 is a curved surface, and when the grinding sleeve 100 is in contact with the third interconnect 233, the grinding sleeve cannot be in contact with other surfaces, so that the effect of grinding only the third interconnect 233 is achieved, the situation that the third metal contact 234 is ground first in the process of grinding the third interconnect 233 is avoided, and the grinding precision is improved. Since the polishing sleeve 100 has a cylindrical shape and can rotate, the polishing efficiency can be improved by selecting the polishing sleeve 100 and polishing the third interconnection line 233.
The rotation of the grinding surface support cylinder 120 among the curved surface grinding device in this application embodiment drives grinding sleeve 100 and rotates, and the position of waiting to grind of selectivity grinding chip curved surface avoids grinding the metal contact before grinding the interconnect line for the probe can be effectively connected with the metal contact.
In step S02, the target chip is extracted from the chip stack, as shown with reference to fig. 6 and 7.
In this embodiment, the first surface of the target chip, i.e., the third chip 230, is coated with the protection layer 231, and the target chip can be extracted from the chip stack by etching the protection layer 231 to disconnect the third chip 230 from other chips in the chip stack. Specifically, as shown in fig. 6, after the third interconnection lines 233 are ground by the curved surface grinding apparatus, the electrical connection lines between the third chip 230 and the second chip 220 are disconnected, the third chip 230 and the second chip 220 are only physically bonded together, then the protective layer 231 is etched, the protective layer between the chips is removed in the process of etching the protective layer 231 of the third chip 230, so that the physical connection between the third chip 230 and the second chip 220 is also disconnected, and the third chip 230 is extracted from the chip stack, as shown in fig. 7, the third chip 230 is completely disconnected from the first chip 210 and the second chip 220, and the first chip 210 and the second chip 220 are electrically connected together because the second interconnection lines 221 are not disconnected.
In this embodiment, when the chip stack is located in the package body, the curved surface grinding device may grind the third interconnection line 233 to disconnect the third chip 230 from the electrical connection with other chips in the chip stack, and then place the ground package body on the heating table for heating, where the temperature of the heating table may be 50 to 90 degrees, and then drop 1 to 2 drops of fuming nitric acid on the package body, where the fuming nitric acid reacts with the package resin 202 for a period of time, for example, 5 to 10 seconds. The reacted encapsulation resin is then rinsed away with acetone or a similar solvent to acetone to expose the entire chip stack, as shown with reference to fig. 6. Then, the exposed chip stack is immersed in an organic solvent, such as a solvent for removing polyimide, and heated, the protective layer between the chips is dissolved and removed in the organic solvent, and the third chip 230 is disconnected from other chips, thereby separating the third chip 230 from the chip stack, as shown in fig. 7.
In this embodiment, after the third chip 230 is extracted from the chip stack, the third chip 230 may be placed on a glass slide, the second surface of the third chip 230 is bonded to the glass slide by a hot melt adhesive, and the first surface of the third chip 230 may be subjected to probe card testing and dynamic hot spot analysis. After the third chip 230 is extracted from the chip stack, the first surface of the third chip 230 may be bonded to a glass slide by thermosol, and then the chip connection film 232 on the second surface of the third chip 230 may be removed by fuming nitric acid, so as to perform probe card probe testing and dynamic hotspot analysis on the second surface of the third chip 230.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (6)
1. A method for extracting a chip by using a curved surface grinding device is characterized by comprising the following steps:
grinding the interconnection line of the target chip in the chip stack by using a grinding sleeve sleeved on the grinding surface supporting cylinder in the curved surface grinding device until the metal contact of the target chip is exposed so as to disconnect the electric connection between the target chip and other chips in the chip stack;
extracting the target chip from the chip stack.
2. The method of claim 1, wherein the first surface of the target chip is coated with a protective layer;
the extracting the target chip from the chip stack specifically includes:
and corroding the protective layer and extracting the target chip from the chip stack.
3. The method according to claim 2, wherein said etching of said protective layer extracts said target chip from said chip stack, in particular:
and placing the stacked chip in an organic solvent for heating, and corroding the protective layer to extract the target chip from the chip stack.
4. The method according to claim 1 or 2, wherein before the grinding the interconnection line of the target chip in the chip stack by using the curved surface grinding device, the method further comprises:
and grinding other chips in the chip stack by adopting a plane grinding device until the interconnecting wire of the target chip is exposed.
5. The method of claim 1 or 2, further comprising:
and adhering the second surface of the target chip on the glass slide, and detecting the first surface of the target chip.
6. The method according to claim 1 or 2, wherein a chip connection film is adhered to the second surface of the target chip;
after the extracting the target chip from the chip stack, the method further includes:
and adhering the first surface of the target chip on the glass slide, removing the chip connecting film on the second surface of the target chip, and detecting the second surface of the target chip.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110090696A (en) * | 2010-02-04 | 2011-08-10 | 한국생산기술연구원 | Method of separating semiconductor chip from package |
| CN102629604A (en) * | 2012-04-06 | 2012-08-08 | 天水华天科技股份有限公司 | Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package |
| CN105789059A (en) * | 2016-04-19 | 2016-07-20 | 浙江中纳晶微电子科技有限公司 | Method for separating bonded wafers |
| CN105818008A (en) * | 2016-03-23 | 2016-08-03 | 陈志同 | Complex generatrix polishing wheel with local reinforcement structure and manufacturing method thereof |
| CN109946586A (en) * | 2019-02-12 | 2019-06-28 | 长江存储科技有限责任公司 | The detection method of chip electrical connection defect |
-
2020
- 2020-07-01 CN CN202010625113.6A patent/CN111745531B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110090696A (en) * | 2010-02-04 | 2011-08-10 | 한국생산기술연구원 | Method of separating semiconductor chip from package |
| CN102629604A (en) * | 2012-04-06 | 2012-08-08 | 天水华天科技股份有限公司 | Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package |
| CN105818008A (en) * | 2016-03-23 | 2016-08-03 | 陈志同 | Complex generatrix polishing wheel with local reinforcement structure and manufacturing method thereof |
| CN105789059A (en) * | 2016-04-19 | 2016-07-20 | 浙江中纳晶微电子科技有限公司 | Method for separating bonded wafers |
| CN109946586A (en) * | 2019-02-12 | 2019-06-28 | 长江存储科技有限责任公司 | The detection method of chip electrical connection defect |
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