CN111739840B - Preparation method of silicon adapter plate and packaging structure of silicon adapter plate - Google Patents

Preparation method of silicon adapter plate and packaging structure of silicon adapter plate Download PDF

Info

Publication number
CN111739840B
CN111739840B CN202010727780.5A CN202010727780A CN111739840B CN 111739840 B CN111739840 B CN 111739840B CN 202010727780 A CN202010727780 A CN 202010727780A CN 111739840 B CN111739840 B CN 111739840B
Authority
CN
China
Prior art keywords
semiconductor substrate
tsv
thinning
stop layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010727780.5A
Other languages
Chinese (zh)
Other versions
CN111739840A (en
Inventor
唐昭焕
王学毅
吴罚
张海欧
邓晓国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Center Co Ltd
Original Assignee
United Microelectronics Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Center Co Ltd filed Critical United Microelectronics Center Co Ltd
Priority to CN202010727780.5A priority Critical patent/CN111739840B/en
Publication of CN111739840A publication Critical patent/CN111739840A/en
Application granted granted Critical
Publication of CN111739840B publication Critical patent/CN111739840B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a preparation method of a silicon adapter plate and a packaging structure of the silicon adapter plate, wherein the preparation method of the silicon adapter plate comprises the steps of providing a semiconductor substrate, thinning the back surface of the semiconductor substrate, and arranging TSV (through silicon Via) through holes in the thinned semiconductor substrate. According to the invention, the TSV through holes are formed after the thinning treatment is carried out on the back surface of the semiconductor substrate, so that the problems that in the prior art, due to the difference of TSV pattern densities, the TSV depths are different, the planarization difficulty and the cost are high in all TSV exposure processes and after exposure are solved, and the consistency of the TSV etching depths is realized.

Description

Preparation method of silicon adapter plate and packaging structure of silicon adapter plate
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a preparation method of a silicon adapter plate and a packaging structure of the silicon adapter plate.
Background
Compared with the traditional 2D package, the 2.5 package based on the TSV adapter plate enables a plurality of chips to be directly interconnected on the adapter plate, so that the wiring length is greatly shortened, the signal delay and the signal loss are reduced, the relative bandwidth of the 2.5 package can reach 8-50 times of that of the traditional package, and a solution is provided for replacing a high-cost system chip (SoC) with a low-cost small-size chip system package. The adapter plate is used as an intermediate layer, so that three-dimensional interconnection between the chips and the substrate is realized, and the preparation cost and the power consumption of the system chip are reduced. The packaging form in which a plurality of functional chips are interconnected through a TSV pinboard is more and more concerned by most semiconductor companies and scientific research institutions all over the world.
In the preparation method of the silicon adapter plate in the prior art, a TSV + Cu Damascus RDL technical framework is adopted, a Cu Damascus process is used for making RDL, and a wafer level 3D integration is easy to realize by adopting a wafer bonding technology. However, due to the difference of the pattern density of the TSVs, the difficulty of the planarization process of the exposed head of the back TSV is increased, and if the dielectric backfill planarization is adopted, VIA photoetching/etching needs to be added to achieve interconnection between the RDL and the TSV on the back side, so that the cost is increased.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for manufacturing a silicon interposer and a package structure of the silicon interposer, so as to solve the problems in the prior art that due to differences in pattern density of TSVs, TSV depths are different, and the exposure process of all TSVs on the back surface and planarization after exposure are difficult and costly.
Therefore, the embodiment of the invention provides the following technical scheme:
in a first aspect of the present invention, a method for manufacturing a silicon interposer is provided, including:
providing a semiconductor substrate;
thinning the back of the semiconductor substrate;
and arranging TSV through holes in the thinned semiconductor substrate.
Optionally, the thinning the back surface of the semiconductor substrate includes:
and thinning the back of the semiconductor substrate by using a mechanical thinning machine, mechanical chemical polishing and dry etching technologies.
Optionally, the thinning the back surface of the semiconductor substrate by using a mechanical thinning machine, mechanochemical polishing and dry etching techniques includes:
thinning to a preset value by a mechanical thinning machine; wherein the preset value is 5-20 μm larger than the target value;
thinning by 5-20 μm through mechanochemical polishing or dry etching or the combination of the two technologies.
Optionally, before the thinning process is performed on the back surface of the semiconductor substrate, the preparation method further includes:
depositing a first stop layer on the front surface of the semiconductor substrate; the first stop layer comprises an inorganic material;
the first carrier sheet is bonded to the front side of the semiconductor substrate where the first stop layer is deposited.
Optionally, the first stop layer comprises SiO 2 、Si 3 N 4 One or two media; alternatively, the first stop layer comprises SiO 2 、Si 3 N 4 、SiO 2 Three layers of composite media.
Optionally, after the back surface of the semiconductor substrate is thinned, the preparation method further includes:
depositing a second stop layer on the back of the thinned semiconductor substrate; the second stop layer includes an inorganic material.
Optionally, the second stop layer comprises a medium of at least one of:
SiO 2 、Si 3 N 4 。
optionally, the preparation method further comprises:
arranging a first rewiring layer on the back of the thinned semiconductor substrate;
providing a UBM bottom metal layer on the first rerouting layer;
temporarily bonding a second carrier and the back of the thinned semiconductor substrate;
releasing the first slide;
arranging a second rewiring layer on the front surface of the thinned semiconductor substrate;
arranging salient points on the front side of the thinned semiconductor substrate;
releasing the second slide;
and arranging a solder ball at the opening position of the second stop layer on the back surface of the thinned semiconductor substrate.
In a second aspect of the present invention, a silicon interposer package structure is provided, where the silicon interposer package structure is prepared according to any one of the above-mentioned methods for preparing a silicon interposer in the first aspect.
The technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a preparation method of a silicon adapter plate and a packaging structure of the silicon adapter plate, wherein the preparation method of the silicon adapter plate comprises the steps of providing a semiconductor substrate, thinning the back surface of the semiconductor substrate, and arranging TSV through holes on the thinned semiconductor substrate. According to the embodiment of the invention, the TSV through holes are formed after the thinning treatment is performed on the back surface of the semiconductor substrate, so that the problems that in the prior art, due to the difference of TSV pattern densities, the TSV depths are different, the planarization difficulty is high and the cost is high in all TSV exposure processes on the back surface and after exposure, and the consistency of the TSV etching depths is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a silicon interposer according to an embodiment of the present invention;
FIGS. 2-17 are schematic diagrams of silicon interposer structures according to embodiments of the present invention.
In the figure:
silicon wafer 1
Silicon dioxide (SiO) 2 ) 2
Silicon nitride (Si) 3 N 4 ) 3
Temporary bonding glue 4
Slide 5-1, 5-2
Through Silicon Vias (TSV) 6
Back surface rewiring 7
UBM 8
Front surface rewiring 9
Photoresist 10
Salient point 11
Tin-silver 12
Solder ball 13
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the prior art, after a TSV through hole is formed in a semiconductor substrate through a TSV process, a wafer is thinned to the bottom of the TSV for a certain distance, and then silicon on the back of the wafer is etched away through wet etching (or dry etching), so that a conductive column at the bottom of the TSV is exposed. Therefore, before the wafer is thinned, the TSV figure density difference is large, so that the TSV depth difference is large after TSV through holes are formed, the planarization difficulty is large after all TSV on the back face are exposed, if media are used for backfilling and planarization, a layer of mask of VIA needs to be added, and the cost is increased.
In view of the above problems in the prior art, an embodiment of the present invention provides a method for manufacturing a silicon interposer, as shown in fig. 1, including the following steps:
step S101, providing a semiconductor substrate, wherein the semiconductor substrate can be a semiconductor chip, the material of the semiconductor substrate can be silicon, germanium, gallium nitride, gallium arsenide and other semiconductor materials, and the semiconductor substrate can also be a wafer;
step S102, thinning the back of the semiconductor substrate;
and step S103, arranging TSV on the thinned semiconductor substrate.
Compared with the prior art that the TSV through holes are formed in the semiconductor substrate through the TSV process, the wafer is thinned, so that the TSV depth difference after the TSV through holes are formed is large, the planarization cost is high after all the TSVs expose out of the back surface, the thinning processing is performed on the back surface of the semiconductor substrate firstly through the steps, the TSV pattern density difference is reduced, then the TSV through holes are formed in the semiconductor substrate, the consistency of the TSV etching depth can be achieved, the problems that in the prior art, due to the fact that the TSV pattern density difference is large before the wafer is thinned, the TSV depth difference after the TSV through holes are formed is large, the planarization difficulty is high after all the TSVs expose out of the back surface, if medium backfilling planarization is adopted, a layer of VIA mask needs to be added, the cost is increased, the TTV, BOW, roughess and the like with good thinning surface can be guaranteed, and the method is very suitable for a system integration process based on a Si-Si wafer bonding technology.
The step S102 involves thinning the back surface of the semiconductor substrate, and in an alternative embodiment, the back surface of the semiconductor substrate is thinned by using a mechanical thinning machine, mechanochemical polishing, and dry etching techniques. Specifically, the thickness is reduced to a preset value which is 5 to 20 mu m larger than the target value by a mechanical thinning machine, and the thickness is reduced by 5 to 20 mu m by a mechanical chemical polishing technology. It should be understood by those skilled in the art that the mechanical thinning machine, the mechanical chemical polishing, and the dry etching techniques are not used to limit the present embodiment, and other thinning processing manners adopted according to actual needs are within the protection scope of the present embodiment.
In an alternative embodiment, before the above step S102, a first stop layer is deposited on the front side of the semiconductor substrate, the first stop layer comprising an inorganic material, in particular, the first stop layer comprising SiO 2 、Si 3 N 4 One or two media; alternatively, the first stop layer comprises SiO 2 、Si 3 N 4 、SiO 2 Three layers of composite media. And bonding the first carrier sheet with the front surface of the semiconductor substrate deposited with the first stop layer, specifically, temporarily bonding the first carrier sheet with the front surface of the semiconductor substrate through bonding glue. Specifically, the carrier plate of the first carrier plate can be square or round, the round carrier plate can be made of silicon or glass, and the square carrier plate can be made of glass or a double-sided copper-clad plate.
In an alternative embodiment, after step S102, a second stop layer is deposited on the back side of the thinned semiconductor substrate, and the material of the second stop layer may be one or more inorganic materials, specifically, the second stop layer comprises SiO 2 、Si 3 N 4 Two layers of composite media, or comprising SiO 2 、Si 3 N 4 A medium of (1).
Step S103 above involves forming TSV through holes in the thinned semiconductor substrate, and in an alternative embodiment, deep reactive ion etching is used to etch TSV through holes on a silicon wafer, where the diameter of the TSV through hole may be 25 μm and the aspect ratio is 6, and copper is electroplated in the TSV through hole.
After the step S103, the method further includes the following steps:
and S1, arranging a first rewiring layer on the back surface of the thinned semiconductor substrate, wherein the thickness of the first rewiring layer can be 3-5 microns, and the material can be copper.
And S2, arranging a UBM bottom metal layer on the first rewiring layer.
And S3, bonding the second carrier with the back of the thinned semiconductor substrate, specifically, bonding the second carrier with the back of the silicon substrate through bonding construction, wherein the carrier of the second carrier can be square or circular, the circular carrier can be made of silicon or glass and the like, and the square carrier can be made of glass or a double-sided copper-clad plate and the like.
And S4, releasing the first slide glass.
And S5, arranging a second rewiring layer on the front surface of the silicon substrate, wherein the second rewiring layer can be a high-density wiring layer, namely the line width/line distance is less than 5 mu m, and the dielectric materials between different rewiring layers can be the same or different.
And S6, arranging salient points on the front surface of the silicon substrate, specifically, forming a protective layer on the second re-wiring layer of the silicon substrate, arranging metal micro salient points with tin lugs at the top ends of the openings of the protective layer, and arranging the micro salient points in an array. The bumps are used for connecting a flip chip, and the flip chip is a single bare chip, or a plurality of bare chips, or a single-group multilayer stacked chip assembly, or a plurality of groups of multilayer stacked chip assemblies. A single bare chip is in flip-chip welding on each TSV adapter plate, a plurality of bare chips are in flip-chip welding on each TSV adapter plate respectively, a single group of multilayer stacked chip assemblies are assembled on each TSV adapter plate, and a plurality of groups of multilayer stacked chip assemblies are assembled on each TSV adapter plate respectively. The flip chip is connected and communicated with the adapter plate through a plurality of bumps, the bumps can be various metals or alloys with good conductive performance, the bumps are preferably gold balls or tin balls in the embodiment, and the bumps are coated in the underfill layer between the adapter plate and the flip chip. The underfill layer is made of epoxy resin, phenolic resin, organic silicon resin and unsaturated polyester resin, preferably epoxy resin plastic sealant, and fillers such as silicon oxide and aluminum oxide are added into the underfill resin to improve the strength, electrical property, viscosity and other properties of the encapsulant and improve the thermo-mechanical reliability of the package structure.
And S7, releasing the second slide glass.
And S8, arranging solder balls at the opening positions of the second stop layer on the back surface of the silicon substrate, specifically arranging the solder balls on the back surface of the silicon substrate, wherein the solder balls can be arranged in an array. In an optional embodiment, a first passivation layer, a first seed layer, the first redistribution layer, a second passivation layer, a second seed layer, and a UBM bottom metal layer are sequentially disposed between the back surface of the silicon substrate and the solder balls. The passivation layer material can be PI or PBO, and the seed layer material can be Ti/Cu. And the first seed layer, the first rewiring layer, the second seed layer and the UBM bottom metal layer are interconnected. The flip chip is electrically connected through the second rewiring layer, the TSV through hole, the first rewiring layer, the UBM bottom metal layer and the solder balls.
In an alternative embodiment, the sidewall of the TSV is deposited with an insulating layer, a diffusion barrier layer, a seed layer, and the TSV is filled with copper or tungsten. Specifically, the diffusion barrier layer and the seed layer form a conductive pillar, wherein the diffusion barrier layer may be at least one of Ta, taN, tiw, and the seed layer is at least one of Cu, A1, au, W. The insulating layer is one of silicon oxide, silicon nitride, aluminum oxide, BCB, polyimide (PI), glass, polypropylene (polypropylene), parylene (Poly-p-phenylene), or the like.
The step S6 mentioned above involves providing bumps on the front side of the silicon substrate, and in an alternative embodiment, sputtering a UBM bottom metal layer on the front side of the silicon substrate, providing conductive alloy powder on the UBM bottom metal layer at a position vertically corresponding to the TSV via, and etching or corroding the UBM bottom metal layer except at a position vertically corresponding to the TSV via. Specifically, the conductive alloy powder is tin-silver alloy powder.
The embodiment of the invention also provides a packaging structure of the silicon adapter plate, which is prepared according to the preparation method of any one of the silicon adapter plates in the embodiment.
This is described in detail below in connection with a specific alternative embodiment.
Step 201, as shown in FIG. 2, depositing a layer including but not limited to SiO on the front surface of the silicon wafer 1 2 、Si 3 N 4 、SiO 2 With Si 3 N 4 Composite media, preferably SiO 2 /Si 3 N 4 /SiO 2 Three layers of composite media.
Step 202, as shown in fig. 3, for the first temporary bonding, the slide 5-1 is subjected to a temporary bonding process on the deposition side of the composite dielectric layer.
Step 203, as shown in fig. 4, the whole wafer is thinned, and the wafer is thinned to a target thickness of +5 to 20 μm by using a thinning machine, and then is thinned to 5 to 20 μm by using CMP.
Step 204, as shown in fig. 5, oxide is deposited on the back side of the silicon wafer 1.
Step 205, as shown in fig. 6, the TSV process includes detailed processes such as TSV lithography, TSV etching, photoresist removal, TSV cleaning, insulating layer dielectric deposition, barrier layer metal sputtering, seed layer, metal sputtering, TSV Cu electroplating, and Cu-CMP.
Step 206, as shown in FIG. 7, dielectric deposition, including SiO 2 、SiO 2 With Si 3 N 4 Composite media, preferably SiO 2 /Si 3 N 4 Two layers of composite media.
Step 207, as shown in fig. 8, rewiring is performed on the back surface of the interposer, and the BM1 is prepared by adopting a damascene process.
Step 208, shown in FIG. 9, covers the UBM1 metal.
Step 209, as shown in fig. 10, the 2 nd temporary bonding, the slide 5-2 is subjected to the temporary bonding process on the side of BM1.
Step 2010, shown in FIG. 11, jie Jiange is the first temporarily bonded slide 5-1.
Step 2011, as shown in fig. 12, a damascene process is used to prepare FM1 on one side of the debonding carrier 5-1.
Step 2012, sputtering UBM2, electroplating to form a bump, and etching or etching UBM2, as shown in fig. 13-15.
Step 2013, as shown in fig. 16 and 17, solder balls are prepared on one side of the BM1 by a ball-planting process until the silicon adapter plate process is completed.
It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. In addition, the definitions of the above-mentioned elements and steps are not limited to the specific structures, shapes or manners mentioned in the embodiments, which may be easily changed or replaced by those skilled in the art, and the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., refer to the directions of the drawings only, and do not limit the protection scope of the present invention; the embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e. technical features in different embodiments may be freely combined to form further embodiments.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims (6)

1. A method for preparing a silicon interposer, comprising:
providing a semiconductor substrate;
depositing a first stop layer on the front side of the semiconductor substrate, wherein the first stop layer comprises an inorganic material;
temporarily bonding the first carrier and the front surface of the semiconductor substrate deposited with the first stop layer;
thinning the back surface of the semiconductor substrate;
depositing a second stop layer on the back of the thinned semiconductor substrate, wherein the second stop layer comprises an inorganic material;
arranging TSV through holes in the thinned semiconductor substrate;
arranging a first rewiring layer on the back of the thinned semiconductor substrate;
providing a UBM bottom metal layer on the first rewiring layer;
temporarily bonding a second carrier and the back of the thinned semiconductor substrate;
releasing the first slide;
arranging a second rewiring layer on the front surface of the thinned semiconductor substrate;
arranging salient points on the front side of the thinned semiconductor substrate;
releasing the second slide;
and arranging a solder ball at the opening position of the second stop layer on the back surface of the thinned semiconductor substrate.
2. The method for manufacturing a silicon interposer as claimed in claim 1, wherein the thinning process of the back surface of the semiconductor substrate includes:
and thinning the back of the semiconductor substrate by using a mechanical thinning machine, mechanical chemical polishing and dry etching technologies.
3. The method for preparing a silicon interposer as claimed in claim 2, wherein the thinning of the back surface of the semiconductor substrate by mechanical thinning machine, mechanochemical polishing and dry etching comprises:
thinning to a preset value by a mechanical thinning machine; wherein the preset value is 5-20 μm larger than the target value;
thinning by 5-20 μm through mechanical chemical polishing or dry etching or the combination of the two technologies.
4. The method of manufacturing a silicon interposer as claimed in claim 1,
the first stop layer comprises SiO 2 、Si 3 N 4 One or two media; alternatively, the first and second electrodes may be,
the first stop layer comprises SiO 2 、Si 3 N 4 、SiO 2 Three layers of composite media.
5. The method of manufacturing a silicon interposer as recited in claim 1,
the second stop layer comprises a medium of at least one of:
SiO 2 、Si 3 N 4 。
6. a silicon interposer package structure, wherein the silicon interposer package structure is prepared according to the method of any one of claims 1-5.
CN202010727780.5A 2020-07-24 2020-07-24 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate Active CN111739840B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010727780.5A CN111739840B (en) 2020-07-24 2020-07-24 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010727780.5A CN111739840B (en) 2020-07-24 2020-07-24 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate

Publications (2)

Publication Number Publication Date
CN111739840A CN111739840A (en) 2020-10-02
CN111739840B true CN111739840B (en) 2023-04-11

Family

ID=72657797

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010727780.5A Active CN111739840B (en) 2020-07-24 2020-07-24 Preparation method of silicon adapter plate and packaging structure of silicon adapter plate

Country Status (1)

Country Link
CN (1) CN111739840B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270603A (en) * 2011-08-11 2011-12-07 北京大学 Manufacturing method of silicon through hole interconnect structure
CN105428260A (en) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 Manufacturing method of carrier-based fan-out 2.5D/3D package structure
CN105428340A (en) * 2014-09-11 2016-03-23 株式会社东芝 Semiconductor Device Having Terminals Formed On A Chip Package Including A Plurality Of Semiconductor Chips And Manufacturing Method Thereof
CN110828430A (en) * 2019-11-07 2020-02-21 中芯长电半导体（江阴）有限公司 Packaging structure and preparation method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7326629B2 (en) * 2004-09-10 2008-02-05 Agency For Science, Technology And Research Method of stacking thin substrates by transfer bonding
KR101387701B1 (en) * 2007-08-01 2014-04-23 삼성전자주식회사 Semiconductor packages and methods for manufacturing the same
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8294280B2 (en) * 2009-05-07 2012-10-23 Qualcomm Incorporated Panelized backside processing for thin semiconductors
TWI419302B (en) * 2010-02-11 2013-12-11 Advanced Semiconductor Eng Package process
US8802499B2 (en) * 2012-11-15 2014-08-12 Amkor Technology, Inc. Methods for temporary wafer molding for chip-on-wafer assembly
KR101419601B1 (en) * 2012-11-20 2014-07-16 앰코 테크놀로지 코리아 주식회사 Semiconductor device using epoxy molding compound wafer support system and fabricating method thereof
CN103077885B (en) * 2013-01-31 2016-06-01 上海新傲科技股份有限公司 Controlled thining method and semiconducter substrate
US20190378781A1 (en) * 2018-06-07 2019-12-12 International Business Machines Corporation Enhanced adhesive materials and processes for 3d applications
US20200144314A1 (en) * 2018-11-05 2020-05-07 Varex Imaging Corporation Detector architecture using photodetector substrates and semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102270603A (en) * 2011-08-11 2011-12-07 北京大学 Manufacturing method of silicon through hole interconnect structure
CN105428340A (en) * 2014-09-11 2016-03-23 株式会社东芝 Semiconductor Device Having Terminals Formed On A Chip Package Including A Plurality Of Semiconductor Chips And Manufacturing Method Thereof
CN105428260A (en) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 Manufacturing method of carrier-based fan-out 2.5D/3D package structure
CN110828430A (en) * 2019-11-07 2020-02-21 中芯长电半导体（江阴）有限公司 Packaging structure and preparation method thereof

Also Published As

Publication number Publication date
CN111739840A (en) 2020-10-02

Similar Documents

Publication Publication Date Title
US11830745B2 (en) 3D packages and methods for forming the same
US10854567B2 (en) 3D packages and methods for forming the same
US11854785B2 (en) Package structure for heat dissipation
US10847383B2 (en) Stacked semiconductor devices and methods of forming same
CN107644870B (en) Semiconductor assembly and packaging method
KR102114454B1 (en) Semiconductor device package and method
US8836140B2 (en) Three-dimensional vertically interconnected structure
US8466059B2 (en) Multi-layer interconnect structure for stacked dies
CN111799227B (en) Semiconductor device and method of forming the same
CN110504247A (en) Ic package and forming method thereof
KR101706119B1 (en) Bowl-shaped solder structure
US7687311B1 (en) Method for producing stackable dies
TW201023299A (en) Method of forming stacked dies
KR20230098518A (en) Semiconductor packages and method of manufacture
CN111739840B (en) Preparation method of silicon adapter plate and packaging structure of silicon adapter plate
US20230260941A1 (en) Semiconductor Device and Method
KR102571920B1 (en) Package and method of fabricating the same
US20230420330A1 (en) Semiconductor Packages and Methods of Forming the Same
TW202403984A (en) Semiconductor package
CN116435196A (en) Package and method of forming the same
CN116525558A (en) Package and method of forming the same
CN116682791A (en) Package and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant