CN116682791A

CN116682791A - Package and method of forming the same

Info

Publication number: CN116682791A
Application number: CN202310368818.8A
Authority: CN
Inventors: 吴俊毅; 余振华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-10
Filing date: 2023-04-07
Publication date: 2023-09-01

Abstract

Embodiments of the present application provide a package and a method of forming the same, the package including: a package substrate including an insulating layer having a trench; and a package assembly bonded to the package substrate. The package assembly includes: a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler proximate a first sidewall of the optical die; a dam structure located on the redistribution structure proximate to the first sidewall of the optical die; a first underfill located between the optical die and the redistribution structure; an encapsulant encapsulating the optical die; and an optical adhesive in physical contact with the first side wall of the optical die. The first underfill does not extend along the first side wall of the optical die. The optical cement separates the dam structure from the encapsulant. The package further includes a second underfill between the insulation layer and the package assembly. The second underfill is disposed partially in the trench.

Description

Package and method of forming the same

Technical Field

Embodiments of the present application relate to packages and methods of forming the same.

Background

The semiconductor industry has experienced a rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the iterative decrease in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, there is a need for smaller, more innovative semiconductor die packaging techniques.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a package including: a package substrate including an insulating layer having a trench; and a package assembly bonded to the package substrate adjacent to the trench. The package assembly includes: a redistribution structure; an optical die bonded to the redistribution structure, the optical die including an edge coupler proximate a first sidewall of the optical die; a dam structure located on the redistribution structure proximate to the first sidewall of the optical die; a first underfill located between the optical die and the redistribution structure, the first underfill in physical contact with the dam structure, the first underfill not extending along the first side wall of the optical die; an encapsulant encapsulating the optical die; and an optical adhesive in physical contact with the first sidewall of the optical die, the optical adhesive separating the dam structure from the encapsulant. The package further includes: and a second underfill between the insulating layer of the package substrate and the package assembly, wherein the second underfill is partially disposed in the trench.

According to another aspect of an embodiment of the present application, there is provided a package including: a package substrate including an insulating layer having a trench; a package assembly bonded to the package substrate, a first sidewall of the package assembly being adjacent to the trench; and an optical fiber array unit attached to the first sidewall of the package assembly. Wherein, the encapsulation subassembly includes: a redistribution structure; an optical die bonded to the redistribution structure, the optical die comprising an edge coupler, wherein a first sidewall of the optical die and a first sidewall of the package assembly are proximate the edge coupler; an optical adhesive in physical contact with the first sidewall of the optical chip and located between the edge coupler and the optical fiber array unit; a dam structure located on the redistribution structure adjacent the first sidewall of the optical die, the dam structure being embedded in the optical cement; and a first underfill between the optical chip and the redistribution structure, the first underfill in physical contact with the dam structure and the optical glue, the first underfill not extending between the edge coupler and the optical glue. The package further includes: and a second underfill between the insulating layer of the package substrate and the package assembly, wherein the second underfill partially fills the trench, and wherein the second underfill does not extend between the edge coupler and the optical fiber array unit.

According to yet another aspect of an embodiment of the present application, there is provided a method of forming a package, including: forming a package assembly. Wherein forming the package assembly comprises: forming a redistribution structure; forming a dam structure on the redistribution structure; bonding an optical die to the redistribution structure, the optical die including an edge coupler proximate a first sidewall of the optical die, the first sidewall of the optical die being adjacent to the dam structure; depositing a first underfill in a first gap between the optical die and the redistribution structure, wherein the first underfill is in physical contact with the dam structure, and wherein the first underfill does not extend along the first sidewall of the optical die; forming an optical adhesive over the dam-like structure, wherein the optical adhesive extends along and is in physical contact with the first sidewall of the optical die; and forming a sealant on the optical adhesive, wherein the optical adhesive separates the dam structure from the sealant. The method of forming the package further includes: forming a trench in an uppermost insulating layer of the package substrate; bonding the package assembly to the package substrate with the edge coupler of the optical die adjacent the trench; and depositing a second underfill in a second gap between the package assembly and the package substrate, wherein the second underfill partially fills the trench, and wherein the second underfill does not extend along the first sidewall of the optical die.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die according to some embodiments.

Fig. 2 illustrates a cross-sectional view of an integrated circuit die in accordance with some embodiments.

Fig. 3 illustrates a cross-sectional view of an integrated circuit die in accordance with some embodiments.

Fig. 4-7, 8A, 8B, 9, 10, 11A, and 11B illustrate top and cross-sectional views of intermediate stages in the manufacture of a package assembly according to some embodiments.

Fig. 12A, 12B, and 12C illustrate top and cross-sectional views of a package assembly according to some embodiments.

Fig. 13-16 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly according to some embodiments.

Fig. 17-20 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly according to some embodiments.

Fig. 21 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 22 illustrates a cross-sectional view of a package assembly according to some embodiments.

Fig. 23, 24A, 24B, 24C, 25A, and 25B illustrate top and cross-sectional views of intermediate stages in the manufacture of a package according to some embodiments.

Fig. 26 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 27 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 28A and 28B illustrate cross-sectional views of packages according to some embodiments.

Fig. 29 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 30 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 31 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 32 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 33 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 34 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 35 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 36A and 36B illustrate cross-sectional views of packages according to some embodiments.

Fig. 37 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 38 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 39 illustrates a cross-sectional view of a package according to some embodiments.

Fig. 40 illustrates a cross-sectional view of a package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

Embodiments will be described with respect to embodiments in a particular context, namely integrated circuit packages and methods of forming the same. In various embodiments presented herein, a package includes a package assembly mounted on a package substrate. The package assembly may include an optical integrated circuit die attached to a redistribution structure or interposer. The optical integrated circuit die may include an optical coupler, such as an edge coupler. A dam structure may be formed on the redistribution structure or interposer near an edge of the package assembly such that the dam is proximate to an edge coupler of the optical integrated circuit die. The dam prevents an underfill formed between the package assembly and the redistribution structure or interposer from extending along the sidewalls of the optical integrated circuit die and shielding the edge coupler. An optical glue layer may be formed on the dam and may cover sidewalls of the optical integrated circuit die near the edge coupler. The optical cement layer prevents an encapsulant encapsulating the optical integrated circuit die from extending along sidewalls of the optical integrated circuit die and shielding the edge coupler. The solder resist trench may be formed in a solder resist layer above the package substrate near an edge of the package assembly. The solder resist trench allows an underfill formed between the package assembly and the package substrate to at least partially fill the solder resist trench and prevent the underfill from extending along the sidewalls of the package assembly and from obscuring edge couplers of the optical integrated circuit die disposed proximate the sidewalls of the package assembly. Various embodiments presented herein allow for the integration of optical integrated circuit dies including edge couplers or grating couplers, through which high bandwidth, co-package (co-package) optics with ultra-low power consumption are achieved, and without the need for additional cost to add a dam.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 may be a logic device (e.g., an Application Specific Integrated Circuit (ASIC) die, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a microcontroller, etc.), a memory device (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management device (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a Digital Signal Processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc., or a combination thereof (e.g., a system on chip (SoC) chip). The integrated circuit die 50 may be formed in a wafer that may include different die areas that are singulated in subsequent steps to form a plurality of integrated circuit die 50. The integrated circuit die 50 includes a semiconductor substrate 52, an interconnect structure 54, and conductive connectors 56.

The semiconductor substrate 52 may be a doped or undoped silicon substrate or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. The semiconductor substrate 52 has an active or front surface (e.g., an upwardly facing surface) and a passive or backside surface (e.g., a downwardly facing surface). The devices are located at the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.) and/or passive devices (capacitors, resistors, inductors, etc.). The passive surface may be devoid of devices.

Interconnect structure 54 is over the active surface of semiconductor substrate 52 and is used to electrically connect the devices of semiconductor substrate 52 to form an integrated circuit. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Acceptable dielectric materials for the dielectric layer include low-k dielectric materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Dielectric materials acceptable for the dielectric layer further include: oxides such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; an analog; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and the like. Other dielectric materials, such as polymers, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymers, and the like, may also be used. The metallization layers may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. Interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

Conductive connectors 56 are formed at the front side 50F of the integrated circuit die 50. Conductive connector 56 may include Under Bump Metallization (UBM) 56A and a solder region 56B over UBM 56A. UBM 56A may be a conductive pillar, a pad, or the like. In some embodiments, UBM 56A may be formed by forming a seed layer over interconnect structure 54. The seed layer may be a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed to light to be patterned. The pattern of the photoresist corresponds to UBM 56A. Openings are patterned through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and over the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, nickel, and the like. Then, the photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process. The seed layer and the remaining portion of the conductive material form UBM 56A.

In some embodiments, UBM 56A may include three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as chrome/chrome-copper alloy/copper/gold, titanium/titanium-tungsten/copper, or copper/nickel/gold arrangements, may be used to form UBM 56A. Any suitable material or material layer that may be used for UBM 56A is fully intended to be included within the scope of the present application.

The solder region 56B may include a solder material and may be formed on the UBM 56A by dipping, printing, plating, or the like. The solder material may, for example, include lead-based and lead-free solders, such as Pb-Sn compositions for lead-based solders; lead-free solder containing InSb; tin, silver and copper (SAC) components; and other eutectic materials that have a common melting point and form a conductive solder connection in electrical applications. For lead-free solder, SAC solders of different compositions, such as SAC 105 (Sn 98.5%, ag 1.0%, cu 0.5%), SAC 305, and SAC 405, may be used. The lead-free solder may further include SnCu compound without using silver (Ag). Lead-free solders may also include tin and silver, sn-Ag, without the use of copper. In some embodiments, a reflow process may be performed, in some embodiments to give the solder regions 56B a partially spherical shape. In other embodiments, the solder regions 56B may have other shapes, such as non-spherical.

In some embodiments, the solder regions 56B may be used to perform Chip Probe (CP) testing on the integrated circuit die 50. For example, the solder regions may be solder balls, solder bumps, etc., the solder regions being used to connect the chip probes to the conductive connectors 56. Chip probe testing may be performed on the integrated circuit die 50 to determine if the integrated circuit die 50 is a Known Good Die (KGD). Thus, only the integrated circuit die 50 that is KGD is subjected to subsequent processing and packaged, while the die that fails the chip probe test is not packaged. In some embodiments, after testing, solder regions 56B may be removed in a subsequent processing step.

Fig. 2 illustrates a cross-sectional view of an integrated circuit die 60 in accordance with some embodiments. Integrated circuit die 60 is a stacked device that includes a plurality of semiconductor substrates 52. For example, the integrated circuit die 60 may be a memory device including a plurality of memory dies, such as a Hybrid Memory Cube (HMC) device, a High Bandwidth Memory (HBM) device, or the like. In such an embodiment, the integrated circuit die 60 includes a plurality of semiconductor substrates 52, the plurality of semiconductor substrates 52 being interconnected by through-substrate vias (TSVs), such as through-silicon vias (not shown). Each semiconductor substrate 52 may (or may not) have a separate interconnect structure.

Fig. 3 illustrates a cross-sectional view of an integrated circuit die 70 according to some embodiments. The integrated circuit die 70 may be an optical integrated circuit die, such as an optical engine die. Integrated circuit die 70 may include an Electrical Integrated Circuit (EIC) 70A bonded to a Photonic Integrated Circuit (PIC) 70B. EIC 70A may include a semiconductor substrate 52, active and/or passive electronics on an active side of semiconductor substrate 52, and interconnect structures 54 on an active side of semiconductor substrate 52. EIC 70A may be formed in a similar manner to integrated circuit die 50 described above with reference to fig. 1, and will not be repeated here. PIC 70B may include optics such as waveguides, modulators, and the like. PIC 70B may also include an optical coupler, such as edge coupler 72. In some embodiments, the edge coupler 72 may comprise a dielectric material (such as silicon nitride, etc.) and may be formed using Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), etc. In other embodiments, the edge coupler 72 may include a semiconductor layer (such as a silicon layer, etc.) and may be formed from an SOI substrate. Edge coupler 72 may be disposed within PIC 70B and proximate to a sidewall (or edge) 70E of integrated circuit die 70. As described in more detail below, edge coupler 72 provides optical coupling between integrated circuit die 70 and optical fibers coupled to integrated circuit die 70.

The integrated circuit die 70 may be formed in a wafer, which may include different die areas, which is singulated in subsequent steps to form a plurality of integrated circuit die 70. In some embodiments, the wafer may be formed by hybrid bonding an EIC wafer (including a plurality of EICs 70A) to a PIC wafer (including a plurality of PICs 70B).

Fig. 4-7, 8A, 8B, 9, 10, 11A, and 11B illustrate top and cross-sectional views of intermediate stages in the manufacture of a package assembly 400 according to some embodiments. Fig. 4 to 7, 8A, 8B, 9, 10 and 11A show sectional views, and fig. 11B shows a top view. In particular, fig. 4-7, 8A, 8B, 9, and 10 illustrate the formation of a wafer level package assembly 200 according to some embodiments. In some embodiments, wafer level package assembly 200 includes a plurality of die level regions (e.g., region 200A) corresponding to a die level package assembly (e.g., package assembly 400). The multiple die-level regions of the wafer-level package assembly 200 are singulated to form individual die-level package assemblies 400, as described below with respect to fig. 11A and 11B.

In fig. 4, a carrier wafer 100 is provided or formed. The carrier wafer 100 serves as a platform or support for the packaging process described below. In some embodiments, the carrier wafer 100 comprises a semiconductor material (e.g., silicon, etc.), a dielectric material (e.g., glass, ceramic material, quartz, etc.), combinations thereof, and the like.

In some embodiments, conductive vias 102 are formed on carrier wafer 100. The conductive via 102 may also be referred to as a through-hole, a molded through-hole, or a sealant through-hole. As an example of forming the conductive vias 102, a seed layer (not shown) is formed over the carrier wafer 100. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed to light to be patterned. The pattern of the photoresist corresponds to the conductive via. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The photoresist and portions of the seed layer where the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The seed layer and the remaining portion of the conductive material form a conductive via 102.

In some embodiments, the integrated circuit die 104 are attached to a carrier wafer. The integrated circuit die 104 may be an embedded local interconnect (ehsi) die. Integrated circuit die 104 may have a similar structure to integrated circuit die 50 described above with reference to fig. 1 and will not be repeated here. In some embodiments, the integrated circuit die 104 includes passive electronics and does not include active electronics. In some embodiments, the integrated circuit die 104 includes active and passive electronics.

In some embodiments, the backside 104B of the integrated circuit die 104 is attached to the carrier wafer 100 such that the front side 104F of the integrated circuit die 104 (e.g., the side on which the electronics and conductive interconnects are formed) faces away from the carrier wafer 100. In some embodiments, the integrated circuit die 104 are attached to the carrier wafer 100 using an adhesive 106. The adhesive 106 may be any suitable adhesive, epoxy, die Attach Film (DAF), or the like. The adhesive 106 may be applied to the back side 104B of the integrated circuit die 104 or may be applied over the surface of the carrier wafer 100.

In fig. 5, an encapsulant 108 is formed over and around the integrated circuit die 104 and the conductive vias 102. After formation, the encapsulant 108 encapsulates the integrated circuit die 104 and the conductive vias 102. The encapsulant 108 may be a molding compound, epoxy, or the like. The encapsulant 108 may be applied by compression molding, transfer molding, or the like, and formed over the carrier wafer 100 such that the integrated circuit die 104 and the conductive vias 102 are buried or covered. The sealant 108 may be applied in liquid or semi-liquid form and then subsequently cured. The encapsulant 108 may be thinned to expose the integrated circuit die 104. The thinning process may be an abrasive process, chemical Mechanical Polishing (CMP), etch back, combinations thereof, or the like. After the thinning process, the front side 104F of the integrated circuit die 104, the top surface of the conductive vias 102, and the top surface of the encapsulant 108 are coplanar (within process variations) such that they are flush with one another. Thinning is performed until a desired amount of the integrated circuit die 104, encapsulant 108, and/or conductive vias 102 have been removed.

In fig. 6, a redistribution structure 110 is formed over the integrated circuit die 104, the encapsulant 108, and the conductive vias 102. In the illustrated embodiment, the redistribution structure 110 includes metallization patterns 112 and 116 (sometimes referred to as redistribution layers or redistribution lines) and insulating layers 114 and 118.

Metallization pattern 112 may be formed on integrated circuit die 104, encapsulant 108, and conductive vias 102. As an example of forming metallization pattern 112, a seed layer is formed over integrated circuit die 104, encapsulant 108, and conductive vias 102. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist (not shown) is then formed and patterned over the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light to be patterned. The pattern of photoresist corresponds to metallization pattern 112. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. Then, the photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process, such as by wet etching or dry etching. The seed layer and the remaining portion of the conductive material form metallization pattern 112.

An insulating layer 114 may be formed on the metallization pattern 112. In some embodiments, the insulating layer 114 is formed of a polymer that may be patterned using a photolithographic mask, which may be a photosensitive material such as PBO, polyimide, BCB, or the like. In other embodiments, the insulating layer 114 is formed of nitride such as silicon nitride, oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The insulating layer 114 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. The insulating layer 114 is then patterned to form openings exposing portions of the metallization pattern 112. Patterning may be performed by an acceptable process, such as by exposing the insulating layer 114 to light or by etching using, for example, anisotropic etching when the insulating layer 114 is a photosensitive material. If the insulating layer 114 is a photosensitive material, the insulating layer 114 may be developed after exposure.

A metallization pattern 116 is then formed. The metallization pattern 116 includes conductive elements that extend along a major surface of the insulating layer 114 and extend through the insulating layer 114 to physically and electrically couple to the metallization pattern 112. As an example of forming the metallization pattern 116, a seed layer is formed over the insulating layer 114 and extends through the opening of the insulating layer 114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned over the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light to be patterned. The pattern of photoresist corresponds to metallization pattern 116. Openings are patterned through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and over the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material of the seed layer and the underlying portion forms a metallization pattern 116. The photoresist and portions of the seed layer where no conductive material is formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, by using an acceptable etching process, such as by wet etching or dry etching.

After forming the metallization pattern 116, an insulating layer 118 is formed over the metallization pattern 116 and the insulating layer 114. Insulating layer 118 can be formed using similar materials and methods as insulating layer 114. In the illustrated embodiment, the redistribution structure 110 includes two metallization patterns (such as metallization patterns 112 and 116) and two insulating layers (such as insulating layers 114 and 118). In some embodiments, the redistribution structure 110 may include any number of insulating layers and metallization patterns. The above steps and process may be repeated if more insulating layers and metallization patterns are to be formed.

Further in fig. 6, conductive connectors 120 are formed on the redistribution structure 110 and are in electrical contact with the redistribution structure 110. The conductive connectors 120 may be Ball Grid Array (BGA) connectors, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG) techniques, and the like. The conductive connector 120 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 120 is formed by initially forming a solder layer by evaporation, plating, printing, solder transfer, ball placement, and the like. Once a layer of solder is formed over the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 120 includes metal posts (e.g., copper posts) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

In some embodiments, conductive connector 120 includes UBM 120A and solder region 120B over UBM 120A. UBM 120A may be formed using similar materials and methods as UBM 56A described above with reference to fig. 1, and will not be repeated here. Solder region 120B may be formed using similar materials and methods as solder region 56B described above with reference to fig. 1, and will not be repeated here.

In some embodiments, one or more dam structures 122 are formed over the redistribution structure 110, such as over the insulating layer 118. The dam structure 122 may include a lower portion 122A and an upper portion 122B above the lower portion 122A. In some embodiments, the conductive connector 120 is formed in the same process as the one or more dam structures 122 such that a lower portion 122A of the dam structure 122 is formed in the same process as the UBM 120A and an upper portion 122B of the dam structure 122 is formed in the same process as the solder region 120B. In such an embodiment, the lower portion 122A of the dam structure 122 and the UBM 120A comprise the same material, and the upper portion 122B of the dam structure 122 and the solder region 120B comprise the same material. In some embodiments, the lower portion 122A of the dam structure 122 and the UBM 120A have the same width. In other embodiments, the lower portion 122A of the dam structure 122 and the UBM 120A have different widths. In some embodiments, the dam structure 122 and the conductive connector 120 have the same height. In other embodiments, the dam structure 122 has a different height than the conductive connector 120. The dam structure 122 has a height H1 and a width W1. The height H1 may be between about 5 μm and about 80 μm. The width W1 may be between about 20 μm and about 1.0 mm. The ratio of the height H1 to the width W1 (H1/W1) may be between about 0.1 and about 1.5.

In some embodiments, one or more of the dam structures 122 may be electrical dummy structures or electrical non-dummy structures. In such an embodiment, one or more of the dam structures 122 may be electrically isolated from the conductive connector 120 and the metallization patterns 112 and 116 of the redistribution structure 110 by the insulating layers 114 and 118 of the redistribution structure 110.

In fig. 7, integrated circuit dies 50, 60, and 70 are attached to redistribution structure 110. In the illustrated cross-sectional view, each die-level region (e.g., region 200A shown in fig. 9) of wafer-level package assembly 200 (see fig. 9) includes two integrated circuit dies 50, a single integrated circuit die 60, and a single integrated circuit die 70. A first one of the integrated circuit dies 50 may be a logic device such as an Application Specific Integrated Circuit (ASIC) die, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), a microcontroller, or the like. The second of the integrated circuit dies 50 may be memory devices such as Dynamic Random Access Memory (DRAM) dies, static Random Access Memory (SRAM) dies, and the like. In some embodiments, the integrated circuit die 50 may be the same type of die, such as a SoC die, an ASIC die, or the like. Although a single integrated circuit die 60 and a single integrated circuit die 70 are shown in the cross-sectional view of fig. 7, there may be multiple integrated circuit dies 60 and multiple single integrated circuit dies 70 in each die level area (e.g., area 200A shown in fig. 9) of the wafer level package assembly 200 (see fig. 9) shown in fig. 11B as an example.

In some embodiments, integrated circuit dies 50, 60, and 70 are attached to redistribution structure 110 using conductive connectors 56 (see fig. 1-3) and 120 (see fig. 6). Integrated circuit dies 50, 60, and 70 may be placed on redistribution structure 110 using, for example, a pick-and-place tool. After the integrated circuit dies 50, 60, and 70 are placed on the redistribution structure 110, the solder areas 56B of the conductive connectors 56 (see fig. 1-3) are in physical contact with the corresponding solder areas 120B of the corresponding conductive connectors 120 (see fig. 6). After the integrated circuit dies 50, 60, and 70 are placed on the redistribution structure 110, a reflow process is performed on the conductive connectors 56 and 120 (see fig. 1-3 and 6). The reflow process melts and merges solder regions 56B and 120B into solder joint 124. Solder joints 124 electrically and mechanically couple the integrated circuit dies 50, 60, and 70 to the redistribution structure 110.

Further in fig. 7, an underfill 126 may be formed around the solder joints 124 and in the gaps between the redistribution structure 110 and the integrated circuit dies 50, 60, and 70. The gap may have a height H2 of between about 5 μm and 55 μm. The height H2 of the gap may be greater than the height H1 of the dam structure 122 (see fig. 6). The ratio of height H1 to height H2 (H1/H2) may be between about 0.1 and about 0.95. The underfill 126 may reduce stress and protect the solder joints 124. The underfill 126 may be formed of an underfill material such as a molding compound, epoxy, or the like. The underfill 126 may be formed by a capillary flow process after the integrated circuit dies 50, 60, and 70 are attached to the redistribution structure 110, or may be formed by a suitable deposition method before the integrated circuit dies 50, 60, and 70 are attached to the redistribution structure 110. The underfill 126 may be applied in liquid or semi-liquid form and then cured. In some embodiments, the underfill 126 partially or completely fills the gaps between adjacent integrated circuit dies 50, 60, and 70 such that the underfill 126 extends along the sidewalls of the integrated circuit dies 50, 60, and 70. In some embodiments, dam structure 122 prevents underfill 126 from physically contacting and extending along sidewalls 70E of integrated circuit die 70. In such an embodiment, the dam structure 122 is in physical contact with the underfill 126. Thus, the underfill 126 does not shield the edge coupler 72 of the integrated circuit die 70.

Fig. 8A and 8B illustrate the structure of fig. 7 after formation of the optical cement 128, according to some embodiments. Fig. 8A shows a cross-sectional view, and fig. 8B shows an enlarged view of region 130 of fig. 8A. In some embodiments, the optical cement 128 includes a polymeric material, such as an epoxy acrylate oligomer. The polymeric material may have a refractive index between about 1 and about 3. In some embodiments, optical adhesive 128 is formed over redistribution structure 110 proximate to sidewalls 70E of integrated circuit die 70 such that optical adhesive 128 covers dam structure 122. The optical cement 128 is in physical contact with the dam structure 122 and the underfill 126. In addition, optical adhesive 128 extends along sidewalls 70E of integrated circuit die 70 and is in physical contact with sidewalls 70E. The optical cement 128 may have a height H3 of between about 6 μm and about 787 μm. In some embodiments, the height H3 of the optical adhesive 128 is less than the height of the integrated circuit die 70.

In fig. 9, an encapsulant 132 is formed over and around the integrated circuit die 50, 60, and 70. After formation, encapsulant 132 encapsulates integrated circuit die 50, 60, and 70, underfill 126, and optical cement 128. The optical cement 128 prevents the encapsulant 132 from shielding the edge coupler 72 of the integrated circuit die 70. The encapsulant 132 may be a molding compound, epoxy, or the like. The filler may not be included in the encapsulant 132. The encapsulant 132 may be applied by compression molding, transfer molding, or the like, and formed over the carrier wafer 100 such that the integrated circuit dies 50, 60, and 70 are buried or covered. The sealant 132 may be applied in liquid or semi-liquid form and then cured. Encapsulant 132 may be thinned to expose integrated circuit die 50, 60, and 70. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. After the thinning process, the top surfaces of the integrated circuit dies 50, 60, and 70 and the top surface of the encapsulant 132 are coplanar (within process variations) such that they are flush with one another. Thinning is performed until a desired amount of the integrated circuit die 50, 60, and 70 and/or encapsulant 132 has been removed. In some embodiments, the sealants 108 and 132 include the same material. In some embodiments, the sealants 108 and 132 include different materials. The index of refraction of encapsulant 132 may be between about 1.5 and about 3.0. In some embodiments, the difference between the refractive index of the optical cement 128 and the refractive index of the encapsulant 132 is between about 0.2 and about 0.3.

In fig. 10, carrier wafer 100 is detached from wafer level package assembly 200 (see fig. 9), such that carrier wafer 100 is detached from encapsulant 108 and integrated circuit die 104. In some embodiments, the release process may also remove the adhesive 106 from the integrated circuit die 104. Subsequently, the wafer level package assembly 200 is flipped over and attached to the carrier wafer 300. Carrier wafer 300 may be formed using similar materials and methods as carrier wafer 100 described with reference to fig. 4 and will not be repeated here. In some embodiments, the wafer level package assembly 200 is attached to the carrier wafer 300 using an adhesive (not shown).

After the wafer level package assembly 200 is attached to the carrier wafer 300, conductive connectors 134 are formed over the integrated circuit die 104 and the encapsulant 108. Conductive connectors 134 are electrically coupled to conductive vias 102 and/or integrated circuit die 104. The conductive connectors 134 may be Ball Grid Array (BGA) connectors, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG) techniques, or the like. The conductive connector 134 may be formed using similar materials and methods as the conductive connector 120 described above with reference to fig. 6, and will not be repeated here. In the illustrated embodiment, the conductive connector 134 includes a UBM 134A and a solder region 134B over the UBM 134A. UBM 134A and solder region 134B may be formed using similar materials and methods as UBM 120A and solder region 120B, respectively, described above with reference to fig. 6, and will not be repeated here.

Further, the singulation process is performed on the wafer level package assembly 200 by performing dicing along scribe line regions, for example, around the region 200A. Singulation processes may include sawing, etching, cutting, combinations thereof, and the like. For example, the singulation process may include sawing the encapsulants 108 and 132, the redistribution structure 110, and the optical cement 128. The singulation process singulation of the regions 200A from adjacent regions to form singulated package assemblies 400 shown in fig. 11A and 11B. Individual package assemblies 400 come from area 200A.

Fig. 11A and 11B illustrate top and cross-sectional views of a package assembly 400 according to some embodiments. Specifically, fig. 11A shows a sectional view and fig. 11B shows a top view. Furthermore, not all of the components of package assembly 400 are shown in the top view of fig. 11B for clarity. As a result of the singulation process described above with reference to fig. 10, the outer sidewalls of the encapsulants 108 and 132, the outer sidewalls of the redistribution structure 110, and the outer sidewalls of the optical adhesive 128 are laterally co-terminal (within process variations), as shown in fig. 11A. After the singulation process, the encapsulant 132 has a thickness T1 on the sidewalls 70E of the integrated circuit die 70. The thickness T1 may be between about 5mm to about 10 mm. In some embodiments, the dam structure 122 has a rectangular shape in plan view, as shown in fig. 11B. In other embodiments, the dam structure 122 may have any desired shape in plan view based on the design requirements of the package assembly 400. In the illustrated embodiment, the dam structure 122 overlaps the respective integrated circuit die 70 such that the sidewall 122L of the dam structure 122 is covered by the respective integrated circuit die 70 and the sidewall 122R (opposite the sidewall 122L) of the dam structure 122 is uncovered by the respective integrated circuit die 70, as shown in fig. 11B.

Fig. 12A, 12B, and 12C illustrate top and cross-sectional views of a package assembly 400' according to some embodiments. Specifically, fig. 12A shows a cross-sectional view, fig. 12B shows an enlarged view of the region 136 of fig. 12A, and fig. 12C shows a top view. Furthermore, not all of the components of the package assembly 400' are shown in the top view of fig. 12C for clarity. The package assembly 400' is similar to the package assembly 400, like parts are labeled with like reference numerals, and description of like parts is not repeated here. The package assembly 400' may be formed using process steps similar to those described above with reference to fig. 4-7, 8A, 8B, 9, 10, 11A, and 11B, and will not be repeated herein. The dam structure 122 of the package assembly 400' is formed such that the dam structure 122 does not overlap the corresponding integrated circuit die 70 in plan view, as shown in fig. 12C. In the illustrated embodiment, the sidewalls 122L of the dam structures 122 are vertically aligned with the sidewalls 70E of the respective integrated circuit die 70. Thus, as shown in the top view of fig. 12C, the sidewalls 122L of the dam structures 122 are shown as being collinear with the sidewalls 70E of the respective integrated circuit die 70. As shown in fig. 12C, sidewalls 122R (opposite sidewalls 122L) of dam structures 122 are not covered by the corresponding integrated circuit die 70.

Fig. 13-16 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly 600 according to some embodiments. Fig. 13-15 illustrate the formation of a wafer level package assembly 500 according to some embodiments. In some embodiments, wafer level package assembly 500 includes a plurality of die level regions (such as region 500A) corresponding to a die level package assembly (such as package assembly 600). The multiple die-level regions of the wafer-level package assembly 500 are singulated to form individual die-level package assemblies 600, as described below in fig. 16. The process steps described below with reference to fig. 13-16 are similar to the process steps described above with reference to fig. 4-7, 8A, 8B, 9, 10, 11A, and 11B, and similar processes and structures will not be repeated. Unlike the package assembly 400 (see fig. 11A and 11B), the package assembly 600 includes one or more dam structures 502 instead of one or more dam structures 122 (see fig. 11A and 11B).

In fig. 13, a carrier wafer 100 is provided or formed. The carrier wafer 100 serves as a platform or support for the packaging process described below. In some embodiments, the carrier wafer 100 comprises a semiconductor material (such as silicon, etc.), a dielectric material (such as glass, ceramic material, quartz, etc.), combinations thereof, and the like.

In some embodiments, the conductive vias 102 are formed on the carrier wafer 100 as described above with reference to fig. 4, and the description is not repeated here. Subsequently, the integrated circuit die 104 are attached to the carrier wafer 100, as described above with reference to fig. 4, which is not repeated here. The integrated circuit die 104 may be an embedded local interconnect (ehsi) die.

In some embodiments, an encapsulant 108 is formed over and around the integrated circuit die 104 and the conductive vias 102, as described above with reference to fig. 5, which is not repeated here. Encapsulant 108 may be thinned to expose integrated circuit die 50. The thinning process may be a grinding process, CMP, etch back, combinations thereof, or the like. After the thinning process, the front side 104F of the integrated circuit die 104, the top surface of the conductive via 102, and the top surface of the encapsulant 108 are coplanar (within process variations) such that they are flush with one another. Thinning is performed until a desired amount of the integrated circuit die 104, encapsulant 108, and/or conductive vias 102 have been removed.

After the encapsulant 108 is formed, a redistribution structure 110 is formed over the integrated circuit die 104, the encapsulant 108, and the conductive vias 102, as described above with reference to fig. 6, and will not be repeated here. Subsequently, the conductive connector 120 is formed on the redistribution structure 110 and is in electrical contact with the redistribution structure 110, as described above with reference to fig. 6, and will not be repeated here.

In fig. 14, after forming the conductive connector 120, one or more dam structures 502 are formed on the redistribution structure 110. Dam structure 502 may include a metallic material, an underfill material, a polymer material, a dielectric material, etc., and may be formed using a suitable deposition process. In some embodiments, dam structure 502 has a rectangular shape in plan view. In other embodiments, dam structure 502 may have any desired shape in plan view, depending on the design requirements of package assembly 600. In the illustrated embodiment, dam structure 502 is formed after conductive connector 120 is formed. In other embodiments, dam structure 502 may be formed prior to forming conductive connector 120.

In fig. 15, the process steps described above with reference to fig. 7, 8A, 8B, 9 and 10 are performed on the structure of fig. 14 to form a wafer level package assembly 500. In some embodiments, dam structure 502 prevents underfill 126 from physically contacting and extending along sidewalls 70E of integrated circuit die 70. In such an embodiment, dam structure 502 is in physical contact with underfill 126. Thus, the underfill 126 does not shield the edge coupler 72 of the integrated circuit die 70. In the illustrated embodiment, dam structure 502 overlaps integrated circuit die 70 (similar to dam structure 122 shown in fig. 11A and 11B) such that a first sidewall of dam structure 502 is covered by integrated circuit die 70 and a second sidewall (opposite the first sidewall) of dam structure 502 is uncovered by integrated circuit die 70. In other embodiments, dam structure 502 does not overlap integrated circuit die 70 (similar to dam structure 122 shown in fig. 12A-12C) such that a first sidewall of dam structure 502 is vertically aligned with a sidewall of integrated circuit die 70 (opposite the first sidewall) and a second sidewall of dam structure 502 is not covered by integrated circuit die 70.

Further, a singulation process is performed on the wafer level package assembly 500 by dicing along scribe line regions (e.g., around the region 500A). Singulation processes may include sawing, etching, cutting, combinations thereof, and the like. For example, the singulation process may include sawing the encapsulants 108 and 132, the redistribution structure 110, and the optical cement 128. The singulation process singulation of the regions 500A from adjacent regions to form singulated package 600 as shown in fig. 16. Individual package assemblies 600 come from region 500A.

Fig. 17-20 illustrate cross-sectional views at intermediate stages in the manufacture of a package assembly 800 according to some embodiments. The package assembly 800 may be a chip on wafer (CoW) package assembly. In fig. 17, an interposer wafer 700 is obtained or formed. Interposer wafer 700 includes a plurality of package regions, such as package region 700A. Interposer wafer 700 includes interposer 702 in a package region (such as package region 700A) that is singulated in subsequent processing for inclusion in package assembly 800. In some embodiments, interposer 702 includes substrate 704, interconnect structure 706, and conductive vias 708.

Substrate 704 may be formed using similar materials and methods as semiconductor substrate 52 described above with reference to fig. 1, and will not be repeated here. In some embodiments, active devices are not typically included in the substrate 704, although the interposer 702 may include passive devices formed in and/or on an active or front surface (e.g., the surface facing upward in fig. 17) of the substrate 704. In other embodiments, active devices such as transistors, capacitors, resistors, diodes, etc. may be formed in and/or on the front surface of the substrate 704.

Interconnect structures 706 are formed over the front surface of substrate 704 and are used to electrically connect devices (if any) of substrate 704. Interconnect structure 706 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Interconnect structure 706 may be formed using similar materials and methods as interconnect structure 54 described above with reference to fig. 1, and will not be repeated here. In some embodiments, the conductive connector 120 and the one or more dam structures 122 are formed at the front side 700FS of the interposer wafer 700, as described above with reference to fig. 6, and will not be repeated here.

Conductive vias 708 extend into the interconnect structure 706 and/or the substrate 704. The conductive vias 708 are electrically connected to the metallization layer of the interconnect structure 706. The conductive vias 708 are sometimes also referred to as Through Substrate Vias (TSVs). As an example of forming the conductive vias 708, grooves may be formed in the interconnect structure 706 and/or the substrate 704 by, for example, etching, milling, laser techniques, combinations thereof, and/or the like. A thin dielectric material may be formed in the recess, for example by using an oxidation technique. The thin barrier layer may be conformally deposited in the opening, such as by CVD, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), thermal oxidation, combinations thereof, and/or the like. The barrier layer may be formed of an oxide, nitride, carbide, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and/or the like. Excess conductive material and barrier layer are removed from the surface of interconnect structure 706 or substrate 704 by, for example, CMP. The barrier layer and the remaining portion of the conductive material form a conductive via 708.

In fig. 18, the process steps described above with reference to fig. 7, 8A, 8B and 9 are performed on the structure of fig. 17 to form a wafer level package assembly. In some embodiments, dam structure 122 prevents underfill 126 from physically contacting and extending along sidewalls 70E of integrated circuit die 70. Thus, the underfill 126 does not shield the edge coupler 72 of the integrated circuit die 70.

In fig. 19, the wafer level package assembly of fig. 17 is flipped over and attached to a carrier wafer 710. The carrier wafer 710 may be formed using similar materials and methods as the carrier wafer 100 described above with reference to fig. 4, and will not be repeated here. In some embodiments, the wafer level package components are attached to the carrier wafer 710 using an adhesive (not shown).

In some embodiments, the substrate 704 is thinned to expose the conductive vias 708. The exposure of the conductive vias 708 may be accomplished by a thinning process, such as a grinding process, CMP, etch back, combinations thereof, and the like. In some embodiments (not separately shown), the thinning process for exposing the conductive vias 708 includes CMP, and the conductive vias 708 protrude at the backside 700BS of the wafer 700 due to dishing that occurs during CMP. In such an embodiment, an insulating layer (not separately shown) may optionally be formed on the backside of the substrate 704 surrounding the protruding portions of the conductive vias 708. The insulating layer may be formed of a silicon-containing insulator such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method such as spin coating, CVD, plasma Enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or the like. After thinning the substrate 704, the conductive vias 708 and the insulating layer (if present) or exposed surface of the substrate 704 are coplanar (within process variations) such that they are flush with each other and exposed at the backside 700BS of the via wafer 700. Subsequently, as described above with reference to fig. 10, the conductive connectors 134 are formed on the backside 700BS of the interposer wafer 700, and the description will not be repeated here.

Further, the singulation process is performed by dicing along the scribe line region (e.g., around the package region 700A). Singulation processes may include sawing, etching, cutting, combinations thereof, and the like. For example, the singulation process may include sawing the encapsulant 132, the optical paste 128, the interconnect structures 706, and the substrate 704. The singulation process singulates the package region 700A from adjacent package regions to form singulated package assemblies 800, as shown in fig. 20. The individual package assemblies 800 come from the package area 700A. Singulation forms interposer 702 from singulated portions of interposer wafer 700. As a result of the singulation process, the outer sidewalls of the interposer 702, encapsulant 132, and optical cement 128 are laterally co-terminal (within process variations), as shown in fig. 20. In the illustrated embodiment, the dam structures 122 of the package assembly 800 overlap the respective integrated circuit die 70 in plan view, as described above with reference to fig. 11A and 11B, and will not be repeated herein.

Fig. 21 illustrates a cross-sectional view of a package assembly 800' according to some embodiments. The package assembly 800' is similar to the package assembly 800 (see fig. 20), like parts are labeled with like reference numerals, and description of like parts is not repeated here. In some embodiments, the package assembly 800' may be formed using process steps similar to those described above with reference to fig. 17-20, and will not be repeated herein. In the illustrated embodiment, the dam structures 122 of the package assembly 800' do not overlap the corresponding integrated circuit die 70 in plan view, as described above with reference to fig. 12A-12C, and are not repeated herein.

Fig. 22 illustrates a cross-sectional view of a package assembly 900 according to some embodiments. The package assembly 900 is similar to the package assembly 800 (see fig. 20), like parts are labeled with like reference numerals, and description of like parts is not repeated here. Unlike package assembly 800 (see fig. 20), package assembly 900 includes one or more dam structures 502 instead of one or more dam structures 122. In some embodiments, the package assembly 900 may be formed using process steps similar to those described above with reference to fig. 17-20, wherein one or more dam structures 502, instead of one or more dam structures 122, as described above with reference to fig. 14, are formed.

Fig. 23, 24A, 24B, 24C, 25A, and 25B illustrate top and cross-sectional views of intermediate stages in the manufacture of a package 1100 according to some embodiments. In particular, fig. 23, 24A and 25A show cross-sectional views, fig. 24B shows a top view, fig. 24C shows an enlarged view of region 1034 of fig. 24B, and fig. 25B shows an enlarged view of region 1052 of fig. 25A.

In fig. 23, a package assembly 400' is placed on a package substrate 1000. Package substrate 1000 includes a substrate core 1002, where substrate core 1002 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, it may be formed using a compound material such as silicon germanium, silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like. In addition, the substrate core 1002 may be an SOI substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In another embodiment, the substrate core 1002 is an insulating core, such as a fiberglass reinforced resin core. One example core material is fiberglass resin, such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or other Printed Circuit Board (PCB) materials or films.

In some embodiments, substrate core 1002 may include active and passive devices (not separately shown). Devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to generate the structural and functional requirements of the system design. Any suitable method may be used to form the device. In some embodiments, substrate core 1002 is substantially free of active and passive devices. In some embodiments, the substrate core 1002 also includes conductive vias 1004, which may also be referred to as TSVs. In some embodiments, conductive vias 1004 may be formed using similar materials and methods as conductive vias 708 described above with reference to fig. 17, and will not be repeated here.

The package substrate 1000 may also include a redistribution structure. In some embodiments, the redistribution structure may be formed from alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the layers of conductive material, and may be formed by any suitable process (such as deposition, damascene, etc.). In other embodiments, the redistribution structure may be formed from alternating layers of dielectric material (e.g., a laminate film such as a flavourant laminate film (ABF) or other laminate film) and conductive material (e.g., copper), wherein vias interconnect the layers of conductive material and may be formed by any suitable process (e.g., lamination, plating, etc.).

In the illustrated embodiment, package substrate 1000 includes redistribution structures 1006 and 1008 formed on opposite surfaces of substrate core 1002 such that substrate core 1002 is interposed between redistribution structures 1006 and 1008. Conductive vias 1004 electrically couple the redistribution structure 1006 to the redistribution structure 1008. In some embodiments, either the redistribution structure 1006 or the redistribution structure 1008 may be omitted.

In some embodiments, bond pad 1010 and solder mask 1012 are formed on redistribution structure 1006, bond pad 1010 being exposed through an opening formed in solder mask 1012. The bond pads 1010 may be part of the redistribution structure 1006 and may be formed with other conductive components of the redistribution structure 1006. The solder mask 1012 may include a suitable insulating material (such as a dielectric material, a polymer material, etc.) and may be formed using any suitable deposition method.

In some embodiments, the conductive connector 1014 extends through an opening in the solder mask 1012 and contacts the bond pad 1010. The conductive connectors 1014 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. The conductive connector 1014 may be formed using similar materials and methods as the conductive connector 120 described above with reference to fig. 6, and will not be repeated here. In the illustrated embodiment, the conductive connectors 1014 include solder balls.

In some embodiments, bond pads 1016 and solder mask 1018 are formed on the redistribution structure 1008, the bond pads 1016 being exposed through openings formed in the solder mask 1018. The bond pads 1016 may be part of the redistribution structure 1008 and may be formed with other conductive features of the redistribution structure 1008. The solder mask 1018 may include a suitable insulating material (e.g., dielectric material, polymeric material, etc.) and may be formed using any suitable deposition method.

In some embodiments, the conductive connector 1020 extends through an opening in the solder mask 1018 and contacts the bond pad 1016. Conductive connector 1020 may be a Ball Grid Array (BGA) connector, solder ball, metal post, controlled collapse chip connection (C4) bump, micro bump, bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. Conductive connector 1020 may be formed using similar materials and methods as conductive connector 120 described above with reference to fig. 6 and will not be repeated here. In the illustrated embodiment, the conductive connector 1020 includes solder balls.

In some embodiments, the solder mask 1012 is patterned to form one or more trenches 1022 in the solder mask 1012. The patterning process may include suitable photolithography and etching methods. Suitable etching methods may include dry etching or wet etching. The etching process may be anisotropic. In some embodiments, the trenches 1022 extend through the solder mask 1012 and expose conductive features of the redistribution structure 1006. In other embodiments, the trenches 1022 extend partially into the solder mask 1012 and do not expose the conductive features of the redistribution structure 1006.

In some embodiments, the package assembly 400' may be placed on the package substrate 1000 using, for example, a pick-and-place tool. After the package assembly 400' is placed on the package substrate 1000, the conductive connectors 134 are in physical contact with the corresponding conductive connectors 1014 such that the solder regions 134B of the conductive connectors 134 are in physical contact with the corresponding conductive connectors 1014.

In fig. 24A-24C, after the package assembly 400 'is placed on the package substrate 1000, a reflow process is performed to mechanically and electrically connect the package assembly 400' to the package substrate 1000. The reflow process melts and fuses the solder regions 134B of the conductive connector 134 (see fig. 23) and the corresponding solder material of the conductive connector 1014 (see fig. 23) into solder joints 1024. Solder connections 1024 electrically and mechanically couple the package assembly 400' to the package substrate 1000.

In some embodiments, an underfill 1026 may be formed around the solder joints 1024 and in the gap between the package assembly 400' and the package substrate 1000. The underfill 1026 may be formed using materials and methods similar to those described above with reference to fig. 7, and will not be repeated here. In some embodiments, the underfill 1026 extends into the trench 1022 and at least partially fills the trench 1022. The grooves 1022 prevent the underfill 1026 from extending along the sidewalls 400R of the package assembly 400' proximate the edge coupler 72 of the integrated circuit package 70. Thus, the edge coupler 72 of the integrated circuit package 70 is not shielded by the underfill 1026. In some embodiments, underfill 1026 extends along sidewalls 400L of package assembly 400' and physically contacts sidewalls 400L, wherein sidewalls 400L are opposite sidewalls 400R.

In some embodiments, the warp control structure 1030 is attached to the package substrate 1000. The warp control structure 1030 may be attached to the package substrate 1000 by an adhesive 1028 such that the adhesive 1028 is interposed between the warp control structure 1030 and the solder mask 1012. Adhesive 1028 may be any suitable adhesive, epoxy, or the like. The warp control structure 1030 may be a ring-shaped structure (see fig. 24B) and may include holes 1032. The package assembly 400' may be disposed in the aperture 1032 of the warp control structure 1030. The warp control structure 1030 may comprise a metal, a metal alloy, a dielectric material, a semiconductor material, or the like.

Referring to fig. 24B and 24C, in the illustrated embodiment, each trench 1022 has a first sidewall 1022L vertically aligned with a sidewall 400R of the package assembly 400 'and a second sidewall 1022R laterally spaced from the sidewall 400R of the package assembly 400' (opposite the first sidewall 1022L). In other embodiments, the grooves 1022 may partially or completely overlap the package assembly 400' in plan view.

In some embodiments, the center of the edge coupler 72, the center of the corresponding dam structure 122, and the center of the corresponding trench 1022 are aligned along the same line (shown by dashed line 1036 in fig. 24C). The edges of dam structures 122 are spaced apart from lines 1036 by a distance D1 along a direction parallel to sidewalls 70E of respective integrated circuit die 70. The distance D1 may be between about 100 μm and about 5.0 mm. Dam structure 122 has a first width W1 measured along a first direction perpendicular to sidewalls 70E of the respective integrated circuit die 70 and a second width W2 measured along a second direction parallel to sidewalls 70E of the respective integrated circuit die 70. The width W2 is 2 times the distance D1. The width W1 is between about 20 μm and about 1.0 mm. The width W2 is between about 200 μm and about 10.0 mm.

The edges of the trenches 1022 are spaced apart from the lines 1036 by a distance D2 along a direction parallel to the sidewalls 70E of the respective integrated circuit die 70. The distance D2 may be between about 100 μm and about 5.0 mm. The trenches 1022 have a first width W3 measured along a first direction perpendicular to the sidewalls 70E of the respective integrated circuit die 70 and a second width W4 measured along a second direction parallel to the sidewalls 70E of the respective integrated circuit die 70. The width W4 is 2 times the distance D2. The width W3 is between about 20 μm and about 1.0 mm. The width W4 is between about 200 μm and about 10.0 mm.

In fig. 25A and 25B, the optical fiber array unit 1042 is connected to the package assembly 400'. The fiber array unit 1042 provides an interface between the edge coupler 72 of the integrated circuit die 70 and the optical fibers 1050 attached to the fiber array unit 1042. In some embodiments, the support structure 1040 is attached to the solder resist layer 1012 of the package substrate 1000 using an adhesive 1038 prior to attaching the fiber array unit 1042 to the package assembly 400'. Support structure 1040 may include semiconductor materials (e.g., silicon), dielectric materials, combinations thereof, and the like. Adhesive 1038 may be formed using similar materials and methods as adhesive 1028.

The fiber array unit 1042 may be attached to the top surface of the package assembly 400' using an adhesive 1044 such that the adhesive 1044 is in physical contact with the top surface of the integrated circuit die 70 and the top surface of the integrated circuit die. The fiber array unit 1042 may be attached to the top surface of the support structure 1040 using an adhesive 1046. The optical fiber array unit 1042 may also be attached to the sidewall 400R of the package assembly 400' using an optical adhesive 1048 such that the optical adhesive 1048 is in physical contact with the sidewall of the optical adhesive 128 and formed between the optical adhesive 128 and the optical fiber array unit 1042. Adhesives 1044 and 1046 may be formed using similar materials and methods as adhesive 1028. The optical cement 1048 may be formed using similar materials and methods as the optical cement 128.

In the illustrated embodiment, optical cement 128 and 1048 is interposed between edge coupler 72 of integrated circuit die 70 and fiber array unit 1042. By forming the dam structure 122, the optical glue 128 and the trench 1022 as described above, no material for the underfill materials 126 and 1026 and the encapsulant 132 is formed between the edge coupler 72 of the integrated circuit die 70 and the fiber array unit 1042. Thus, the edge coupler 72 of the integrated circuit die 70 and the fiber array unit 1042 are not shielded by the materials of the underfills 126 and 1026 and the encapsulant 132.

Fig. 26 illustrates a cross-sectional view of a package 1200 according to some embodiments. Package 1200 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and descriptions of like components are not repeated here. The package 1200 may be formed using the process steps described above with reference to fig. 23, 24A, 24B, 24C, 25A, and 25B, except that the package assembly 400 (see fig. 11A and 11B) is attached to the package substrate 1000 instead of the package assembly 400' (see fig. 25A and 25B).

Fig. 27 illustrates a cross-sectional view of a package 1300 according to some embodiments. Package 1300 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and a description of like components is not repeated here. Package 1300 may be formed using the process steps described above with reference to fig. 23, 24A, 24B, 24C, 25A, and 25B, except that package assembly 600 (see fig. 16) is attached to package substrate 1000 instead of package assembly 400' (see fig. 25A and 25B).

Fig. 28A and 28B illustrate cross-sectional views of a package 1400 according to some embodiments. Fig. 28B shows an enlarged view of region 1054 of fig. 28A. Package 1400 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and a description of like components is not repeated here. The package 1400 may be formed using the process steps described above with reference to fig. 23, 24A, 24B, 24C, 25A and 25B, and the description is not repeated here. In the illustrated embodiment, the underfill 1026 extends along the sidewalls 400R of the package assembly 400' (e.g., the sidewalls of the encapsulant 108 and the redistribution structure 110) and does not extend along the sidewalls of the optical glue 128.

Fig. 29 illustrates a cross-sectional view of a package 1500 according to some embodiments. Package 1500 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and a description of like components is not repeated here. The package 1500 may be formed using the process steps described above with reference to fig. 23, 24A, 24B, 24C, 25A, and 25B, except that the package assembly 800 '(see fig. 21) is attached to the package substrate 1000 instead of the package assembly 400' (see fig. 25A and 25B).

Fig. 30 illustrates a cross-sectional view of a package 1600 according to some embodiments. Package 1600 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and a description of like components is not repeated here. Package 1600 may be formed using the process steps described above with reference to fig. 23, 24A, 24B, 24C, 25A, and 25B, except that package assembly 800 (see fig. 20) is attached to package substrate 1000 instead of package assembly 400' (see fig. 25A and 25B).

Fig. 31 illustrates a cross-sectional view of a package 1700 according to some embodiments. Package 1700 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and a description of like components is not repeated here. The package 1700 may be formed using the process steps described above with reference to fig. 23, 24A, 24B, 24C, 25A, and 25B, except that the package assembly 900 (see fig. 22) is attached to the package substrate 1000 instead of the package assembly 400' (see fig. 25A and 25B).

Fig. 32 illustrates a cross-sectional view of a package 1800 according to some embodiments. Package 1800 is similar to package 1500 (see fig. 29), like parts are labeled with like reference numerals, and a description of like parts will not be repeated here. Package 1800 may be formed in a similar manner to package 1500 and will not be repeated here. In the illustrated embodiment, the underfill 1026 extends along the sidewalls 800R of the package assembly 800' (such as the sidewalls of the interposer 702) and does not extend along the sidewalls of the optical cement 128.

Fig. 33 illustrates a cross-sectional view of a package 1900 according to some embodiments. Package 1900 is similar to package 1100 (see fig. 25A and 25B), like components are labeled with like reference numerals, and descriptions of like components are not repeated here. Package 1900 may be formed in a similar manner to package 1100, except that heat dissipating cover 1060 is attached to package substrate 1000 instead of warp control structure 1030 (see fig. 25A and 25B). In some embodiments, the heat dissipating cover 1060 includes a highly thermally conductive material, such as a metal, metal alloy, or the like. The heat spreading cover 1060 may be attached to the solder mask 1012 by an adhesive 1056. Adhesive 1056 may be formed using similar materials and methods as adhesive 1038. In some embodiments, a thermal interface material 1058 is interposed between the top surface of the package assembly 400' and the heat sink lid 1060. The thermal interface material 1058 may include a thermal interface material having a high thermal conductivity. In some embodiments, the heat dissipating cover 1060 includes an opening 1062 exposing the optical fiber array unit 1042. In such an embodiment, the optical fibers 1050 extend into the opening 1062 and attach to the fiber array unit 1042.

Fig. 34 illustrates a cross-sectional view of a package 2000, according to some embodiments. Package 2000 is similar to package 1200 (see fig. 26), like parts being labeled with like reference numerals, and a description of like parts will not be repeated here. The package 2000 may be formed in a similar manner to the package 1200, except that the heat dissipating cover 1060 is attached to the package substrate 1000 instead of the warp control structure 1030 (see fig. 26). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Fig. 35 illustrates a cross-sectional view of a package 2100 according to some embodiments. Package 2100 is similar to package 1300 (see fig. 27), like components being labeled with like reference numerals, and a description of like components will not be repeated here. Package 2100 may be formed in a similar manner to package 1300, except that heat dissipating cover 1060 is attached to package substrate 1000 instead of warp control structure 1030 (see fig. 27). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Fig. 36A and 36B illustrate cross-sectional views of a package 2200 according to some embodiments. Fig. 36B shows an enlarged view of region 1064 of fig. 36A. The package 2200 is similar to the package 1400 (see fig. 28A and 28B), like parts are labeled with like reference numerals, and a description of like parts is not repeated here. The package 2200 may be formed in a similar manner to the package 1400, except that the heat dissipating cover 1060 is attached to the package substrate 1000 instead of the warp control structure 1030 (see fig. 28A and 28B). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Fig. 37 illustrates a cross-sectional view of a package 2300 according to some embodiments. The package 2300 is similar to the package 1500 (see fig. 29), like parts are labeled with like reference numerals, and a description of like parts will not be repeated here. The package 2300 may be formed in a similar manner to the package 1500, except that the heat dissipating cover 1060 is attached to the package substrate 1000 instead of the warp control structure 1030 (see fig. 29). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Fig. 38 illustrates a cross-sectional view of a package 2400 in accordance with some embodiments. Package 2400 is similar to package 1600 (see fig. 30), like components being labeled with like reference numerals, and a description of like components will not be repeated here. The package 2400 may be formed in a similar manner as the package 1600, except that the heat dissipating cover 1060 is attached to the package substrate 1000 instead of the warp control structure 1030 (see fig. 30). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Fig. 39 illustrates a cross-sectional view of a package 2500 in accordance with some embodiments. Package 2500 is similar to package 1700 (see fig. 31), like components being labeled with like reference numerals, and the description of like components will not be repeated here. Package 2500 may be formed in a similar manner to package 1700, except that heat sink cap 1060 is attached to package substrate 1000 instead of warp control structure 1030 (see fig. 31). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Fig. 40 illustrates a cross-sectional view of a package 2600 according to some embodiments. Package 2600 is similar to package 1800 (see fig. 32), like parts being labeled with like reference numerals, and a description of like parts will not be repeated here. Package 2600 may be formed in a similar manner as package 1800, except that heat sink cap 1060 is attached to package substrate 1000 instead of warp control structure 1030 (see fig. 32). In some embodiments, the heat dissipating cover 1060 is attached to the package substrate 1000 as described above with reference to fig. 33, and the description is not repeated here.

Embodiments may take advantage of this. By forming a package (e.g., package 1100 shown in fig. 25A and 25B) including a dam structure (e.g., such as dam structure 122 shown in fig. 25A and 25B), an optical paste (e.g., such as optical paste 128 shown in fig. 25A and 25B), and a solder resist trench (e.g., trench 1022 shown in fig. 25A and 25B), various advantages as described above can be achieved. The dam prevents the underfill formed between the package assembly (e.g., such as package assembly 400' shown in fig. 25A and 25B) and the redistribution structure or interposer (e.g., redistribution structure 110 shown in fig. 25A and 25B) from extending along the sidewalls of the optical integrated circuit die (e.g., integrated circuit die 70 shown in fig. 25A and 25B) and from shielding the edge coupler (e.g., edge coupler 72 shown in fig. 25A and 25B) of the optical integrated circuit die. The optical cement prevents an encapsulant (e.g., encapsulant 132 shown in fig. 25A and 25B) that encapsulates the optical integrated circuit die from extending along the sidewalls of the optical integrated circuit die and from shielding the edge coupler. The solder resist trench allows an underfill (e.g., underfill 1026 shown in fig. 25A and 25B) formed between the package assembly and the package substrate (e.g., package substrate 1000 shown in fig. 25A) to at least partially fill the solder resist trench and prevent the underfill from extending along the sidewalls of the package assembly and from shielding edge couplers of the optical integrated circuit die disposed adjacent the sidewalls of the package assembly. Thus, improved coupling between the edge coupler of the optical integrated circuit die and the fiber array unit (e.g., fiber array unit 1042 shown in fig. 25A and 25B) is achieved. The various embodiments presented herein allow for the integration of optical integrated circuit dies including edge couplers or grating couplers, through which high bandwidth and ultra low power consumption are achieved, wide integration of co-packaged optics is achieved, and additional costs of adding a dam structure are not required.

According to one embodiment, a package includes: a package substrate including an insulating layer having a trench; and a package assembly bonded to the package substrate adjacent to the trench. The package assembly includes: a redistribution structure; an optical die bonded to the redistribution structure, the optical die including an edge coupler proximate a first sidewall of the optical die; a dam structure located on the redistribution structure proximate to the first sidewall of the optical die; a first underfill between the optical die and the redistribution structure; an encapsulant encapsulating the optical die; and an optical adhesive in physical contact with the first side wall of the optical die. The first underfill is in physical contact with the dam structure. The first underfill does not extend along the first side wall of the optical die. The optical cement separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer of the package substrate and the package assembly. The second underfill is disposed partially in the trench. In one embodiment, the package further comprises a fiber array unit coupled to the optical die, wherein the optical glue is interposed between the edge coupler and the fiber array unit. In one embodiment, the package further comprises an optical fiber attached to the optical fiber array unit. In one embodiment, the dam structure partially overlaps the optical chip in plan view. In one embodiment, the first sidewall of the optical die is vertically aligned with the first sidewall of the dam structure. In one embodiment, the trench partially overlaps the optical die in plan view. In one embodiment, the center of the edge coupler, the center of the dam structure, and the center of the trench are aligned along the same line in plan view.

According to another embodiment, a package includes: a package substrate including an insulating layer having a trench; a package assembly bonded to the package substrate, a first sidewall of the package assembly being adjacent to the trench; and an optical fiber array unit attached to the first sidewall of the package assembly. The package assembly includes: a redistribution structure and an optical die bonded to the redistribution structure. The optical die includes an edge coupler. The first side wall of the optical die and the first side wall of the package assembly are proximate the edge coupler. The package assembly further includes: an optical adhesive in physical contact with the first sidewall of the optical chip and located between the edge coupler and the optical fiber array unit; a dam structure located on the redistribution structure adjacent the first sidewall of the optical die; and a first underfill between the optical chip and the redistribution structure. The dam structure is embedded in the optical cement. The first underfill is in physical contact with the dam structure and the optical cement. The first underfill does not extend between the edge coupler and the optical cement. The package also includes a second underfill between the insulating layer of the package substrate and the package assembly. The second underfill partially fills the trench. The second underfill does not extend between the edge coupler and the fiber array unit. In one embodiment, the package further comprises a support structure located on the package substrate adjacent to the first side wall of the package assembly, wherein the fiber array unit is attached to the support structure. In one embodiment, the package assembly further comprises an encapsulant over the redistribution structure, wherein the optical die and the optical glue are embedded in the encapsulant, and the encapsulant does not extend between the edge coupler and the optical glue. In one embodiment, the encapsulant does not extend between the edge coupler and the fiber array unit. In one embodiment, the package further comprises a heat-dissipating cover attached to the package substrate and covering the package assembly, wherein the heat-dissipating cover comprises an opening exposing the optical fiber array unit. In one embodiment, the package further includes optical fibers located within the opening in the heat dissipating cover and attached to the optical fiber array unit. In one embodiment, the first sidewall of the package assembly is vertically aligned with the first sidewall of the trench.

According to yet another embodiment, a method includes forming a package assembly. Forming the package assembly includes forming a redistribution structure. A dam structure is formed over the redistribution structure. The optical die is bonded to the redistribution structure. The optical die includes an edge coupler proximate the first sidewall of the optical die. The first sidewall of the optical die is adjacent to the dam structure. A first underfill is deposited in a first gap between the optical die and the redistribution structure. The first underfill is in physical contact with the dam structure. The first underfill does not extend along the first side wall of the optical die. An optical cement is formed over the dam structure. The optical cement extends along and is in physical contact with the first side wall of the optical die. A sealant is formed on the optical cement. The optical cement separates the dam structure from the sealant. The method further includes forming a trench in an uppermost insulating layer of the package substrate. The package assembly is bonded to a package substrate. The edge coupler of the optical die is adjacent to the trench. A second underfill is deposited in a second gap between the package assembly and the package substrate. The second underfill partially fills the trench. The second underfill does not extend along the first sidewall of the optical die. In one embodiment, the method further comprises attaching the fiber array unit to the first side wall of the optical die, wherein no portion of the first underfill, no portion of the second underfill, and no portion of the encapsulant extend between the edge coupler and the fiber array unit. In one embodiment, the method further comprises, prior to attaching the fiber array unit to the first side wall of the optical die, attaching a support structure to an uppermost insulating layer of the package substrate adjacent to the first side wall of the optical die, wherein the fiber array unit is attached to the support structure. In one embodiment, the method further comprises attaching a heat spreading cover to the package substrate, the heat spreading cover covering the package assembly, wherein the heat spreading cover comprises an opening exposing the fiber array unit. In one embodiment, the method further comprises attaching an optical fiber to the optical fiber array unit, wherein the optical fiber is disposed in the opening of the heat dissipating cover. In one embodiment, the method further comprises forming a plurality of conductive connectors on the redistribution structure prior to bonding the optical die to the redistribution structure, wherein the plurality of conductive connectors and the dam structure are formed in the same process.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package, comprising:

a package substrate including an insulating layer having a trench;

a package assembly bonded to the package substrate adjacent the trench, the package assembly comprising:

a redistribution structure;

an optical die bonded to the redistribution structure, the optical die including an edge coupler proximate a first sidewall of the optical die;

a dam structure located on the redistribution structure proximate to the first sidewall of the optical die;

a first underfill located between the optical die and the redistribution structure, the first underfill in physical contact with the dam structure, the first underfill not extending along the first sidewall of the optical die;

An encapsulant encapsulating the optical die; and

an optical adhesive in physical contact with the first sidewall of the optical die, the optical adhesive separating the dam structure from the encapsulant; and

and a second underfill between the insulating layer of the package substrate and the package assembly, wherein the second underfill is partially disposed in the trench.

2. The package of claim 1, further comprising a fiber array unit coupled to the optical die, wherein the optical glue is interposed between the edge coupler and the fiber array unit.

3. The package of claim 2, further comprising an optical fiber attached to the optical fiber array unit.

4. The package of claim 1, wherein the dam structure partially overlaps the optical die in plan view.

5. The package of claim 1, wherein the first sidewall of the optical die is vertically aligned with a first sidewall of the dam structure.

6. The package of claim 1, wherein the trench partially overlaps the optical die in plan view.

7. The package of claim 1, wherein a center of the edge coupler, a center of the dam structure, and a center of the trench are aligned along a same line in plan view.

8. A package, comprising:

a package substrate including an insulating layer having a trench;

a package assembly bonded to the package substrate, a first sidewall of the package assembly being proximate the trench;

a fiber array unit attached to the first sidewall of the package assembly, wherein the package assembly includes:

a redistribution structure;

an optical die bonded to the redistribution structure, the optical die comprising an edge coupler, wherein a first sidewall of the optical die and the first sidewall of the package assembly are proximate the edge coupler;

an optical adhesive in physical contact with the first sidewall of the optical chip and located between the edge coupler and the optical fiber array unit;

a dam structure located on the redistribution structure adjacent to the first sidewall of the optical die, the dam structure being embedded in the optical adhesive; and

a first underfill located between the optical chip and the redistribution structure, the first underfill in physical contact with the dam structure and the optical glue, the first underfill not extending between the edge coupler and the optical glue; and

A second underfill between the insulating layer of the package substrate and the package assembly, wherein the second underfill partially fills the trench, and wherein the second underfill does not extend between the edge coupler and the fiber array unit.

9. The package of claim 8, further comprising a support structure on the package substrate adjacent to the first sidewall of the package assembly, wherein the fiber array unit is attached to the support structure.

10. A method of forming a package, comprising:

forming a package assembly, wherein forming the package assembly comprises:

forming a redistribution structure;

forming a dam structure over the redistribution structure;

bonding an optical die to the redistribution structure, the optical die including an edge coupler proximate a first sidewall of the optical die, the first sidewall of the optical die being adjacent to the dam structure;

depositing a first underfill in a first gap between the optical die and the redistribution structure, wherein the first underfill is in physical contact with the dam structure, and wherein the first underfill does not extend along the first sidewall of the optical die;

Forming an optical paste over the dam structure, wherein the optical paste extends along and is in physical contact with the first sidewall of the optical die; and

forming a sealant above the optical adhesive, wherein the optical adhesive separates the dam structure from the sealant;

forming a trench in an uppermost insulating layer of the package substrate;

bonding the package assembly to the package substrate, the edge coupler of the optical die adjacent the trench; and

depositing a second underfill in a second gap between the package assembly and the package substrate, wherein the second underfill partially fills the trench, and wherein the second underfill does not extend along the first sidewall of the optical die.