CN111737638A - Data processing method based on Fourier transform and related device - Google Patents
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Abstract
The application provides a data processing method and a related device based on Fourier transform, firstly, calculating a storage address displacement value of input data under each address offset through an address manager; then, writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data; then, simultaneously reading the storage data from the first memory through an operation module to perform butterfly computation to obtain operation data, and storing the operation data in a second memory; and finally, reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to process the operation data, so as to obtain output data. The method can prevent the storage address conflict when the butterfly operation reads data, greatly improve the speed of the butterfly operation, and obviously improve the modulation and demodulation efficiency of the 5G signal.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data processing method based on fourier transform and a related apparatus.
Background
In the fourth generation mobile communication technology (4G), Orthogonal Frequency Division Multiplexing (OFDM) is used, so that a module for managing Fast Fourier Transform (FFT), Inverse Fast Fourier Transform (IFFT), and Discrete Fourier Transform (DFT) becomes an indispensable functional module regardless of a transmitting end or a receiving end, which is one of key modules on a modulation and demodulation link.
A global 5G standard designed based on a New Radio (NR) of OFDM, that is, the 5GNR system continues to use the OFDM modulation technique, but compared with a Long Term Evolution (LTE) system in the 4G era, the throughput of the 5G NR system data is greatly improved, so that the requirement on the processing capability of the FFT/IFFT/DFT module is also correspondingly improved. In an LTE system, the maximum bandwidth of a single carrier signal is 20MHz, the interval of subcarriers is 15KHz, and 2048-point FFT and 1200-point DFT are required to be supported on each carrier; in the 5G NR system, the maximum bandwidth of a single carrier signal is 400MHz, the subcarrier interval is 120KHz, and each carrier needs to support 4096-point FFT and 3240-point DFT. The data processing speed of the current FFT/DFT module is very limited.
Disclosure of Invention
Based on the above problems, the present application provides a data processing method based on fourier transform and a related device, which can solve the address conflict problem of butterfly operation, and greatly improve the efficiency of 5G signal modulation and demodulation.
In a first aspect, an embodiment of the present application provides a data processing method based on fourier transform, where the method includes:
calculating a storage address displacement value of the input data under each address offset through an address manager;
writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data;
simultaneously reading the storage data from the first memory through an operation module, performing butterfly computation to obtain operation data, and storing the operation data in a second memory;
and reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to process the operation data to obtain output data.
In a second aspect, an embodiment of the present application provides a data processing apparatus based on fourier transform, the apparatus including:
an address calculation unit for calculating a storage address displacement value of the input data at each address offset amount by the address manager;
the storage writing unit is used for writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data;
the storage reading unit is used for simultaneously reading the storage data from the first storage through an operation module to perform butterfly calculation to obtain operation data and storing the operation data in a second storage;
and the output processing unit is used for reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to process the operation data to obtain output data.
In a third aspect, an embodiment of the present application provides an electronic device, comprising an application processor, a memory, and one or more programs, stored in the memory and configured to be executed by the application processor, the program comprising instructions for performing the steps of the method according to any one of claims 1 to 7.
In a fourth aspect, embodiments of the present application provide a computer storage medium storing a computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method according to any one of the first aspect of the embodiments of the present application.
In a fifth aspect, the present application provides a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in any one of the methods of the first aspect of the embodiments of the present application. The computer program product may be a software installation package.
It can be seen that, in the data processing method and the related device based on the fourier transform, firstly, the address manager calculates the storage address displacement value of the input data under each address offset; then, writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data; then, simultaneously reading the storage data from the first memory through an operation module to perform butterfly computation to obtain operation data, and storing the operation data in a second memory; and finally, reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to process the operation data, so as to obtain output data. The method can prevent the storage address conflict when the butterfly operation reads data, greatly improve the speed of the butterfly operation, and obviously improve the modulation and demodulation efficiency of the 5G signal.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1A is a schematic diagram illustrating an architecture of a conventional data processing method according to an embodiment of the present application;
fig. 1B is a schematic diagram of another conventional data processing method according to an embodiment of the present application;
fig. 2 is a system architecture diagram of a data processing method based on fourier transform according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of a data processing method based on fourier transform according to an embodiment of the present application;
FIG. 5A is a diagram illustrating a power-of-2 parallel butterfly operation according to an embodiment of the present disclosure;
FIG. 5B is a diagram illustrating a non-power-of-2 parallel butterfly operation according to an embodiment of the present disclosure;
fig. 6 is a block diagram illustrating functional units of a data processing apparatus based on fourier transform according to an embodiment of the present disclosure;
fig. 7 is a block diagram illustrating functional units of another data processing apparatus based on fourier transform according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
For ease of understanding, the background and related terms related to the embodiments of the present application are first explained.
In the field of communications, Discrete Fourier Transform (DFT) is a general term for an efficient and Fast calculation method for calculating DFT while Fast Fourier Transform (FFT) is a general term for a Discrete Fourier Transform (DFT) that can convert a signal from the time domain to the frequency domain, and an IFFT (inverse Fourier Transform) calculation method is a method that is not essentially different from the FFT calculation method, and only converts a signal from the frequency domain to the time domain, and a butterfly operation related to the Fourier Transform will be described below.
Butterfly operation, 2-point DFT operation may be called butterfly operation, and the whole FFT consists of several levels of iterative butterfly operation, as shown in fig. 1A, fig. 1A is a system architecture diagram of the existing data processing method provided by the embodiment of the present application, including a plurality of butterfly operation units and a plurality of storage units, where the butterfly operation unit can only process butterfly operation whose radix number is a power of 2, and may be called as a pipeline architecture based on data stream; as shown in fig. 1B, fig. 1B is a system architecture diagram of another existing data processing method provided in this embodiment of the present application, which also includes a plurality of butterfly operation units and a plurality of storage units, but in this architecture based on storage units, a large-scale FFT is decomposed into a plurality of stages of small-scale butterfly operation units, and one or more butterfly operation units are used for iterative operation, so as to perform repeated "read-butterfly operation-write" on a storage unit to implement a plurality of stages of iterations, thereby completing the processing of the entire FFT.
The pipeline-based architecture of FIG. 1A described above has the advantage of sufficiently high data throughput, but has the disadvantage of large area with more FFT points and larger delay. If multiple carriers share the same assembly line for FFT processing, when the number of FFT points needed by data of each carrier is different, the efficiency of the carrier is also obviously reduced, and the processing that sub-carriers with different FFT points share the same assembly line FFT module is not common. The storage-based architecture of fig. 1B has the advantages of reducing latency and improving processing efficiency, but cannot achieve simultaneous reading or writing of multiple data stored in different storage areas of the storage unit, which is required by the butterfly unit, i.e., cannot solve the problem of address collision when the storage unit reads and writes multiple data.
Based on the foregoing background, embodiments of the present application provide a data processing method and related apparatus based on fourier transform, which can implement high-speed operation and satisfy operations of all DFT (including FFT, DFT operations in the following description include FFT) lengths required by a 5G LTE/NR system.
Referring to fig. 2, a system architecture of a data processing method based on fourier transform according to an embodiment of the present application is described below, where the system architecture 200 includes an address manager 210, an operation module 220, a first memory 231, and a second memory 232. The address manager 210 is connected to the operation module 220, the first memory 231, and the second memory 232, and is configured to control a storage address when input data is written into the first memory 231 and the second memory 232, the operation module 220 is connected to the first memory 231 and the second memory 232 through the address manager 210, and is configured to perform a butterfly operation, and a data flow is indicated by a serial number in the figure.
The address manager 210 may be a memory manager, and the specific functions include calculating a memory address of the input data in the first memory 231 and a read address of the output data in the second memory 232, and writes the input data into the first memory 231 and the second memory 232 at the storage addresses corresponding to the storage address displacement values, and outputs the output data in the order corresponding to the read addresses, it is understood that the address manager 210 serves as an intermediate module between the operation unit 220 and the first and second memories 231 and 232, for controlling how input data is written into the first memory 231, how the operation module 220 reads input data from the first memory 231, how the operated operation data is written into the second memory 232 again, and how output data is output from the second memory 232 in a predetermined arrangement.
Wherein, the operation module 220 may be a conventional time-domain interpolation butterfly operation unit, including a radix-16 butterfly operation unit or a radix-8 butterfly operation unit, etc., the embodiment of the present application is exemplified by the radix-16 butterfly operation unit, the radix-16 butterfly operation unit not only can perform the butterfly operation of radix-16, but also can connect a register of each node to a memory, and has the capability of simultaneously performing the butterfly operations of two radix-8, four radix-4 and eight radix-2, and in addition, the function of simultaneously calculating the butterfly operations of three radix-5 and five radix-3 can be realized by changing the connection mode between the nodes of the operation module 220, wherein the butterfly operation of one radix-16, the butterfly operation of two radix-8, the butterfly operation of four radix-4 and the butterfly operation of eight radix-2 are used for FFT calculation, the three radix-5 butterflies and the five radix-3 butterflies described above may be used for the calculation of the DFT.
The first memory 231 and the second memory 232 are adapted to the arithmetic module 220, and when the arithmetic module 220 is a radix-16 butterfly arithmetic unit, the first memory 231 and the second memory 232 may be two single-port memories having 16 banks (hereinafter, all of which are denoted by banks), or may be integrated into one double-port memory module, and the single-port memory and the double-port memory are different in that the single-port memory has only one set of data lines and address lines, and thus, reading and writing cannot be performed simultaneously; and the double ports have two groups of data lines and address lines, and the reading and writing can be carried out simultaneously. The memory with 16 banks can read or write 16I/Q signal data at most simultaneously, the butterfly operation of the radix 16 also needs 16I/Q signal data for calculation, and meanwhile, the butterfly operation of the radix 8, the butterfly operation of the radix 4, the butterfly operation of the radix 2, the butterfly operation of the radix 5 and the butterfly operation of the radix 3 can be regarded as subsets of the butterfly operation of the radix 16, so that the memory with 16 banks can meet the requirements of all butterfly operations. It should be noted that, in the embodiment of the present application, the first memory 231 only represents a memory for storing input data, and the second memory 232 only represents a memory for storing operation data of the operation module, and these two memories may alternately perform different operations to implement synchronous storage of operation data when storing input data, so as to improve operation efficiency.
It can be understood that, the memory address in the embodiment of the present application is optimized and adjusted, which is different from the conventional memory address, so that the operation unit 220 can simultaneously read a large amount of input data from the first memory 231 for calculation, and write the calculated operation data into the second memory 232 according to the memory address during reading, thereby preventing the memory address collision during reading data by the butterfly operation, greatly increasing the speed of the butterfly operation, and significantly improving the efficiency of 5G signal modulation and demodulation.
An electronic device in the embodiment of the present application is described below with reference to fig. 3, fig. 3 is a schematic structural diagram of an electronic device provided in the embodiment of the present application, and the exemplary electronic device 300 may be a device with communication capability, and the device may include various handheld devices with wireless communication function, vehicle-mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem, and various forms of User Equipment (UE), a Mobile Station (MS), a terminal device (terminal device), and the like. The electronic device 300 in the present application may include one or more of the following components: a processor 310, a memory 320, and an input-output device 330.
A memory may be provided in the processor 310 for storing instructions and data. In some embodiments, the memory in the processor 310 is a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 310. If the processor 310 needs to reuse the instruction or data, it can be called directly from the memory. Avoiding repeated accesses, reducing the latency of the processor 310 and increasing system efficiency. The processor 310 may include one or more interfaces, such as an integrated circuit (I2C) interface, an integrated circuit built-in audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a Subscriber Identity Module (SIM) interface, and/or a Universal Serial Bus (USB) interface, etc. It is understood that the processor 110 may be mapped to a System on a Chip (SOC) in an actual product, and the processing unit and/or the interface may not be integrated into the processor 110, and the corresponding functions may be implemented by a communication Chip or an electronic component alone. The above-described interface connection relationship between the modules is merely illustrative, and does not constitute a unique limitation on the structure of the electronic device 300.
The Memory 320 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 320 includes a non-transitory computer-readable medium. The memory 320 may be used to store instructions, programs, code sets, or instruction sets. The memory 320 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a signal modulation function, a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like, and the operating system may be an Android (Android) system (including a system based on Android system depth development), an IOS system developed by apple, including a system based on IOS system depth development), or other systems. The storage data area can also store data created by the electronic device in use, such as butterfly operation data and the like.
The input and output device 330 may include a touch display screen for receiving a touch operation of a user on or near the touch display screen using a finger, a touch pen, or any other suitable object, and displaying a user interface of each application.
A data processing method based on fourier transform in the embodiment of the present application is described below with reference to fig. 4, where fig. 4 is a schematic flow chart of the data processing method based on fourier transform provided in the embodiment of the present application, and specifically includes the following steps:
in step 401, a storage address displacement value of the input data at each address offset is calculated by the address manager.
The address manager may refer to a description of a system architecture, which is not described herein again, where the input data is a series of data point values, such as 1024 data point values and 2048 data point values, required by a fourier transform in a signal processing process of a 5g lte/NR system, the address Offset is a distance between an actual address of a storage unit and a segment address of a segment where the storage unit is located, in brief, if a storage address is regarded as a table of N rows and M columns, N, M is a positive integer, each unit in the table corresponds to a storage address, an address Offset of a first row is 0, an address Offset of a second row is 1, and so on, an address Offset of an nth row is N-1, the M list represents M banks, when the storage address displacement value is 0, the storage address is written in a conventional order for storage, and when the storage address displacement value is 1, the conventional sequential written address corresponding to the row is sequentially cyclically displaced to the right One unit, and so on, is illustrated with 16 banks, i.e. 16 columns, in the present embodiment for ease of understanding.
Specifically, the corresponding butterfly operation number and the base number of each stage of butterfly operation may be determined according to the sequence length of the input data, and then the storage address displacement value of the input data at each address offset may be determined according to the base number of each stage of butterfly operation and the address offset, where the sequence length of the input data is exemplified by the following table one:
table one
It should be noted that the input data with the sequence length 2916 is only one point requiring the seven-stage butterfly operation, and the seventh-stage butterfly operation is the radix-3 butterfly operation, and accordingly, the table is omitted to save space, and it is understood that 4096, 2048, 1024, 512, 256, and 128 are all powers of 2, and are the sequence length of the input data required for FFT, and are the sequence length of the input data required for DFT in addition.
As can be seen from the above table, the radix number is 1, which indicates that there is no butterfly operation of this stage, for example, the radix number R0 of the first stage butterfly operation of 4096 sequence lengths is 16, the radix number R1 of the second stage butterfly operation is 16, the radix number R2 of the third stage butterfly operation is 16, the radix number R3 of the fourth stage butterfly operation, the radix number R4 of the fifth stage butterfly operation, and the radix number of the subsequent butterfly operations are all 1, it can be seen that the butterfly operation stage number corresponding to 4096 is three, the first stage butterfly operation, the second stage butterfly operation, and the third stage butterfly operation are all butterfly operations of the radix number 16, 16 × 16 is 4096, and so on, the stage number of the butterfly operation corresponding to each sequence length and the radix number of each stage of the butterfly operation can be determined, which is not listed here. The above table is merely exemplary and does not represent a limitation on the length of the sequence.
After the radix numbers R0, R1, R2, R2, R3, R4, R5, R6 of each level of butterfly operation are determined, a storage address displacement value of input data at each address offset amount, which is a variable with respect to a normal storage address, may be determined according to a preset formula as shown in the following pseudo code:
m is an arbitrary integer, nocirrularshift means that address displacement is not required, bankshift means a storage address displacement value, mod function is a remainder function, mod (a, b) means the remainder of dividing a by b, i means the address offset, and in conclusion, the above formula means: when the radix R1 of the second-stage butterfly operation is a preset value, determining that the displacement value of the storage address of the input data under each address offset is 0, wherein the preset value is not a value of power of 2, and storing according to the traditional storage address; when the radix R2 of the third-stage butterfly operation is not the power of 2, the first displacement formula is used
Determining the displacement value of the storage address; otherwise, according to the second displacement formula
The memory address displacement value is determined. The value calculated by the above formula needs to be rounded as the memory address displacement value.
For ease of understanding, the following table two shows a conventional memory address of 48 dots, which embodies the if case in the above preset formula:
table two
It should be noted that each Bank in the 16 banks corresponds to one column in the second table, i.e., 0 to 15 columns in the second table represent 16 banks, and the rows in the second table represent address offset amounts, and each row increases by one from 0, i.e., 0 to 2 rows in the second table represent 3 address offset amounts offset.
It can be seen that 48-point butterfly operations exist, the radix R0 of the first-level butterfly operation is 16, the radix R1 of the second-level butterfly operation is 3, and R1 is not equal to the power of 2, and at this time, address shift is not needed, because 0,3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 42, 45 involved in the first-level butterfly operation are stored in different banks, there is no address conflict, and there is no address conflict in the second-level butterfly operation, so the storage address of 48-point butterfly operation does not need to be changed.
For ease of understanding, the following table three shows a regular memory address of 192 dots and a table four shows a memory address of 192 dots subjected to address offset, which embodies the elseif case in the above preset formula:
table III
Table four
It can be seen that 192 points have three levels of butterfly operations, the radix R0 of the first level of butterfly operations is 16, the radix R1 of the second level of butterfly operations is 4, and the radix R2 of the third level of butterfly operations is 3, it can be determined that the values 0, 48, 96, 144 required for the first level of butterfly operations are stored in the same memory Bank under the conventional memory address, 36, 84, 132, 180 are stored in the same memory Bank, 24, 72, 120, 168 are stored in the same memory Bank, 12, 60, 108, 156 are stored in the same memory Bank, and the conventional memory address has address conflict during the butterfly operations, so there is address conflict according to the preset formula
The displacement value of the storage address under each offset address can be obtained by calculation and rounding: when the address offset is 0, storing the address displacement value as 0, and not carrying out address displacement; when the address offset is 1, storing the address displacement value as 0, and not carrying out address displacement; when the address offset is 2, storing the address displacement value as 0, and not carrying out address displacement; when the address offset is 3, the address displacement value is stored to be 1, and all units in the row are sequentially displaced to the right by one grid in a circulating way; when the address offset is 4, the address displacement value is stored to be 1, and all units in the row are sequentially displaced to the right by one grid in a circulating way; when the address offset is 5, the address displacement value is stored to be 1, and all units in the row are sequentially displaced to the right by one grid in a circulating way; when the address offset is 6, the address displacement value is stored to be 2, and all units in the row are sequentially circularly displaced to the right by two grids; when the address offset is 7, the address displacement value is stored to be 2, and all units in the row are sequentially circularly displaced to the right by two grids; when the address offset is 8, the address displacement value is stored to be 2, and all units in the row are sequentially displaced to the right circularly for two grids; when the address offset is 9, the address displacement value is stored to be 3, and all units in the row are sequentially circularly displaced to the right for three grids; in the address biasWhen the shift amount is 10, the shift value of the storage address is 3, and all units in the row are sequentially shifted to the right circularly for three grids; when the address offset is 11, the address displacement value is stored to be 3, and all units in the row are sequentially circularly displaced to the right for three grids; the address conflict does not occur in the storage address after the address displacement during the first-stage butterfly operation. As for the 0,3, 6 and 9 related to the second stage butterfly operation, the 0,1 and 2 related to the third stage butterfly operation are in different memory banks, and address displacement is not needed, so that address conflict does not occur in the 192-point butterfly operation.
For ease of understanding, the following table five shows a 128-point normal memory address and a table six shows an address offset 128-point memory address, embodying the else case in the above predetermined formula:
table five
Table six
Wherein, 128 points exist two-stage butterfly operation, the first stage butterfly operation is the butterfly operation of radix 16, the second stage butterfly operation is the butterfly operation of radix 8, it can be seen from table two that the values required for the first stage butterfly operation are 0,8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, wherein 0,16, 32, 48, 64, 80, 96, 112 are stored in the same memory Bank, there is an address conflict, 8, 24, 40, 56, 72, 88, 104, 120 are stored in the same memory Bank, there is an address conflict, here, the radix R1 of the second stage butterfly operation is 8, so according to the above-mentioned preset formula
And toAnd rounding the calculation result to obtain a storage address displacement value corresponding to each address offset: when the address offset is 0, the address displacement is not carried out; when the address offset is 1, storing the address displacement value as 1, and circularly displacing all the units of the row to the right by one grid in sequence; when the address offset is 2, the address displacement value is stored to be 2, and all units in the row are sequentially displaced to the right by two grids in a circulating way; and analogizing in sequence until the address displacement value is 7 when the address offset is 7, circularly displacing all units of the row to the right for seven grids in sequence, and then showing that the address conflict of the first-stage butterfly operation is solved, and the cardinal number of the second-stage butterfly operation is 8, so that the arrangement itself has no address conflict and does not need to carry out address displacement. Thus, no address collision occurs in the 128-point butterfly operation.
By the method, the storage address displacement values under different sequence lengths can be determined, and after address collision is avoided, butterfly operation can simultaneously read related data of all storage banks, so that the speed of butterfly operation and the signal processing efficiency of 5G communication are greatly improved.
And 402, writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data.
After determining the storage address displacement value corresponding to each address offset, the address manager may write the input data into the first memory according to a new storage address subjected to address displacement, that is, first obtain a reference storage sequence in which the input data is sequentially written into each storage line, and then sequentially move the reference storage sequence of each storage line to the right to obtain the storage data, where each storage line corresponds to one address offset. This step is the basic function of the address manager and is not described herein.
And 403, simultaneously reading the storage data from the first memory through an operation module, performing butterfly computation to obtain operation data, and storing the operation data in a second memory.
The operation module may be an independent butterfly operation module, such as a radix-16 butterfly operation unit, and the address manager positions a storage address of data required for each level of butterfly operation according to a storage address displacement value corresponding to each address offset, the independent butterfly operation module reads data from the storage address of the data required for each level of butterfly operation to perform butterfly operation to obtain operation data, and the independent butterfly operation module writes the operation data into the second memory again according to the storage address when the operation data is read through the address manager. The radix-16 butterfly, the radix-8 butterfly, the radix-4 butterfly, the radix-2 butterfly, the radix-5 butterfly, and the radix-3 butterfly are well known in the art, and detailed computation processes are not described herein.
Optionally, the operation module may include a plurality of parallel butterfly operation units to implement parallel operation of low-order butterfly operations with radix less than 16, where the parallel operation of the low-order butterfly operations is divided into parallel operation of low-order butterfly operations with power of 2 and parallel operation of low-order butterfly operations with power other than power of 2, that is, the butterfly operation unit with radix 16 may be regarded as 2 butterfly operation units with radix 8, 4 butterfly operation units with radix 4, and 8 butterfly operation units with radix 2. During parallel operation, the purpose of solving the conflict is achieved by regularly selecting the buttons participating in the parallel operation.
In the parallel operation of the low-order butterfly operation of the power of 2, the rule for selecting the parallel butterfly operation unit is as follows: all the butterfly operation units operated in parallel only have the digit adjacent to the radix on the left side (high order digit) increment change, and the rest digits of the radix which is not the butterfly operation of the stage are kept unchanged. All the digit changes are traversed by the rule, and the butterfly operation of one stage is completed.
Specifically, taking 480 points as an example, as shown in fig. 5A, the second stage of the 480-point DFT is radix-2 operation, and 8 parallel butterflies of radix-2 are performed thereon: 8 radix-2 butterfly units in parallel, with the digit n3 to the left of R1 as increment 1; the highest bit (n3) of each BF participating in parallel is different, and the remaining three bits (n2, n1, n0) are the same; the butterfly units as shown participate in the same set of parallel operations;
(0,15), (30,45), (60,75), (90,105), (120,135), (150,165), (180,195), (210,225) are a group;
(240,255), (270,285), (300,315), (330,345), (360,375), (390,405), (420,435), (450,465) are a group, not shown;
(1,16), (31,46), (61,76), (91,106), (121,136), (151,166), (181,196), (211,226) are a group;
by analogy, all group items may be determined.
Because only high bits of a plurality of butterfly operation units which are operated in parallel are different, the parallel operation can be ensured not to generate address conflict because the butterfly operation units are subjected to address displacement.
In the parallel operation of the low-order butterfly operation of the power of 2, that is, the parallel butterfly operation of radix 3 or the parallel butterfly operation of radix 5, the address shift performed before may be canceled, and then the parallel butterfly operation may be performed by selecting a certain digit as a change digit and fixing other digits.
Specifically, still taking 480 as an example, as shown in fig. 5B, the 480-point third-stage butterfly operation is a radix-3 butterfly operation, and a radix-3 5 parallel butterfly operation is performed on the third-stage butterfly operation: parallel, 5 radix-3 butterflies, increment by 1 by the digit n2 to the left of R2, advancing one digit forward (n3) as the digit's number increases to the radix of the digit; the most significant bit (n2 or n3) participating in each butterfly operation in parallel is different, and the butterflies (n1 and n0) formed by the remaining two bits are the same; the butterfly unit shown in FIG. 5B participates in parallel operation;
(0,5,10), (15,20,25), (30,35,40), (45.50.55), (60,65,70) is a group;
(75,80,85), (90,95,100), (105,110,115), (120.125.130), (135,140,145) are a group, not shown;
by analogy, 5 radix-3 butterfly operation units which operate in parallel have three data on each butterfly operation unit, and the indexes of the three data can be expressed as the following combination:
(n2,n2+1,n2+2,n2+3,n2+4)*R2R3+(0,1,2)*R3+n0
according to the above formula, these 15 numbers are respectively:
(n2R2R3+n0,n2R2R3+1+n0,n2R2R3+2+n0)
((n2+1)R2R3+n0,(n2+1)R2R3+1+n0,(n2+1)R2R3+2+n0)
((n2+2)R2R3+n0,(n2+2)R2R3+1+n0,(n2+2)R2R3+2+n0)
((n2+3)R2R3+n0,(n2+3)R2R3+1+n0,(n2+3)R2R3+2+n0)
((n2+4)R2R3+n0,(n2+4)R2R3+1+n0,(n2+4)R2R3+2+n0)
since R2 and R3 are not 3, i.e. 5, the 15 numbers and the 16 numbers must be different in remainder. That is, if all data used for DFT computation is not address shifted, there is no address conflict when performing the above parallel operation.
Therefore, the data processing efficiency can be greatly improved through the low-order parallel butterfly operation.
And 404, reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset, and processing the operation data to obtain output data.
The address manager dynamically adjusts the read address in the second memory according to the output clock cycle to output data, and may be implemented by the following pseudo codes:
wherein, the bankiIt may be calculated according to the above-mentioned preset formula, or may be stored as a table when determining the storage address displacement value in step 401, where the lookup may be performed according to the address offset, since the input/output data of FFT/DFT may not be evenly divided by 16, there may be more read data than actual data, and the length of DFT is known information, and the redundant data has no influence.
In summary, the following beneficial effects can be achieved by the above method:
(1) the input data of all the storage banks are read and written simultaneously to carry out butterfly operation, so that the speed of the butterfly operation is greatly improved, for example, the FFT operation with the length of 4096 only needs about 800 cycles, and the delay can be almost ignored; (2) the butterfly operation of radix 3 and the butterfly operation of radix 5 can multiplex the architecture of the butterfly operation of radix 16, the same architecture in the embodiment of the application can complete FFT (power of 2) and DFT (power of non-2), and the area cost is reduced; (3) when the low-order butterfly operation with the radix number smaller than 16 multiplexes the related circuits of the butterfly operation unit of the radix 16, all the low-order butterfly operations are processed in parallel to the maximum extent by the address conflict solution provided by the embodiment of the application, and the operation efficiency of the related circuits is maximized; (4) because the framework of the embodiment of the application supports FFT and DFT at the same time, the DFT module and the FFT module do not need to be tested and verified respectively, and the time cost of verification is reduced.
The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It is understood that the electronic device comprises corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above-mentioned functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Fig. 6 is a block diagram showing a functional block configuration of a data processing apparatus based on fourier transform according to the above-described embodiment, in a case where each functional block is divided according to each function. As shown in fig. 6, the fourier transform-based data processing apparatus 600 includes:
an address calculation unit 610 for calculating a storage address displacement value of input data at each address offset amount by the address manager;
a storage writing unit 620, configured to write the input data into the first memory according to the storage address displacement value corresponding to each address offset to obtain storage data;
a storage reading unit 630, configured to read the storage data from the first memory through an operation module at the same time, perform butterfly computation to obtain operation data, and store the operation data in a second memory;
and the output processing unit 640 is configured to read the operation data from the second memory according to the storage address displacement value corresponding to each address offset, and process the operation data to obtain output data.
In the case of an integrated unit, fig. 7 shows a block diagram of functional units of a fourier transform-based data processing apparatus according to the above-described embodiment. As shown in fig. 7, the data processing apparatus 700 based on fourier transform includes a processing unit 701 and a communication unit 702, where the processing unit 701 is configured to execute any step in the above method embodiments, and when performing data transmission such as sending, the communication unit 702 is optionally invoked to complete the corresponding operation.
The fourier transform-based data processing apparatus 700 may further include a storage unit 703 for storing program codes and data of an electronic device. The processing unit 701 may be a central processing unit, the communication unit 702 may be a radio frequency module, and the storage unit 703 may be a memory. It can be understood that, since the method embodiment and the apparatus embodiment are different presentation forms of the same technical concept, the content of the method embodiment portion in the present application should be synchronously adapted to the apparatus embodiment portion, and is not described herein again.
Embodiments of the present application also provide a computer storage medium, where the computer storage medium stores a computer program for electronic data exchange, the computer program enabling a computer to execute part or all of the steps of any one of the methods described in the above method embodiments, and the computer includes an electronic device.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package, the computer comprising an electronic device. It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application. In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (13)
1. A method for processing data based on fourier transform, the method comprising:
calculating a storage address displacement value of the input data under each address offset through an address manager;
writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data;
simultaneously reading the storage data from the first memory through an operation module, performing butterfly computation to obtain operation data, and storing the operation data in a second memory;
and reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to process the operation data to obtain output data.
2. The method of claim 1, wherein calculating, by the address manager, a storage address displacement value for the input data at each address offset comprises:
determining the corresponding butterfly operation series and the cardinal number of each stage of butterfly operation according to the sequence length of the input data;
and determining the storage address displacement value of the input data under each address offset according to the radix of each stage of butterfly operation and the address offset.
3. The method of claim 2, wherein determining the stored address displacement value of the input data at each address offset based on the radix of the each level butterfly and the address offset comprises:
and when the cardinality of the second-stage butterfly operation is a preset value, determining that the storage address displacement value of the input data under each address offset is 0.
4. The method of claim 2, wherein determining the stored address displacement value of the input data at each address offset based on the radix of the each level butterfly and the address offset comprises:
and when the cardinality of the second-level butterfly operation is not a preset value and the cardinality of the third-level butterfly operation is a preset value, substituting the cardinality of the third-level butterfly operation and the cardinality and each address offset of the butterfly operation after the third-level butterfly operation into a first displacement formula, and determining the storage address displacement value of the input data under each address offset according to the output of the first displacement formula.
5. The method of claim 2, wherein determining the stored address displacement value of the input data at each address offset based on the radix of the each level butterfly and the address offset comprises:
and when the cardinality of the second-level butterfly operation is not a preset value and the cardinality of the third-level butterfly operation is a preset value, substituting the cardinality of the third-level butterfly operation and the cardinality and each address offset of the butterfly operation after the third-level butterfly operation into a second displacement formula, and determining the storage address displacement value of the input data under each address offset according to the output of the second displacement formula.
6. The method of claim 1, wherein the first memory comprises a plurality of memory lines; the writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data includes:
acquiring a reference storage sequence of the input data written into each storage line in sequence;
and sequentially shifting the reference storage sequence of each storage line to the right by the storage address displacement value corresponding to each address offset to obtain the storage data, wherein each storage line corresponds to one address offset.
7. The method of claim 2, wherein the operation module comprises an independent butterfly operation module; the reading the storage data from the first memory simultaneously by the operation module to perform butterfly computation to obtain operation data, and storing the operation data in the second memory, includes:
positioning the storage address of the data required by each stage of butterfly operation according to the storage address displacement value corresponding to each address offset;
reading data from a storage address of data required by each stage of butterfly operation through the independent butterfly operation module to perform butterfly operation to obtain operation data;
and writing the operation data into the second memory according to the storage address of the data required by each stage of butterfly operation.
8. The method of claim 2, wherein the operation module comprises a plurality of parallel butterfly operation units; the reading the storage data from the first memory simultaneously by the operation module to perform butterfly computation to obtain operation data, and storing the operation data in the second memory, includes:
and simultaneously reading the storage data from the first memory through the plurality of parallel butterfly operation units to perform a first parallel butterfly operation to obtain the operation data, wherein the first parallel butterfly operation comprises parallel operation with a base number of 2 to the power of the power.
9. The method of claim 2, wherein the operation module comprises a plurality of parallel butterfly operation units; the reading the storage data from the first memory simultaneously by the operation module to perform butterfly computation to obtain operation data, and storing the operation data in the second memory, includes:
and simultaneously reading the storage data from the first memory through the plurality of parallel butterfly operation units to perform second parallel butterfly operation to obtain the operation data, wherein the second parallel butterfly operation comprises parallel operation with odd-numbered base numbers.
10. The method of claim 1, wherein reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to obtain output data, and wherein the reading the operation data from the second memory comprises:
reading the operation data from the second memory in a reverse order according to the storage address displacement value corresponding to each address offset;
and outputting the operation data read by the inverted sequence in the inverted sequence to obtain the output data.
11. A fourier transform-based data processing apparatus, characterized in that the apparatus comprises:
an address calculation unit for calculating a storage address displacement value of the input data at each address offset amount by the address manager;
the storage writing unit is used for writing the input data into a first memory according to the storage address displacement value corresponding to each address offset to obtain storage data;
the storage reading unit is used for simultaneously reading the storage data from the first storage through an operation module to perform butterfly calculation to obtain operation data and storing the operation data in a second storage;
and the output processing unit is used for reading the operation data from the second memory according to the storage address displacement value corresponding to each address offset to process the operation data to obtain output data.
12. An electronic device comprising an application processor, a memory, and one or more programs stored in the memory and configured for execution by the application processor, the programs comprising instructions for performing the steps of the method of any of claims 1-10.
13. A computer storage medium, characterized in that the computer storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to carry out the method according to any one of claims 1 to 10.
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