CN102855222A - Address mapping method and device of FFT (Fast Fourier Transform) of parallel branch butterfly unit - Google Patents
Address mapping method and device of FFT (Fast Fourier Transform) of parallel branch butterfly unit Download PDFInfo
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Abstract
The invention discloses the address mapping method and device of a kind of FFT of parallel branch butterfly unit, method includes: that the number of sampling points of foundation FFT determines the total series converted between radix and FFT grades; Sampled point is stored into the memory bank of the first memory bank group in order; It is converted between executing FFT grades, when current series m is more than or equal to 1 and is less than M, the pending data or intermediate data that will be stored in the memory bank for working as prime are written in parallel to next stage according to arranging by logical block shifting one, row by memory bank shifting one cyclic shift mode
In a Different Logic block; Until stopping converting between grade when current series m is equal to M. By the above-mentioned transformation based between FFT grades and according to the method for row, column cyclic shift, realize parallel branch butterfly unit FFT address of cache, it is not had an impact between each other by the concurrent reading and concurrent writing between the Mapping implementation multi-group data between address, guarantees the continuity and validity in FFT calculating process.
Description
Technical field
The present invention relates to communication technical field, in particular, relate to address mapping method and the device of a kind of FFT of parallel branch butterfly unit.
Background technology
Current, in the broadband wireless system along with the chip rate that requires to transmit improves constantly, transmission bandwidth is also in the more and more wider situation, be the interference in the elimination transmission course and decline etc., the Physical layer of broadband wireless system adopts OFDM (Orthogonal Frequency Division Multiplexing more, OFDM) technology, such as WiMAX (Worldwide Interoperability for Microwave Access, the worldwide interoperability for microwave access), WiFi (wireless fidelity, WLAN (wireless local area network)), DVB (Digital Video Broadcasting, digital video broadcasting), DAB (Digital Audio Broadcasting, digital signal broadcasting) etc., the common feature of said system baseband modulation part namely all adopts FFT (Fast Fourier Transformation, Fast Fourier Transform (FFT)) as " modulation engine ".Because the continuous upgrading of broadband system, people are also harsher to the requirement of bandwidth, are the processing power of elevator system, to meet above-mentioned requirements can be at a high speed, parallel, can expand and cheaply the design requirement of FFT also become urgently.
In the prior art, during the realization framework of design parallel FFT (main control unit and the external memory storage that in the FFT of correspondence device, comprise the coordinated scheduling between control framework internal module), in order to solve inevitable high speed, parallel reading and writing data problem, the general mode of a plurality of memory banks (radix of FFT) that adopts solves the problem of above-mentioned parallel data read-write, and adopts lower-cost single port or dual-ported memory more.
But, operation rule according to FFT (namely utilizes the periodicity of twiddle factor and symmetry to carry out computing, this twiddle factor is stored in the twiddle factor storer), in the process of the FFT address mapping of carrying out butterfly unit, when intermediate data is write the next stage set of memory banks, can affect reading of back to back parallel data, can not guarantee continuity and the validity of FFT computing, especially more when counting of FFT, radix is large or when a plurality of radix hybrid operation is arranged, when carrying out the parallel FFT computing, more can not guarantee continuity and the validity of FFT computing.
Summary of the invention
In view of this, the invention provides address mapping method and the device of a kind of FFT of parallel branch butterfly unit, to overcome prior art in the mapping process of the FFT address of butterfly unit, can not guarantee the continuity of FFT computing and the problem of validity.
For achieving the above object, the invention provides following technical scheme:
The address mapping method of a kind of Fast Fourier Transform (FFT) FFT of parallel branch butterfly unit comprises:
Determine the radix of FFT according to the sampled point number of Fast Fourier Transform (FFT) FFT, and total progression M of FFT inter-stage conversion corresponding to described radix;
In order described sampled point is stored in the memory bank of the first set of memory banks, the number of described memory bank is the numerical value D of the Gao Ji in the radix of current definite FFT
Max
Between the first set of memory banks and the second set of memory banks, carry out the conversion of FFT inter-stage according to current definite radix, be specially:
When current progression m more than or equal to 1 and during less than M, move one, row according to row by logical block and move one cyclic shift mode by memory bank being stored in pending data in the memory bank of prime or intermediate data, be written in parallel to next stage
In the individual Different Logic piece, the span of described m is 1～M;
The above-mentioned FFT inter-stage of circulation execution is converted into current progression m and equals M.
Preferably, during described execution FFT inter-stage conversion, will work as among the prime m
Individual logical block is divided, and logical block correspondence is divided into D logical block of next stage.
Preferably, the scope of described ring shift comprises:
The range of DO of row is the memory bank number in the set of memory banks;
The range of DO of row is the address number of each memory bank of comprising in each logical block at different levels.
Preferably, the mode of described ring shift data writing is: be shifted by memory bank first, be shifted by logical block, press afterwards the rear data writing of row displacement in the logical block.
Preferably, the mode of described ring shift data writing is: press first row displacement in the logical block, be shifted by logical block, afterwards by the memory bank rear data writing that is shifted.
Preferably, comprising:
When the sampling number of FFT was 4 or 8 integral number power, the radix of determining FFT was single base, and described single base is base 2, base 4 or base 8;
The data D of Gao Ji in the radix of current definite FFT
MaxEqual the numerical value of described single base;
Total progression M of the FFT inter-stage conversion that described single radix is corresponding is take the logarithm of single base as end sampling number.
Preferably, comprising:
When the sampling number of FFT was not 4 or 8 integral number power, the radix of determining FFT was mixed base, and described mixed base is the combination in any of base 2, base 4 or base 8;
The data D of Gao Ji in the radix of current definite FFT
MaxNumerical value for the Gao Ji in the mixed radix;
Total progression M of the FFT inter-stage conversion that described mixed base is corresponding is specially: will not be the product that the sampling number of 4 or 8 integral number power is decomposed into the integral number power numerical value of each single base in the mixed base;
Calculate progression corresponding to each described single base, the summation of obtaining the progression that each single base is corresponding in the described mixed base is total progression M;
When carrying out the conversion of FFT inter-stage, carry out the conversion of FFT inter-stage according to base 4 or base 8 first, afterbody is carried out the computing of base 2 or base 4.
The address mapping device of a kind of Fast Fourier Transform (FFT) FFT of parallel branch butterfly unit comprises main control unit, twiddle factor storer and external memory storage, also comprises:
Parallel branch butterfly unit group is used for the radix through the definite FFT of main control unit control, carries out the computing of FFT inter-stage;
The first internal repository group and the second internal repository group, when being used for storage and carrying out the conversion of FFT inter-stage, row move one, row by logical block and move pending data or the intermediate data that one cyclic shift mode is written in parallel to or reads by memory bank;
Address-generation unit is used for providing the address of reading when carrying out the conversion of FFT inter-stage to described twiddle factor storer, described external memory storage, described the first internal repository group and the second internal repository group.
Via above-mentioned technical scheme as can be known, compared with prior art, the invention discloses address mapping method and the device of a kind of FFT of parallel branch butterfly unit, based on the conversion of FFT inter-stage with according to row, the method of row ring shift, realize parallel branch butterfly unit FFT address mapping, the inter-stage reading and writing data problem of FFT in the time of can solving the computing of parallel branch butterfly unit, namely do not exert an influence each other by the concurrent reading and concurrent writing between the Mapping implementation multi-group data between the address, guarantee continuity and validity in the FFT calculating process, and can adopt common low-cost single port commonly used or dual-ported memory to realize the parallel FFT computing, further reduce realization cost and complexity.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is embodiments of the invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to the accompanying drawing that provides other accompanying drawing.
Fig. 1 is the address mapping method process flow diagram of the FFT of the embodiment of the invention one disclosed a kind of parallel branch butterfly unit;
Fig. 2 is the schematic flow diagram of 64 DIF4 address mappings of a kind of parallel branch butterfly unit of the present invention FFT;
Fig. 3 is the schematic flow diagram of 64 DIF8 address mappings of a kind of parallel branch butterfly unit of the present invention FFT;
Fig. 4 is a kind of FFT implementation structure synoptic diagram of using parallel branch butterfly unit FFT address mapping method of the present invention.
Embodiment
For quote and know for the purpose of, the explanation of the technical term that hereinafter uses, write a Chinese character in simplified form or abridge and be summarized as follows:
FFT:Fast Fourier Transformation, Fast Fourier Transform (FFT);
DIF: decimation in frequency, a kind of in the fft algorithm, another kind is decimation in time DIT;
Data: data.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
By background technology as can be known, when the reading and writing data problem of utilizing framework of the prior art to solve at a high speed, walk abreast, wherein corresponding FFT device is in the process of the FFT address mapping of carrying out butterfly unit, when the intermediate data in the processing procedure is write the next stage set of memory banks, can affect reading of back to back parallel data, can not guarantee continuity and the validity of FFT computing, especially more when counting of FFT, radix is large or when a plurality of radix hybrid operation is arranged, when carrying out the parallel FFT computing, more can not guarantee continuity and the validity of FFT computing.
Therefore, the invention provides address mapping method and the device of a kind of FFT of parallel branch butterfly unit, do not exert an influence each other by the concurrent reading and concurrent writing between the Mapping implementation multi-group data between the address, guarantee continuity and validity in the FFT calculating process.Detailed process is elaborated by following examples.
Embodiment one
See also accompanying drawing 1, the process flow diagram for the address mapping method of the FFT of a kind of parallel branch butterfly unit disclosed by the invention mainly may further comprise the steps:
Step S101 determines the radix D of FFT according to the sampled point number N of FFT, and total progression M of FFT inter-stage conversion corresponding to described radix D.
In execution in step S101, the FFT of radix D is the radix of carrying out the FFT butterfly unit, and the value of D is relevant with the number N of sampled point.Total progression M of the FFT inter-stage conversion that described radix D is corresponding is then relevant with sampling number N with radix D.Radix in the present invention mainly comprises: base 8, base 4 and base 2, generally speaking, the larger efficient of radix is higher.Wherein, sampling number can extract by DIF, also can extract according to DIT.
Step S102 is stored to described sampled point in the memory bank of the first set of memory banks in order, and the number of described memory bank is the numerical value D of the Gao Ji in the radix of current definite FFT
Max
Step S103 carries out the conversion of FFT inter-stage according to the radix of determining between the first set of memory banks and the second set of memory banks.
Have two groups of set of memory banks in whole FFT system, the inter-stage conversion of carrying out is also rattled in two groups of set of memory banks and is carried out.In execution in step S102, the sampled point N that is drawn into is stored in the memory bank of the first set of memory banks, need to prove that the number of the memory bank in two groups of set of memory banks is the numerical value D of the Gao Ji in the radix of current definite FFT
MaxThe number of the sampled point of storing in each memory bank in each set of memory banks generally speaking, is identical.
Whether step S104 judges the progression m of the current FFT of carrying out inter-stage conversion more than or equal to 1 and less than M, if so, and execution in step S105 then; If not, execution in step S106 then.
Step S105 moves one, row according to row by logical block and moves one cyclic shift mode by memory bank being stored in pending data in the memory bank of prime or intermediate data, is written in parallel to next stage
In the individual Different Logic piece, the span of described m is 1～M.
When execution in step S105 carries out the conversion of FFT inter-stage, will work as among the prime m
Individual logical block is divided, and logical block correspondence is divided into D logical block of next stage.
Division to logical block is described in detail, and the number of the logical block that concrete every one-level is divided is relevant with the radix of its place sum of series FFT, is specially: D
M-1, wherein the span of m is 1～M, namely within total progression (comprising total progression).It should be noted that this division is the logical partitioning in the actual operation process, and a logical block in the upper level is divided into correspondence D logical block of next stage.
Providing an example describes:
When the radix of FFT is 2, sampling number is that total progression M of 64, FFT is 6, and the logical block that calculate its each place progression m this moment is:
When m equals 1, D
M-1=D
0, the first order has a logical block;
When m equals 2, D
M-1=D
1=2, the second level has two logical blocks;
When m equals 3, D
M-1=D
2=4, the third level has four logical blocks;
The like, eight of the fourth stages, 16 of level Vs, the 6th grade 32.Thus, a logical block in the first order is divided into two logical blocks in the second level; Two logical blocks in the second level then are divided into four logical blocks in the third level successively, cut apart successively.Need to prove, in the process of cutting apart, divided logical block with cut apart after logical block be one to one, for example have four logical blocks in the third level, respectively it is numbered the first logical block to the four logical blocks of the third level, and the first logical block that is numbered the second level and second logical block of two logical blocks in the second level, logical block after its correspondence is cut apart, namely the logical block in the corresponding third level is respectively: the first logical block in the second level is divided into the first logical block and the second logical block of the third level; The second logical block in the second level then is divided into the 3rd logical block and the 4th logical block of the third level, when namely cutting apart the logical block in the upper level, cuts apart successively and corresponding with the logical block cut apart in the next stage.
Step S106, the current progression m that carries out the FFT computing equals M, and the FFT inter-stage conversion that above-mentioned circulation is carried out has arrived afterbody, and namely total progression M level place stops the conversion of FFT inter-stage, namely stops the FFT computing.
At execution in step S104 to the process of step S106, at current progression m during less than total progression M, then carry out successively the conversion of FFT inter-stage, namely begin to carry out to the second level conversion (carrying out conversion to the second set of memory banks from the first set of memory banks) from the first order, and then carry out conversion (carrying out conversion to the first set of memory banks from the second set of memory banks) from the second level to the third level, carry out successively.If total progression is 2, then only carries out an inter-stage conversion and get final product.
If total progression is larger, then the mode according to step S105 loops above-mentioned inter-stage conversion, ring shift etc., namely utilize the mode of row (address in logical block or the piece), row (memory bank) ring shift to realize the intermediate data that upper level FFT handles is write in the pending D of the next stage memory bank, for the FFT that does not affect next stage processes computing, the data that are disposed can be written in parallel to the D in the next stage
M-1In (m is the residing progression of current computing) individual Different Logic piece.
Need to prove that in the process of carrying out above-mentioned ring shift, the range of DO of row is the memory bank number in the set of memory banks; The range of DO of row is the address number of each memory bank of comprising in each logical block at different levels.
In addition, the mode of above-mentioned ring shift data writing can for: be shifted by memory bank first, be shifted by logical block again, press afterwards in the logical block data writing after the row displacement; Also can for: press first row displacement in the logical block, be shifted by logical block again, afterwards by the memory bank rear data writing that is shifted.The present invention does not limit this, and namely the order of displacement is not unique.
The method that provides by the invention described above, based on the conversion of FFT inter-stage with according to the method for row, column ring shift, realize parallel branch butterfly unit FFT address mapping, the inter-stage reading and writing data problem of FFT in the time of can solving the computing of parallel branch butterfly unit, and can adopt common low-cost single port commonly used or dual-ported memory to realize the parallel FFT computing, further reduce realization cost and complexity.
What need to describe is, about the impact on the selected radix of FFT of the value of the sampling number N of FFT.
When the sampling number N of FFT was 4 or 8 integral number power, the radix of determining FFT was single base, and described single base is base 2, base 4 or base 8.So, the data D of the Gao Ji in the radix of current definite FFT
MaxEqual the numerical value of described single base, namely determine the number of the memory bank in the current set of memory banks.
And for total progression M of FFT inter-stage conversion corresponding to this single radix for take the logarithm of single base as end sampling number.Can use formula (1) expression:
Wherein, M is total progression of FFT, and D is the radix of FFT, and the sampling number of N for determining is the integral number power of D.
When the sampling number of FFT was not 4 or 8 integral number power, the radix of determining FFT was mixed base, and described mixed base is the combination in any of base 2, base 4 or base 8.So, the data D of the Gao Ji in the radix of current definite FFT
MaxNumerical value for the Gao Ji in the mixed radix.Be base 2 and base 8 combination, then D such as mixed base
Max=8; Be base 2 and base 4 combination, then D such as mixed base
Max=4.
And for total progression M of FFT inter-stage conversion corresponding to this mixed base, then sampled point is decomposed into the product of the integral number power numerical value of each single base in the mixed base, and then calculate progression corresponding to each single base, namely be retrieved as base 2, base 4 or basic 8 o'clock each self-corresponding progression according to formula (1), the summation of calculating its progression is total progression M of FFT inter-stage conversion.Such as N=128, adopt base 2 and base 4 to mix, it is decomposed into 1 power of 2 and 3 power products of 4, according to formula (1) as can be known,
M=3+1=4.In fact be, first three level of FFT inter-stage conversion adopts base 4, and afterbody adopts base 2.
For mixed base, when carrying out the conversion of FFT inter-stage, carry out the conversion of FFT inter-stage according to base 4 or base 8 first, afterbody is carried out the computing of base 2 or base 4.
Equally, the method that provides by the invention described above, based on the conversion of FFT inter-stage with according to the method for row, column ring shift, realize parallel branch butterfly unit FFT address mapping, the inter-stage reading and writing data problem of FFT in the time of can solving the computing of parallel branch butterfly unit, and can adopt common low-cost single port commonly used or dual-ported memory to realize the parallel FFT computing, further reduce realization cost and complexity.
In addition, both can be used for basic 4, basic 8 efficient realization for the disclosed address mapping method of the invention described above, also can be used for the operating range of base 2.The below provides specific embodiment and is elaborated.
Embodiment two
See also accompanying drawing 2, be the schematic flow diagram of 64 the DIF4 address mappings of a kind of parallel branch butterfly unit FFT shown in the present invention, concrete shift process is as described below:
As shown in Figure 2, according to DIF namely according to the mode of decimation in frequency, altogether sampling (extraction) 64 points, carry out computing according to the base 4 of FFT, namely the value of D is that the value of 4, N is 64.Thus, can draw according to formula (1), total progression M of FFT is 3, and the middle progression of the FFT conversion of these 64 DIF4 is 2 grades successively, as shown in Figure 2 A and B, and wherein, A represents first order conversion set of memory banks, B represents second level conversion set of memory banks.
As shown in Figure 2, two set of memory banks in the Two Stages are respectively:
Comprise RAMA1, RAMA2, RAMA3, RAMA4 in the group 1;
Comprise RAMB1, RAMB2, RAMB3, RAMB4 in the group 2.
On the basis of known above-mentioned pacing items, at first, with data to be transformed (sampled point that namely obtains) according to writing successively in the set of memory banks 1 such as Fig. 2 order.
Owing to be the concurrent operation of base 4, therefore, process according to parallel read-out, 4 data of parallel read-out from organize 4 memory banks of 1, first group is: 0, the pending data in 16,32 and 48 addresses (data that read in the follow-up explanation with the sign data mode represent, such as data0, data16, data32, data48 etc.).Being written in parallel to after butterfly unit is processed in 4 memory banks in the set of memory banks 2, in problem to be solved by this invention, mainly is will finish the parallel of pending data or intermediate data on the basis of the concurrent operation that does not affect inter-stage to read and write.
Therefore, in method provided by the present invention, in order not affect second level parallel computation, write rule as shown in Figure 2, namely first a logical block in the first order is divided in the corresponding second level four logical blocks and respectively to its numbering; Then, according to writing that the mode of row, column ring shift walks abreast.Be specially:
Data0 is write among first memory bank RAMB1 of first logical block in the set of memory banks 2; Data16 is write among the memory bank RAMB2 after the displacement of the corresponding data0 memory bank of second logical block row, column; Data32 is write among the memory bank RAMB3 after the displacement of the corresponding data16 memory bank of the 3rd logical block row, column; Data48 is write among the memory bank RAMB4 after the displacement of the corresponding data32 memory bank of the 4th logical block row, column.Finishing the pending data of first group of parallel output in the above-mentioned first order carries out being written in parallel to the second level behind the first order conversion A.
In like manner, carry out the mode that is written in parallel to behind the first order conversion A as shown in Figure 2 for pending data data1, data17, data33 and the data49 of second group of parallel output, be about to data1 and write in the set of memory banks 2 among the memory bank RAMB2 after the displacement of the corresponding data0 position circulation of first logical block row, column; Data17 writes in the set of memory banks 2 among the memory bank RAMB3 after the displacement of the corresponding data16 position circulation of second logical block row, column; Data33 writes in the set of memory banks 2 among the memory bank RAMB4 after the displacement of the corresponding data32 position circulation of the 3rd logical block row, column; Data49 writes in the set of memory banks 2 among the memory bank RAMB1 after the displacement of the corresponding data48 position circulation of the 4th logical block row, column.
Need to prove, for follow-up from the first order data of parallel output write again fashionable, all according to before the row, column displacement that circulates of the position of data writing.The scope of this circulation row, column displacement is whole logical block.
As shown in Figure 2, for second level conversion B, in the same way the logical block correspondence in the upper level is divided into 16 logical blocks, each corresponding its four logical block that are split to form of a logical block in the upper level.
Equally, in the process of carrying out second level conversion B, its direction is for reading pending data or intermediate data writes in the set of memory banks 1 by group is parallel from set of memory banks 2.Write rule as shown in Figure 2, its detailed process is identical with the process of carrying out first order conversion A.As: first of parallel output group of pending data is data0, data4, data8, data12 from set of memory banks 2, data0 write among first memory bank RAMA1 of first logical block in the set of memory banks 1; Data4 is write among the memory bank RAMA2 after the displacement of the corresponding data0 memory bank of second logical block row, column; Data8 is write among the memory bank RAMA3 after the displacement of the corresponding data4 memory bank of the 3rd logical block row, column; Data12 is write among the memory bank RAMA4 after the displacement of the corresponding data8 memory bank of the 4th logical block row, column.
In like manner, pending data data13, data1, data5 and data9 for second group of parallel output, as shown in Figure 2, data13 is write in the set of memory banks 1 among the memory bank RAMA1 after the displacement of the corresponding data0 position circulation of first logical block row, column in the 4th logical block; Data1 writes in the set of memory banks 1 in the first logical block among the memory bank RAMA2 after the displacement of the corresponding data4 position circulation of second logical block row, column; Data5 writes in the set of memory banks 1 in the 3rd logical block among the memory bank RAMA3 after the displacement of the corresponding data8 position circulation of second logical block row, column; Data9 writes in the set of memory banks 1 in the 3rd logical block among the memory bank RAMA4 after the displacement of the corresponding data12 position circulation of the 4th logical block row, column.
Need to prove, the pending data of storing in memory bank corresponding to a logical block in the upper level, be written in parallel to each time and row, column when displacement of circulating all carries out for logical block corresponding in its next stage that is split to form, i.e. writing shown in the recycle design when carrying out conversion B in the second level among Fig. 2.
Embodiment three
On the disclosed basis of the invention described above embodiment, as shown in Figure 3, the invention also discloses the schematic flow diagram of 64 DIF8 address mappings of a kind of parallel branch butterfly unit FFT, concrete shift process is as described below:
As shown in Figure 3, according to DIF namely according to the mode of decimation in frequency, altogether sampling (extraction) 64 points, carry out computing according to the base 8 of FFT, namely the value of D is that the value of 8, N is 64.Thus, can draw according to formula (1), total progression M of FFT is 2, and the middle progression of the FFT conversion of these 64 DIF4 is 1 grade successively, and A represents first order conversion as shown in Figure 3.
As shown in Figure 3, two set of memory banks in the Two Stages are respectively:
Comprise RAMA1, RAMA2, RAMA3, RAMA4, RAMA5, RAMA6, RAMA7, RAMA8 in the group 1;
Comprise RAMB1, RAMB2, RAMB3, RAMB4, RAMB5, RAMB6, RAMB7, RAMB8 in the group 2.
On the basis of known above-mentioned pacing items, at first, with data to be transformed (sampled point that namely obtains) according to writing successively in the set of memory banks 1 such as Fig. 3 order.
In the process that the butterfly unit of parallel branch is processed, 8 data parallel read-outs with in the set of memory banks 1 are written in parallel in the set of memory banks 2 after the processing again.For the data that do not affect second level FFT are processed, 8 data of parallel read-out are that data (the data back of n address all adopts the form of the data to be indicated) employing in 0 address, 8 addresses, 16 addresses, 24 addresses, 32 addresses, 40 addresses, 48 addresses and 56 addresses writes in the set of memory banks 2 such as drawing method.
8 data are write in the different logical blocks successively, and namely list at memory bank and to be shifted.The writing mode of follow-up data is also identical, is ring shift during the row displacement.
By the described specific embodiment of the invention described above as can be known, based on the conversion of FFT inter-stage with according to the method for row, column ring shift, realize parallel branch butterfly unit FFT address mapping, the inter-stage reading and writing data problem of FFT in the time of can solving the computing of parallel branch butterfly unit, and can adopt common low-cost single port commonly used or dual-ported memory to realize the parallel FFT computing, further reduce realization cost and complexity.
Need to prove, when the computing that sampling obtains is counted, be that sampling number N is not when being 4 or 8 integral number power, in the process of carrying out the mapping of parallel branch butterfly unit FFT address, method according to above-mentioned conversion, carry out first the conversion of base 4 or base 8, afterbody then adopts the compute mode of base 2 or base 4 to finish and gets final product.
In addition, during for the processing of multistage base, the displacement of columns and rows is ring shift, and is same, and the range of DO of row is the number of memory bank in the set of memory banks, and the range of DO of row is the address number of each memory bank of comprising in the logical block.
Describe a kind of parallel branch butterfly unit FFT address mapping method among the disclosed embodiment of the invention described above in detail, can adopt the device of various ways to realize for method of the present invention, therefore the invention also discloses a kind of parallel branch butterfly unit FFT address mapping device, the below provides specific embodiment and is elaborated.
See also accompanying drawing 4, be the address mapping device of the Fast Fourier Transform (FFT) FFT of a kind of parallel branch butterfly unit disclosed by the invention, be i.e. the structural representation realized of FFT.Mainly comprise: main control unit 101, address-generation unit 102, twiddle factor storer 103, the first internal repository group 104, the second internal repository group 105, parallel branch butterfly unit 106 and external memory storage 107.
Parallel branch butterfly unit group 106 is formant, is used for determining through main control unit control the radix of FFT, carries out the computing of FFT inter-stage.
The first internal repository group 104 and the second internal repository group 105, when being used for storage and carrying out the conversion of FFT inter-stage, row moves one, row by logical block and moves pending data or the intermediate data that one cyclic shift mode is written in parallel to by memory bank.
Address-generation unit 102 is used for providing the address of reading when carrying out the conversion of FFT inter-stage to described twiddle factor storer 103, described external memory storage 107, described the first internal repository group 104 and the second internal repository group 105.
Its concrete implementation is: main control unit 101 is responsible for the coordinated scheduling between the control internal module, comprise that mainly the control address-generation unit is external memory storage 107, the first internal repository group 104 and the second internal repository group 105 and twiddle factor storer 103 provide reading address, also need control simultaneously parallel branch butterfly unit group 106 to select the radix of butterfly unit, can comprise base 2 in it, the parallel branch butterfly unit of base 4 or base 8, adopt which kind of branch and when adopt by main control unit and controlled, main transform method of the present invention namely is embodied in this unit, is the arithmetic core of whole FFT.
Have the required twiddle factor of FFT conversion in the twiddle factor storer 103, for cooperating the parallel computation of FFT, twiddle factor also can adopt the form of a plurality of memory bank storages.The first internal repository group 104 and the second internal repository group 105 are mainly used to preserve the intermediate data of FFT computing, form the maximal value of the corresponding FFT computing of D radix by D memory bank.
In sum:
The method and apparatus that provides by the invention described above, based on the conversion of FFT inter-stage with according to row, the method of row ring shift, realize parallel branch butterfly unit FFT address mapping, do not exert an influence each other by the concurrent reading and concurrent writing between the Mapping implementation multi-group data between the address, guarantee continuity and validity in the FFT calculating process, the inter-stage reading and writing data problem of FFT in the time of can solving the computing of parallel branch butterfly unit, and can adopt common low-cost single port commonly used or dual-ported memory to realize the parallel FFT computing, further reduce realization cost and complexity.
Each embodiment adopts the mode of going forward one by one to describe in this instructions, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For the disclosed device of embodiment, because it is corresponding with the disclosed method of embodiment, so description is fairly simple, relevant part partly illustrates referring to method and gets final product.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random access memory (RAM), internal memory, ROM (read-only memory) (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (8)
1. the address mapping method of the Fast Fourier Transform (FFT) FFT of a parallel branch butterfly unit is characterized in that, comprising:
Determine the radix of FFT according to the sampled point number of Fast Fourier Transform (FFT) FFT, and total progression M of FFT inter-stage conversion corresponding to described radix;
In order described sampled point is stored in the memory bank of the first set of memory banks, the number of described memory bank is the numerical value D of the Gao Ji in the radix of current definite FFT
Max
Between the first set of memory banks and the second set of memory banks, carry out the conversion of FFT inter-stage according to current definite radix, be specially:
When current progression m more than or equal to 1 and during less than M, move one, row according to row by logical block and move one cyclic shift mode by memory bank being stored in pending data in the memory bank of prime or intermediate data, be written in parallel to next stage
In the individual Different Logic piece, the span of described m is 1～M; The above-mentioned FFT inter-stage of circulation execution is converted into current progression m and equals M.
2. method according to claim 1 is characterized in that, during described execution FFT inter-stage conversion, will work as among the prime m
Individual logical block is divided, and logical block correspondence is divided into D logical block of next stage.
3. method according to claim 1 is characterized in that, the scope of described ring shift comprises:
The range of DO of row is the memory bank number in the set of memory banks;
The range of DO of row is the address number of each memory bank of comprising in each logical block at different levels.
4. method according to claim 1 is characterized in that, the mode of described ring shift data writing is: be shifted by memory bank first, be shifted by logical block, press afterwards the rear data writing of row displacement in the logical block.
5. method according to claim 1 is characterized in that, the mode of described ring shift data writing is: press first row displacement in the logical block, be shifted by logical block, afterwards by the memory bank rear data writing that is shifted.
6. the described method of any one is characterized in that according to claim 1～5, comprising:
When the sampling number of FFT was 4 or 8 integral number power, the radix of determining FFT was single base, and described single base is base 2, base 4 or base 8;
The data D of Gao Ji in the radix of current definite FFT
MaxEqual the numerical value of described single base;
Total progression M of the FFT inter-stage conversion that described single radix is corresponding is take the logarithm of single base as end sampling number.
7. the described method of any one is characterized in that according to claim 1～5, comprising:
When the sampling number of FFT was not 4 or 8 integral number power, the radix of determining FFT was mixed base, and described mixed base is the combination in any of base 2, base 4 or base 8;
The data D of Gao Ji in the radix of current definite FFT
MaxNumerical value for the Gao Ji in the mixed radix;
Total progression M of the FFT inter-stage conversion that described mixed base is corresponding is specially: will not be the product that the sampling number of 4 or 8 integral number power is decomposed into the integral number power numerical value of each single base in the mixed base;
Calculate progression corresponding to each described single base, the summation of obtaining the progression that each single base is corresponding in the described mixed base is total progression M;
When carrying out the conversion of FFT inter-stage, carry out the conversion of FFT inter-stage according to base 4 or base 8 first, afterbody is carried out the computing of base 2 or base 4.
8. the address mapping device of the Fast Fourier Transform (FFT) FFT of a parallel branch butterfly unit comprises main control unit, twiddle factor storer and external memory storage, it is characterized in that, also comprises:
Parallel branch butterfly unit group is used for the radix through the definite FFT of main control unit control, carries out the computing of FFT inter-stage;
The first internal repository group and the second internal repository group, when being used for storage and carrying out the conversion of FFT inter-stage, row move one, row by logical block and move pending data or the intermediate data that one cyclic shift mode is written in parallel to or reads by memory bank;
Address-generation unit is used for providing the address of reading when carrying out the conversion of FFT inter-stage to described twiddle factor storer, described external memory storage, described the first internal repository group and the second internal repository group.
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