CN111696870A - Double-sided fan-out packaging method and double-sided fan-out packaging structure - Google Patents

Double-sided fan-out packaging method and double-sided fan-out packaging structure Download PDF

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Publication number
CN111696870A
CN111696870A CN202010428904.XA CN202010428904A CN111696870A CN 111696870 A CN111696870 A CN 111696870A CN 202010428904 A CN202010428904 A CN 202010428904A CN 111696870 A CN111696870 A CN 111696870A
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nano metal
composite substrate
double
metal paste
layer
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杨斌
匡自亮
崔成强
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/03—Manufacturing methods
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

The invention discloses a double-sided fan-out packaging method, which comprises the following steps: s10, providing a composite substrate, and forming a through hole and a mounting groove in the composite substrate along the thickness direction of the composite substrate; s20, providing nano metal paste, filling the nano metal paste into the through hole and carrying out sintering treatment; s30, providing a chip, and sticking the chip with the front side facing upwards in the mounting groove through an adhesive layer; s40, respectively manufacturing an electric connection structure on the two sides of the composite substrate to electrically lead out the I/O port of the chip through the sintered nano metal paste; the composite substrate is prepared by mixing and hot-pressing graphene, metal powder and an adhesive. The double-sided fan-out packaging method can be used for manufacturing the double-sided fan-out packaging structure with good heat dissipation effect, and can simplify the process and reduce the cost.

Description

Double-sided fan-out packaging method and double-sided fan-out packaging structure
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a double-sided fan-out packaging method and a double-wire fan-out packaging structure.
Background
With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has gradually become the mainstream of new generation of electronic products. Different packaging technologies have great differences in manufacturing processes and technologies, and play a crucial role in the performance of the chip after packaging. With the development of packaging technology and technology, chips are developed in the direction of higher density, faster speed, smaller size, lower cost, and the like.
In the existing chip packaging structure, most of chips are wrapped in an injection molding body, heat transmission is mainly carried out between metal connected with the chips and the outside, the normal work of the chips is seriously influenced due to limited heat dissipation capacity, and the energy consumption is increased. In the prior art, polymer epoxy resin is mostly adopted as a plastic package material, the resin has poor heat dissipation performance, a chip mainly dissipates heat through metal particles added in the resin, the metal particles are selected for better heat dissipation to account for a higher resin material, so that the problems of high stress residue and the like are caused, and a method adopting the high-heat-conductivity plastic package material is also adopted to improve the heat dissipation effect, but the cost is higher.
Disclosure of Invention
The invention aims to provide a double-sided fan-out packaging method, which can be used for manufacturing a double-sided fan-out packaging structure with a good heat dissipation effect, and can simplify the process and reduce the cost.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, the invention provides a double-sided fan-out packaging method, which comprises the following steps:
s10, providing a composite substrate, and forming a through hole and a mounting groove in the composite substrate along the thickness direction of the composite substrate; the composite substrate is provided with a plurality of mounting grooves, wherein the two sides of the composite substrate adjacent to each mounting groove are respectively provided with a through hole, of course, the through holes can be only arranged on one side of the composite substrate adjacent to the mounting grooves, and the mounting grooves are used for mounting chips, so that the size of the mounting grooves is slightly larger than that of the chips;
s20, providing a nano metal paste, filling the nano metal into the through hole and carrying out sintering treatment, so that the nano metal paste is fixed in the through hole of the composite substrate to play a role in conducting electricity;
s30, providing a chip, and sticking the chip with the front side facing upwards in the mounting groove through an adhesive layer;
s40, respectively manufacturing electric connection structures on two sides of the composite substrate, wherein one side of the electric connection structure is simultaneously contacted with one end of the nano metal paste and the I/O port of the chip, and the other side of the electric connection structure is contacted with the other end of the nano metal paste, so that the I/O port of the chip is electrically led out through the sintered nano metal paste;
the composite substrate is prepared by mixing and hot-pressing graphene, metal powder and an adhesive.
According to the invention, the composite substrate prepared by mixing and hot-pressing graphene, metal powder and an adhesive is used as a carrier plate of the chip, and the chip is attached in the mounting groove formed in the composite substrate, so that the heat dissipation effect of the chip can be effectively enhanced, and meanwhile, the composite substrate has a good electrical insulation effect and effectively prevents the short circuit of the chip; the nano metal paste is embedded into the through hole in a filling mode and is sintered and fixed to form an electric connection structure for electrically connecting two sides, heat generated in the sintering and fixing process of the nano metal paste can be quickly dissipated through the composite substrate, deformation of the composite substrate caused by thermal stress concentration is prevented, compared with traditional electroplating or direct insertion of a conductive block, the process is simpler, the production cost is reduced, and meanwhile good electric connectivity is guaranteed.
Preferably, the composite substrate is prepared from 50-75 wt.% of graphene, 20-35 wt.% of metal powder and 5-30 wt.% of adhesive.
Preferably, the metal powder is nano metal powder selected from any one of copper, gold and aluminum. Any one of copper, gold and aluminum nano metal powder is uniformly dispersed in graphene and the adhesive, and the composite substrate with good heat conduction performance and good electrical insulation performance for the chip can be prepared after hot pressing. Specifically, the adhesive is prepared by mixing any one or at least two of thermosetting resin, silicate and phosphate with a curing agent and a reinforcing agent. Specifically, the thermosetting resin includes any one of epoxy resin, phenol resin, urea resin, and urethane.
Further, the temperature of the hot pressing treatment is 200-500 ℃, the time is 30-300 s, and the graphene, the metal powder and the adhesive which are uniformly mixed are subjected to hot pressing treatment under the condition, so that the composite substrate with excellent performance can be prepared.
In the invention, the aperture of the through hole for filling the nano metal paste is 1-1000 μm, and the aperture size and the hole density can be designed according to actual conditions such as the density of an I/O port of a chip.
In the invention, the nano metal paste comprises nano metal powder, an antioxidant, a soldering flux, a stabilizer and an active agent. Wherein the nano metal powder comprises nano copper powder, nano silver powder and the like; the antioxidant is glycol, polyethylene glycol or imidazole compound; the soldering flux is rosin or derivatives thereof; the stabilizer is one or more of imidazole compounds and derivatives thereof, polyvinylpyrrolidone (PVP), organic vinyl polymers, polymers synthesized by organic alkene and organic alcohol, organic ketone, organic acid, ammonium, cetyl ammonium bromide (CTAB), Sodium Dodecyl Benzene Sulfonate (SDBS), Sodium Dodecyl Sulfate (SDS), polyethylene glycol and organic polymers containing hydroxyl and carboxyl; the active agent mainly comprises one or more of hydrochloric acid, zinc chloride, ammonium chloride, lactic acid, citric acid, stearic acid, sodium stearate, non-activated rosin and activated rosin.
Wherein, the nano metal paste comprises the following components:
Figure BDA0002499765660000021
Figure BDA0002499765660000031
further, firstly, the nano metal powder is subjected to ultrasonic cleaning treatment: ultrasonic washing with ethanol for 1-3 min, ultrasonic washing with acid for 3-5 min, and ultrasonic washing with water for 1-3 min; and then mixing the nano metal powder subjected to ultrasonic cleaning with the antioxidant, the soldering flux, the stabilizer and the activator to prepare the nano metal paste. Firstly, ultrasonically cleaning with ethanol for 1-3 min to remove oil and other impurities on the surface of the nano metal powder, then ultrasonically cleaning with acid for 3-5 min to remove oxides on the surface of the nano metal powder, and finally ultrasonically cleaning with water to improve the heat-conducting property of the composite substrate.
The method comprises the steps of uniformly mixing nano metal powder, an antioxidant, a soldering flux, a stabilizer and an active agent to form a paste, filling the paste into the through holes, and then sintering at 180-300 ℃ and 0.1-5 atmospheric pressures for 1-10 min to fix the sintered nano metal paste in the through holes, so that the electric connection structure on two sides can be well conducted.
Further, step S40 specifically includes the following steps:
s40a, manufacturing a first dielectric layer covering the chip on one side of the composite substrate where the chip is installed, and opening a hole in the first dielectric layer to expose an I/O port of the chip and one end of the nano metal paste; specifically, the first dielectric layer is punched by laser, so that an I/O port of a chip and one end of the nano metal paste can be exposed, and then scraps generated in the punching process are removed by cleaning treatment;
s40b, sequentially manufacturing a first seed layer and a first rewiring layer on the first dielectric layer; specifically, a first seed layer is firstly manufactured on the surfaces of a first dielectric layer and holes thereof through vacuum sputtering, then a dry film is covered on the first seed layer, a copper plated layer is manufactured through exposure, development and copper plating, after film stripping treatment, part of the first seed layer is removed through a differential etching method, and a first rewiring layer is formed, wherein the manufacturing method of the first seed layer and the first rewiring layer is conventional in the field and is not described in detail;
s40c, manufacturing a first solder mask layer on the first rewiring layer, and opening holes in the first solder mask layer to expose a pad area of the first rewiring layer; specifically, covering photosensitive ink above the first redistribution layer, and carrying out exposure, development and curing treatment to expose a pad area of the first redistribution layer for implanting metal bumps such as solder balls and the like so as to electrically lead out an I/O port of the chip to one surface of the composite substrate;
s40d, manufacturing a second dielectric layer on the other side of the composite substrate, which is far away from the chip, and opening a hole in the second dielectric layer to expose the other end of the nano metal paste; specifically, the second dielectric layer is punched by laser, so that the other end of the nano metal paste can be exposed, and then scraps generated in the punching process are removed by cleaning treatment;
s40e, sequentially manufacturing a second seed layer and a second rewiring layer on the second dielectric layer; the manufacturing method of the second seed layer may be the same as that of the first seed layer, and the manufacturing method of the first redistribution layer may be the same as that of the second redistribution layer, which is not described in detail;
s40f, manufacturing a second solder mask layer on the second rewiring layer, and opening holes in the second solder mask layer to expose the pad area of the second rewiring layer; this step is similar to step S40c described above and will not be described in detail.
Preferably, the first dielectric layer and the second dielectric layer in the invention are both solid PI, LCP and ABF films, wherein the first dielectric layer is fixed on the composite substrate by vacuum hot pressing and is filled in the gap between the chip and the mounting groove.
On the other hand, the invention also provides a double-sided fan-out packaging structure which is manufactured by adopting the double-sided fan-out packaging method, and the composite substrate in the double-sided fan-out packaging structure enables a chip to have a good heat dissipation effect.
The invention has the beneficial effects that: according to the invention, the composite substrate prepared by mixing the graphene and the metal powder through the adhesive and then carrying out hot pressing is adopted, so that the heat dissipation effect of the chip can be effectively enhanced; the nano metal paste filled in the through hole of the composite substrate is fixed in the through hole after sintering, so that the process is simplified, the production cost is reduced, and good electrical connection can be ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a flow diagram of a double-sided fan-out packaging method according to the present invention.
Fig. 2 is a detailed flowchart of step S40 in the double-sided fan-out packaging method according to the present invention.
Fig. 3 is a schematic cross-sectional view of a composite substrate according to embodiment 1 of the present invention after filling a nano metal paste in a via hole.
Fig. 4 is a schematic cross-sectional view of a composite substrate after a chip is mounted in a mounting groove according to embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional view of the first dielectric layer after being mounted according to embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional view of the first seed layer after being fabricated according to embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional view of the first seed layer after a dry film is attached thereon according to embodiment 1 of the present invention.
Fig. 8 is a schematic cross-sectional view of a dry film on a first seed layer after exposure and development according to example 1 of the present invention.
Fig. 9 is a schematic cross-sectional view of the first redistribution layer after being fabricated according to embodiment 1 of the present invention.
Fig. 10 is a schematic sectional view after a first solder resist layer is formed according to embodiment 1 of the present invention.
Fig. 11 is a schematic cross-sectional view of the composite substrate of embodiment 1 after a second dielectric layer is mounted and opened on the other side of the composite substrate.
Fig. 12 is a schematic cross-sectional view of a second seed layer after being fabricated according to embodiment 1 of the present invention.
Fig. 13 is a schematic cross-sectional view of a dry film attached to a second seed layer after exposure and development in example 1 of the present invention.
Fig. 14 is a schematic cross-sectional view of the second redistribution layer after being fabricated according to embodiment 1 of the present invention.
Fig. 15 is a schematic sectional view after a first solder resist layer is formed according to embodiment 1 of the present invention.
In the figure:
1. a composite substrate; 2. nano metal paste; 3. a chip; 4. a first dielectric layer; 5. a first seed layer; 6. a first rewiring layer; 7. a first solder resist layer; 8. a second dielectric layer; 9. a second seed layer; 10. a second rewiring layer; 11. and a second solder resist layer.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 1, the present invention provides a double-sided fan-out packaging method, including the following steps:
s10, providing a composite substrate prepared by mixing and hot-pressing graphene, metal powder and an adhesive, and forming a through hole and an installation groove in the composite substrate along the thickness direction of the composite substrate;
the composite substrate is provided with a plurality of mounting grooves, wherein the two sides of the composite substrate adjacent to each mounting groove are respectively provided with a through hole, of course, the through holes can be only arranged on one side of the composite substrate adjacent to the mounting grooves, and the mounting grooves are used for mounting chips, so that the size of the mounting grooves is slightly larger than that of the chips;
s20, providing a nano metal paste, filling the nano metal into the through hole and carrying out sintering treatment, so that the nano metal paste is fixed in the through hole of the composite substrate to play a role in conducting electricity;
s30, providing a chip, and sticking the chip with the front side facing upwards in the mounting groove through an adhesive layer;
and S40, respectively manufacturing electric connection structures on the two sides of the composite substrate, wherein one side of the electric connection structure is simultaneously contacted with one end of the nano metal paste and the I/O port of the chip, and the other side of the electric connection structure is contacted with the other end of the nano metal paste, so that the I/O port of the chip is electrically led out through the sintered nano metal paste.
As shown in fig. 2, step S40 specifically includes the following steps:
s40a, manufacturing a first dielectric layer covering the chip on one side of the composite substrate where the chip is installed, and opening a hole in the first dielectric layer to expose an I/O port of the chip and one end of the nano metal paste;
s40b, sequentially manufacturing a first seed layer and a first rewiring layer on the first dielectric layer;
s40c, manufacturing a first solder mask layer on the first rewiring layer, and opening holes in the first solder mask layer to expose a pad area of the first rewiring layer;
s40d, manufacturing a second dielectric layer on the other side of the composite substrate, which is far away from the chip, and opening a hole in the second dielectric layer to expose the other end of the nano metal paste;
s40e, sequentially manufacturing a second seed layer and a second rewiring layer on the second dielectric layer;
s40f, manufacturing a second solder mask layer on the second rewiring layer, and opening holes in the second solder mask layer to expose the pad area of the second rewiring layer.
The double-sided fan-out packaging method of the present invention is specifically explained and illustrated in detail by the following examples.
Example 1
The double-sided fan-out packaging method of the embodiment comprises the following steps:
s1, preparing the composite substrate 1: mixing 50 wt.% of graphene, 35 wt.% of nano copper powder and 15 wt.% of adhesive, and hot-pressing at 220 ℃ for 270s to obtain a composite substrate 1;
preparing a nano metal paste 2: ultrasonic cleaning is carried out on the nano metal powder for 1-3 min by adopting ethanol, 3-5 min by adopting acid ultrasonic cleaning and 1-3 min by adopting water ultrasonic cleaning in sequence, and 85 wt.% of nano metal powder (after cleaning), 8 wt.% of antioxidant, 3 wt.% of soldering flux, 4 wt.% of stabilizer and activator are mixed to prepare nano metal paste 2;
s2, referring to fig. 3 and 4, forming a plurality of through holes and mounting grooves on the composite substrate 1, filling the nano metal paste 2 in the through holes and sintering at 200 ℃ and 4 atmospheres for 3min, and then attaching the chip 3 to the bottom of the mounting groove by bonding glue;
s3, referring to fig. 5, fabricating a first dielectric layer 4 covering the chip 3 on the side of the composite substrate 1 where the chip 3 is mounted, and performing a vacuum thermocompression process and a hole opening process on the first dielectric layer 4 to expose the I/O port of the chip 3 and one end of the nano metal paste 2;
s4, referring to fig. 6 to 9, firstly, a first seed layer 5 is formed on the surface of the first dielectric layer 4 and the holes thereof by vacuum sputtering, then a dry film is covered on the first seed layer 5, a copper plated layer is formed by exposure, development and copper plating, after the film removing process, a part of the first seed layer 5 is removed by a differential etching method, and a first redistribution layer 6 is formed;
s5, referring to fig. 10, fabricating a first solder mask layer 7 on the first redistribution layer 6, and opening a hole in the first solder mask layer 7 to expose a pad region of the first redistribution layer 6;
s6, referring to fig. 11, fabricating a second dielectric layer 8 on the other side of the composite substrate 1, and opening the second dielectric layer 8 to expose the other end of the nano metal paste 2;
s7, referring to fig. 12 to 14, firstly, a second seed layer 9 is formed on the surfaces of the second dielectric layer 8 and the holes thereof by vacuum sputtering, then a dry film is covered on the second seed layer 9, a copper plated layer is formed by exposure, development and copper plating, after the film removing process, a part of the second seed layer 9 is removed by a differential etching method, and a second redistribution layer 10 is formed;
s8, referring to fig. 15, fabricating a second solder resist layer 11 on the second redistribution layer 10, and opening the second solder resist layer 11 to expose the pad region of the second redistribution layer 10;
s9, respectively implanting solder balls in the pad areas on the two sides of the composite substrate 1 to complete double-sided fan-out packaging;
and S10, cutting the double-sided fan-out packaging structure to obtain an independent packaging unit.
Example 2
The double-sided fan-out packaging method of the present embodiment is substantially the same as that of embodiment 1 described above, except that step S1 and step S2:
s1, preparing a composite substrate: mixing 65 wt.% of graphene, 25 wt.% of nano copper powder and 10 wt.% of adhesive, and hot-pressing at 280 ℃ for 60s to obtain a composite substrate;
preparing a nano metal paste: ultrasonic cleaning is carried out on the nano metal powder for 1-3 min by adopting ethanol, 3-5 min by adopting acid ultrasonic cleaning and 1-3 min by adopting water ultrasonic cleaning in sequence, and 90 wt.% of nano metal powder (after cleaning), 3 wt.% of antioxidant, 5 wt.% of soldering flux, 2 wt.% of stabilizer and activator are mixed to prepare nano metal paste;
and S2, forming a plurality of through holes and mounting grooves on the composite substrate, filling the nano metal into the through holes, and sintering for 8min at 250 ℃ and 2 atmospheric pressures.
Example 3
The double-sided fan-out packaging method of the present embodiment is substantially the same as that of embodiment 1 described above, except that step S1 and step S2:
s1, preparing a composite substrate: mixing 68 wt.% of graphene, 20 wt.% of nano copper powder and 12 wt.% of adhesive, and hot-pressing at 220 ℃ for 270s to obtain a composite substrate;
preparing a nano metal paste: ultrasonic cleaning is carried out on the nano metal powder for 1-3 min by adopting ethanol, ultrasonic cleaning is carried out for 3-5 min by adopting acid and ultrasonic cleaning is carried out for 1-3 min by adopting water, and 88 wt.% of nano metal powder (after cleaning), 6 wt.% of antioxidant, 3 wt.% of soldering flux, 1 wt.% of stabilizer and activator are mixed to prepare nano metal paste;
and S2, forming a plurality of through holes and mounting grooves on the composite substrate, filling the nano metal into the through holes, and sintering at 250 ℃ and 2 atmospheric pressures for 5 min.
The chip in the double-sided fan-out package structure manufactured in the above embodiments 1 to 3 has a good heat dissipation effect, can ensure rapid heat release, and can ensure good electrical connection of the electrical connection structures on both sides of the composite substrate after the nano metal paste filled in the through holes of the composite substrate is sintered and fixed.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (10)

1. A double-sided fan-out packaging method is characterized by comprising the following steps:
s10, providing a composite substrate, and forming a through hole and a mounting groove in the composite substrate along the thickness direction of the composite substrate;
s20, providing nano metal paste, filling the nano metal paste into the through hole and carrying out sintering treatment;
s30, providing a chip, and sticking the chip with the front side facing upwards in the mounting groove through an adhesive layer;
s40, respectively manufacturing an electric connection structure on the two sides of the composite substrate so as to lead out the I/O port of the chip electrically through the sintered nano metal paste;
the composite substrate is prepared by mixing and hot-pressing graphene, metal powder and an adhesive.
2. The double-sided fan-out packaging method of claim 1, wherein the composite substrate is made of 50-75 wt.% graphene, 20-35 wt.% metal powder, and 5-30 wt.% adhesive.
3. The double-sided fan-out packaging method according to claim 1, wherein the temperature of the hot pressing treatment is 200-500 ℃ and the time is 30-300 s.
4. The double-sided fan-out packaging method according to claim 1, wherein the aperture of the through hole is 1-1000 μm.
5. The dual sided fan out packaging method of claim 1, in which the nano metal paste comprises nano metal powder, an antioxidant, a flux, a stabilizer, and an active agent.
6. The dual sided fan out packaging method of claim 5, in which the nano metal paste comprises the following components:
Figure FDA0002499765650000011
7. the dual sided fan out packaging method of claim 6, in which the nano metal powder is subjected to an ultrasonic cleaning process: ultrasonic washing with ethanol for 1-3 min, ultrasonic washing with acid for 3-5 min, and ultrasonic washing with water for 1-3 min; and then mixing the nano metal powder subjected to ultrasonic cleaning with the antioxidant, the soldering flux, the stabilizer and the activator to prepare the nano metal paste.
8. The double-sided fan-out packaging method according to claim 1, wherein after the nano metal paste is filled in the through hole, the nano metal paste is sintered for 1-10 min at 180-300 ℃ and 0.1-5 atmospheric pressures, so that the sintered nano metal paste is fixed in the through hole.
9. The double-sided fan-out packaging method of claim 1, wherein step S40 specifically includes the steps of:
s40a, manufacturing a first dielectric layer covering the chip on one side of the composite substrate where the chip is installed, and opening a hole in the first dielectric layer to expose an I/O port of the chip and one end of the nano metal paste;
s40b, sequentially manufacturing a first seed layer and a first rewiring layer on the first dielectric layer;
s40c, manufacturing a first solder mask layer on the first rewiring layer, and opening holes in the first solder mask layer to expose a pad area of the first rewiring layer;
s40d, manufacturing a second dielectric layer on the other side of the composite substrate, which is far away from the chip, and opening a hole in the second dielectric layer to expose the other end of the nano metal paste;
s40e, sequentially manufacturing a second seed layer and a second rewiring layer on the second dielectric layer;
s40f, manufacturing a second solder mask layer on the second rewiring layer, and opening holes in the second solder mask layer to expose the pad area of the second rewiring layer.
10. A double sided fan out package structure made using the double sided fan out packaging method of any of claims 1 to 9.
CN202010428904.XA 2020-05-20 2020-05-20 Double-sided fan-out packaging method and double-sided fan-out packaging structure Pending CN111696870A (en)

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CN102480908A (en) * 2010-11-25 2012-05-30 光宏精密股份有限公司 Moulded interconnect device with heat conduction property and manufacturing method thereof
CN105575913A (en) * 2016-02-23 2016-05-11 华天科技（昆山）电子有限公司 Fan-out type 3D packaging structure embedded in silicon substrate
CN105895538A (en) * 2016-04-28 2016-08-24 合肥祖安投资合伙企业(有限合伙) Manufacture method for chip packaging structure and chip packaging structure
CN108550566A (en) * 2018-04-12 2018-09-18 中国工程物理研究院电子工程研究所 The three-dimensional stacked interconnection structure of SiC device based on nano mattisolda and preparation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102480908A (en) * 2010-11-25 2012-05-30 光宏精密股份有限公司 Moulded interconnect device with heat conduction property and manufacturing method thereof
CN105575913A (en) * 2016-02-23 2016-05-11 华天科技（昆山）电子有限公司 Fan-out type 3D packaging structure embedded in silicon substrate
CN105895538A (en) * 2016-04-28 2016-08-24 合肥祖安投资合伙企业(有限合伙) Manufacture method for chip packaging structure and chip packaging structure
CN108550566A (en) * 2018-04-12 2018-09-18 中国工程物理研究院电子工程研究所 The three-dimensional stacked interconnection structure of SiC device based on nano mattisolda and preparation method

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