CN220569634U

CN220569634U - High heat conduction embedded structure

Info

Publication number: CN220569634U
Application number: CN202322013767.5U
Authority: CN
Inventors: 陈先明; 黄高; 洪业杰; 黄本霞
Original assignee: Nantong Yueya Semiconductor Co ltd
Current assignee: Nantong Yueya Semiconductor Co ltd
Priority date: 2023-07-28
Filing date: 2023-07-28
Publication date: 2024-03-08
Anticipated expiration: 2033-07-28

Abstract

The utility model discloses a high-heat-conductivity embedded structure, and relates to the technical field of packaging structures. The high-heat-conductivity embedded structure comprises a core layer, a first circuit layer, a second conducting column, an insulating layer, a second circuit layer, a third conducting column, a first chip, a second chip, a first medium layer and a third circuit layer; the first circuit layer is arranged on the upper surface and the lower surface of the core layer, and the second conducting column is arranged on the surface of the first circuit layer; the insulating layers are arranged on the upper surface and the lower surface of the core layer; the second circuit layer is arranged on the surface of the insulating layer; the third conducting column is arranged on the surface of the second circuit layer; the first chip is arranged on the insulating layer on the upper surface of the core layer; the second chip is arranged on a second circuit layer on the surface of the insulating layer on the lower surface of the core layer; the first dielectric layer is arranged on the surface of the insulating layer; the third circuit layer is arranged on the surface of the first dielectric layer. According to the embedded structure with high heat conductivity, disclosed by the embodiment of the utility model, embedded packaging and electric connection of multiple chips can be realized, and the heat dissipation performance of the embedded structure can be ensured.

Description

High heat conduction embedded structure

Technical Field

The utility model relates to the technical field of packaging structures, in particular to a high-heat-conductivity embedded structure.

Background

With the increasing development of electronic technology, the performance requirements of electronic products are higher and higher, so that the electronic components and the circuit board substrate circuit are more and more complex; meanwhile, the electronic products are required to be smaller and thinner in size; therefore, the electronic element packaging substrate such as a chip has a certain trend towards high-density integration, miniaturization and multifunction.

In order to realize the multifunction, high performance and miniaturization of electronic products, how to embed and package active and passive elements such as chips in a substrate with high efficiency and low cost is an important research direction in the semiconductor packaging industry at present. Meanwhile, the application of electronic components is also moving toward high frequency, high speed and high power, resulting in a rapid increase of heat flux density per unit area. The speed of the electronic element is reduced along with the increase of the temperature of the operation environment, and the loss is increased along with the increase of the temperature; moreover, the reliability of the electronic product is relatively lowered by long-term operation under a high-temperature environment. Therefore, if the heat generated by the high-frequency high-speed high-power electronic element cannot be timely dissipated, the performance and the reliability of the electronic product can be affected to a certain extent. Therefore, under the large trend of high frequency, high speed and high power, how to reasonably optimize the design of the embedded package substrate and the package body and improve the heat dissipation performance of the embedded package structure is an important subject at present.

Disclosure of Invention

The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, the utility model provides the embedded structure with high heat conductivity, which can improve the heat dissipation performance of the embedded structure while improving the packaging integration level.

According to an embodiment of the utility model, a high thermal conductivity embedded structure comprises:

the inner part of the core layer is provided with a first conducting column longitudinally penetrating through the core layer;

the first circuit layer is arranged on the upper surface and the lower surface of the core layer, is communicated with the first conducting column and comprises a first radiating block;

the second conducting column is arranged on the surface of the first circuit layer; the second conduction column comprises a second heat dissipation block, and the second heat dissipation block is positioned on the first heat dissipation block;

the insulating layer is arranged on the upper surface and the lower surface of the core layer, the insulating layer covers the first circuit layer and the second conducting column, and the surface of the insulating layer is flush with the surface of the second conducting column;

the second circuit layer is arranged on the surface of the insulating layer and is communicated with the second conducting column;

the third conducting column is arranged on the surface of the second circuit layer;

the first chip is arranged on the surface of the insulating layer on the upper surface of the core layer and is positioned on the second radiating block;

the second chip is arranged on the second circuit layer on the surface of the insulating layer on the lower surface of the core layer;

the first dielectric layer is arranged on the surface of the insulating layer, covers the third conducting column, the first chip and the second chip, and is flush with the surface of the third conducting column;

the third circuit layer is arranged on the surface of the first dielectric layer, the third circuit layer is communicated with the third conducting column, and the third circuit layer is communicated with the first chip and the second chip through blind holes in the first dielectric layer.

According to some embodiments of the utility model, the high thermal conductivity embedded structure further comprises:

the fourth conducting column is arranged on the surface of the third circuit layer;

the second dielectric layer is arranged on the surface of the first dielectric layer and covers the third circuit layer and the fourth conducting column;

the fourth line layer is arranged on the surface of the second dielectric layer; the fourth circuit layer is communicated with the fourth conducting column.

According to some embodiments of the utility model, the fourth conductive pillar includes a plurality of first copper pillars and a plurality of second copper pillars, the second copper pillars having a size larger than the first copper pillars, the second copper pillars being for high current carrying capacity conduction.

the solder mask layer is arranged on the surface of the first dielectric layer, and a window is formed in the position, corresponding to the third circuit layer, of the solder mask layer;

and the bonding pad is arranged in the window.

According to some embodiments of the utility model, the first surface of the first chip is fixed on the second heat dissipation block by a core material, and the second surface of the first chip is provided with a first connection terminal.

According to some embodiments of the utility model, the second chip is provided with second connection terminals on both sides; or, the second chip includes a first combined chip and a second combined chip that are stacked, a first surface of the first combined chip is provided with a third connection terminal, the third connection terminal is fixed on the surface of the second circuit layer through a solder ball, a first surface of the second combined chip is disposed on a second surface of the first combined chip, and a second surface of the second combined chip is provided with a fourth connection terminal.

According to some embodiments of the utility model, the third conductive pillars include a plurality of third copper pillars and a plurality of fourth copper pillars, the fourth copper pillars having a size larger than the size of the third copper pillars, the fourth copper pillars being used for high current carrying capacity conduction.

According to some embodiments of the utility model, the core layer is a ceramic material.

According to some embodiments of the utility model, the insulating layer is PP prepreg.

According to some embodiments of the utility model, the first dielectric layer is made of epoxy molding compound.

The high-heat-conductivity embedded structure provided by the embodiment of the utility model has at least the following beneficial effects: the embedded packaging and the electric connection of the multi-chip and double-sided I/O chips can be realized, so that the packaging integration level is improved, and the embedded packaging cost of the chips is effectively reduced; meanwhile, through multidirectional heat dissipation schemes such as the first heat dissipation block, the second heat dissipation block and the like, high integration is achieved, meanwhile, heat dissipation performance of the embedded structure is guaranteed, and reliability of the embedded structure is improved.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a high thermal conductivity embedded structure according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of a high thermal conductivity embedded structure according to another embodiment of the present utility model;

FIG. 3 is a schematic structural diagram of a high thermal conductivity embedded structure according to another embodiment of the present utility model;

fig. 4 to fig. 9 are schematic structural diagrams corresponding to a manufacturing process of the high thermal conductivity embedded structure according to the embodiment of the utility model;

reference numerals:

the chip package includes a core layer 100, a first via post 110, a first circuit layer 200, a first heat sink 210, a second via post 300, a second heat sink 310, an insulating layer 400, a second circuit layer 500, a third via post 600, a third copper post 610, a fourth copper post 620, a first chip 700, a first connection terminal 710, a core-bonding material 720, a second chip 800, a first combined chip 810, a third connection terminal 811, a second combined chip 820, a fourth connection terminal 821, a solder ball 830, a first dielectric layer 900, a first through hole 910, a blind hole 920, a third circuit layer 1000, a second dielectric layer 1100, a fourth via post 1200, a first copper post 1210, a second copper post 1220, a fourth circuit layer 1300, a solder resist layer 1400, and a pad 1500.

Detailed Description

Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.

In the description of the present utility model, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present utility model and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present utility model.

The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Therefore, the embodiment of the utility model provides a high-heat-conductivity embedded structure, which can realize embedded packaging and electrical interconnection of a plurality of chips and double-sided I/O chips without prefabricating a frame, effectively reduces the embedded packaging cost of the chips, and can realize integrated packaging with higher density. In addition, through setting up the radiating block at the inside of packaging structure, can promote packaging structure's radiating effect, and then promote efficiency and reliability.

The following describes in detail the high thermal conductivity embedded structure according to the embodiment of the present utility model with reference to fig. 1 to 9.

As shown in fig. 1, a high thermal conductivity embedded structure according to an embodiment of the present utility model includes:

the core layer 100, the first conducting column 110 longitudinally penetrating through the core layer 100 is arranged in the core layer 100;

the first circuit layer 200 is disposed on the upper and lower surfaces of the core layer 100, the first circuit layer 200 is electrically connected to the first conductive via 110, and the first circuit layer 200 includes a first heat dissipating block 210;

the second conductive via 300 is disposed on the surface of the first circuit layer 200; the second conductive pillar 300 includes a second heat sink 310, where the second heat sink 310 is located on the first heat sink 210;

the insulating layer 400 is arranged on the upper surface and the lower surface of the core layer 100, the insulating layer 400 covers the first circuit layer 200 and the second conducting post 300, and the surface of the insulating layer 400 is flush with the surface of the second conducting post 300;

the second circuit layer 500 is disposed on the surface of the insulating layer 400, and the second circuit layer 500 is electrically connected to the second conductive via 300;

the third conductive via 600 is disposed on the surface of the second circuit layer 500;

the first chip 700 is disposed on the surface of the insulating layer 400 on the upper surface of the core layer 100, and the first chip 700 is located on the second heat dissipation block 310;

the second chip 800 is disposed on the second circuit layer 500 on the surface of the insulating layer 400 on the lower surface of the core layer 100;

the first dielectric layer 900 is disposed on the surface of the insulating layer 400, the first dielectric layer 900 covers the third conductive pillar 600, the first chip 700 and the second chip 800, and the surface of the first dielectric layer 900 is flush with the surface of the third conductive pillar 600;

the third circuit layer 1000 is disposed on the surface of the first dielectric layer 900, the third circuit layer 1000 is electrically connected to the third conductive via 600, and the third circuit layer 1000 is electrically connected to the first chip 700 and the second chip 800 through the blind hole 920 disposed in the first dielectric layer 900.

Specifically, referring to fig. 4 to 9, the high thermal conductivity embedded structure is manufactured by the following steps:

as shown in fig. 4, first, a core layer 100 is prepared, and then the core layer 100 is drilled by laser drilling or mechanical drilling to form a second through hole (not shown) longitudinally penetrating the core layer 100; then, the second via is electroplated to form the first via 110. As shown in fig. 2, the number of the first conductive pillars 110 is not limited, and may be determined according to practical needs, and the first conductive pillars 110 may be made of a conductive material such as copper. The upper and lower end surfaces of the first via post 110 are exposed to the surface of the core layer 100. In this example, the core layer 100 is made of a ceramic material, which has good rigidity and high thermal conductivity, and can improve the stability and heat dissipation performance of the entire embedded structure. It should be noted that, the core layer 100 may be made of other insulating materials with high thermal conductivity, but is not limited thereto.

Then, first circuit layers 200 are formed on the upper and lower surfaces of the core layer 100, first, metal seed layers are formed on the upper and lower surfaces of the core layer 100, photosensitive dry films are attached to the metal seed layers, circuit patterns are formed by exposing and developing, and then, the first circuit layers 200 are formed by electroplating according to the circuit patterns. The first circuit layer 200 on the upper and lower surfaces of the core layer 100 is conducted through the first conductive pillars 110 inside the core layer 100, and the end surfaces of the first conductive pillars 110 are flush with the surface of the chip 100. The first circuit layer 200 includes a heat dissipating surface with a larger area as the first heat dissipating block 210, so as to facilitate subsequent heat dissipation.

Then, a second conductive via 300 is formed on the surface of the first circuit layer 200; specifically, a pattern corresponding to the second conductive pillars 300 is also fabricated by means of film pasting, exposure and development, and then the second conductive pillars 300 are formed on the surface of the first circuit layer 200 by means of electroplating; finally, film stripping is performed, and the redundant metal seed layer on the surface of the core layer 100 is etched away. The number of the second conductive pillars 300 is also plural, and a conductive material such as copper may be used. The second conducting column 300 includes a second heat dissipating block 310 with an area larger than that of the other conducting columns 300, and the second heat dissipating block 310 is located on the first heat dissipating block 210, and the second heat dissipating block and the first heat dissipating block are matched with each other to promote the heat dissipation effect of the package structure. In this example, the first heat sink block 210 and the second heat sink block 310 are both located on the upper surface of the core layer 100; it should be noted that the first heat dissipation block 210 and the second heat dissipation block 310 may be disposed on the lower surface or both surfaces of the core layer 100.

Then, as shown in fig. 5, an insulating layer 400 is laminated on the upper and lower surfaces of the core layer 100, such that the insulating layer 400 covers the first circuit layer 200 and the second via 300. Among them, the insulating layer 400 is preferably an insulating material such as PP prepreg with high thermal conductivity. After the insulating layer 400 is pressed, the insulating layer 400 is thinned by adopting processes such as grinding, plasma etching and the like, so that the surface of the insulating layer 400 is flush with the end face of the second conducting post 300, and the end face of the second conducting post 300 is exposed; the insulating layer 400 serves as a dielectric layer of the package structure.

Then, a second circuit layer 500 is formed on the surface of the insulating layer 400; specifically, a metal seed layer is sputtered on the surface of the insulating layer 400, a photosensitive dry film is attached, exposure and development are carried out on the photosensitive dry film to form a pattern corresponding to the second circuit layer 500, and the second circuit layer 500 is formed according to pattern electroplating; the second wiring layer 500 contacts the end surface of the second conductive post 300, thereby achieving conduction.

Then, as shown in fig. 6, a third via post 600 is fabricated on the surface of the second circuit layer 500; specifically, a pattern corresponding to the third conductive via 600 is also fabricated by means of film pasting, exposure and development, and then the third conductive via 600 is formed on the surface of the second circuit layer 500 by means of electroplating; finally, film stripping is performed, and the redundant metal seed layer on the surface of the insulating layer 400 is etched away. The number of the third conductive via 600 is also plural, and a conductive material such as copper may be used. In the third conductive via 600, a plurality of third copper pillars 610 and a plurality of fourth copper pillars 620 are included, the size of the fourth copper pillars 620 is larger than the size of the third copper pillars 610, and the fourth copper pillars 620 are used for high-current-carrying capacity conduction. By selectively disposing the fourth copper pillars 620 with a large size in the third conductive pillars 600, the requirement of high current-carrying capacity conduction of a part of the circuit is satisfied, the loss is reduced, and the efficiency is further improved.

Then, as shown in fig. 7, the first chip 700 and the second chip 800 are mounted. Specifically, as shown in fig. 7, insulating layers 400 are disposed on the upper and lower surfaces of the core layer 100, and for the insulating layer 400 located above, the position of the second heat sink 310 is reserved for subsequent placement of the first chip 700 when the second circuit layer 500 is fabricated. When the first chip 700 is disposed on the surface of the second heat sink 310, the adhesive core material 720 may be disposed on the surface of the second heat sink 310, the first surface (i.e., the lower surface) of the first chip 700 is fixed on the second heat sink 310 through the adhesive core material 720, and the second surface (i.e., the upper surface) of the first chip 700 is provided with the first connection terminal 710. Through setting up first chip 700 on second heat dissipation piece 310, in the course of the operation of first chip 700, can dispel the heat fast through second heat dissipation piece 310, prevent that the high temperature from influencing the normal work of first chip 700.

The second chip 800 may be a single chip having double-sided I/O, i.e., both sides of the second chip 800 are provided with second connection terminals (not shown); alternatively, the second chip 800 may also take the form of a chipset. As shown in fig. 7, in this example, the second chip 800 is in the form of a chip set, the second chip 800 includes a first combined chip 810 and a second combined chip 820 which are stacked, a first face (i.e., an upper surface) of the first combined chip 810 is provided with a third connection terminal 811, the third connection terminal 811 is fixed to a surface of the second wiring layer 500 by a solder ball 830, the first face (i.e., an upper surface) of the second combined chip 820 is provided on a second face (i.e., a lower surface) of the first combined chip 810, and a second face (i.e., a lower surface) of the second combined chip 820 is provided with a fourth connection terminal 821. The first combined chip 810 and the second combined chip 820 may be fixed by a core material.

Through setting up first chip 700 in packaging structure's top, set up second chip 800 in packaging structure's below to can realize embedding encapsulation and the electrical interconnection of many chips, two-sided I/O chip, the chip of upper and lower side is through inside conduction post and circuit layer realization switch on, thereby can realize the integrated encapsulation of higher density, effectively reduce the chip embedding encapsulation cost.

Then, as shown in fig. 8, a first dielectric layer 900 is disposed on the surface of the insulating layer 400, so that the first dielectric layer 900 covers the third conductive pillars 600, the first chip 700, and the second chip 800. Specifically, after the first chip 700 and the second chip 800 are mounted, the first dielectric layer 900 is pressed at the upper side and the lower side, wherein the first dielectric layer 900 is preferably an epoxy Molding compound with high heat conduction property, and the upper structure and the lower structure are packaged by Molding. As shown in fig. 8 and 9, a first dielectric layer 900 is disposed on the surface of the insulating layer 400, after the first dielectric layer 900 covers the third conductive pillar 600, the first chip 700 and the second chip 800, the first dielectric layer 900 is thinned by using processes such as grinding, plasma etching, etc., so that the surface of the first dielectric layer 900 is flush with the surface of the third conductive pillar 600, thereby exposing the end surface of the third conductive pillar 600; then, the first dielectric layer 900 is drilled to form a first through hole 910 communicating with the first connection terminal 710 of the first chip 700 and the fourth connection terminal 821 of the second chip 800, so that subsequent electroplating of the first through hole 910 to form the blind hole 920 is facilitated.

Finally, as shown in fig. 1, a third circuit layer 1000 is disposed on the surface of the first dielectric layer 900, the third circuit layer 1000 is conducted with the third conductive pillar 600, and the third circuit layer 1000 is conducted with the connection terminals of the first chip 700 and the second chip 800 through the blind hole 920 disposed in the first dielectric layer 900. Specifically, a circuit pattern corresponding to the third circuit layer 1000 is fabricated on the surface of the first dielectric layer 900 by means of setting a metal seed layer, attaching a photosensitive dry film, exposing and developing, then electroplating is performed according to the circuit pattern, and in the electroplating process, blind holes 920 are formed in the first through holes 910 in an electroplating manner, so that the third circuit layer 1000 is conducted with the connection terminals of the first chip 700 and the second chip 800 through the blind holes 920 formed in the first dielectric layer 900, then film is removed, and redundant metal seed layers on the surface of the first dielectric layer 900 are etched, thereby completing the fabrication of the embedded packaging structure.

According to the high-heat-conductivity embedded structure provided by the embodiment of the utility model, embedded packaging and electric connection of multiple chips and double-sided I/O chips can be realized, so that the packaging integration level is improved, and the chip embedded packaging cost is effectively reduced; meanwhile, through multidirectional heat dissipation schemes such as the first heat dissipation block 210, the second heat dissipation block 310 and the like, high integration is realized, and meanwhile, the heat dissipation performance of the embedded structure is ensured, and the reliability of the embedded structure is improved; the large-size copper columns or copper blocks are selectively arranged, so that the requirement of high current-carrying capacity conduction of part of loops is met, loss is reduced, and efficiency is further improved; in addition, the manufacturing method can also shorten the technological process of chip embedding and packaging, shorten the processing period and reduce the processing cost.

Further, as shown in fig. 2, in practical application, build-up manufacturing may be performed according to the wiring requirement of the embedded package structure. As shown in fig. 2, in the present example, a fourth conductive pillar 1200 is disposed on the surface of the third line layer 1000, a second dielectric layer 1100 is disposed on the surface of the first dielectric layer 900, and the second dielectric layer 1100 covers the third line layer 1000 and the fourth conductive pillar 1200; the surface of the second dielectric layer 1100 is provided with a fourth circuit layer 1300; the fourth circuit layer 1300 is conductive to the fourth conductive pillar 1200. In this example, the build-up layer is formed only under the embedded package structure, and in practical applications, the build-up layer may be formed over or on both sides of the embedded package structure. The fourth conductive pillar 1200 includes a third copper pillar 1210 and a fourth copper pillar 1220, where the size of the fourth copper pillar 1220 is larger than that of the third copper pillar 1210, and the fourth copper pillar 1220 is used for high-current-carrying capacity conduction, so as to meet the requirement of high-current-carrying capacity conduction of part of the loop, reduce loss, and further improve efficiency.

Further, as shown in fig. 3, the high thermal conductivity embedded structure according to the embodiment of the present utility model further includes:

the solder mask 1400 is disposed on the surface of the first dielectric layer 900, and the solder mask 1400 has a window;

and a pad 1500 disposed in the window.

Specifically, as shown in fig. 3, since the first dielectric layer 900 below is further subjected to build-up, the upper solder mask 1400 is directly disposed on the surface of the first dielectric layer 900; for the lower solder mask 1400, the second dielectric layer 1100 is further disposed on the surface of the first dielectric layer 900, so that the lower solder mask 1400 is disposed on the surface of the second dielectric layer 1100, i.e. no matter how many dielectric layers are disposed on the embedded package structure, the solder mask 1400 is disposed on the surface of the dielectric layer on the outermost layer of the embedded package structure. Then, the solder resist layer 1400 is windowed to form a window corresponding to the third wiring layer 1000, and the window is subjected to metal surface treatment to form the pad 1500.

Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and/or processing capabilities described in connection with a particular device or component may be performed by any other device or component. In addition, while various exemplary implementations and architectures have been described in terms of embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

The embodiments of the present utility model have been described in detail with reference to the accompanying drawings, but the present utility model is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present utility model.

Claims

1. The utility model provides a high heat conduction embedment structure which characterized in that includes:

2. The high thermal conductivity embedded structure of claim 1, further comprising:

3. The high thermal conductivity embedded structure of claim 2, wherein the fourth conductive via comprises a plurality of first copper pillars and a plurality of second copper pillars, the second copper pillars having a size greater than the first copper pillars, the second copper pillars being configured for high current carrying capacity conduction.

4. The high thermal conductivity embedded structure of claim 1, further comprising:

and the bonding pad is arranged in the window.

5. The embedded structure of claim 1, wherein a first surface of the first chip is fixed to the second heat sink via a core material, and a second surface of the first chip is provided with a first connection terminal.

6. The embedded structure of claim 1, wherein the second chip is provided with second connection terminals on both sides; or, the second chip includes a first combined chip and a second combined chip that are stacked, a first surface of the first combined chip is provided with a third connection terminal, the third connection terminal is fixed on the surface of the second circuit layer through a solder ball, a first surface of the second combined chip is disposed on a second surface of the first combined chip, and a second surface of the second combined chip is provided with a fourth connection terminal.

7. The high thermal conductivity embedded structure of claim 1, wherein the third conductive pillars comprise a plurality of third copper pillars and a plurality of fourth copper pillars, the fourth copper pillars having a size greater than the size of the third copper pillars, the fourth copper pillars being for high current carrying capacity conduction.

8. The embedded structure of claim 1, wherein the core layer is made of a ceramic material.

9. The embedded structure of claim 1, wherein the insulating layer is PP prepreg.

10. The embedded structure of claim 1, wherein the first dielectric layer is an epoxy molding compound.