CN111694759A

CN111694759A - Flash memory management method and flash memory

Info

Publication number: CN111694759A
Application number: CN201910377863.3A
Authority: CN
Inventors: 邱日圣; 许智宏; 萧智伟; 陈昱维; 叶庭玮
Original assignee: Asolid Technology Co Ltd
Current assignee: Asolid Technology Co Ltd
Priority date: 2019-03-14
Filing date: 2019-05-06
Publication date: 2020-09-22
Anticipated expiration: 2039-05-06
Also published as: TWI776028B; CN111694759B; TW202034169A

Abstract

The disclosure provides a flash memory management method and a flash memory. The flash memory management method comprises the following steps: generating a plurality of partial page address mapping tables in a random access memory; and when a first partial page address mapping table of the partial page address mapping table is released, moving data stored in a second partial page address mapping table which is newly generated in the partial page address mapping table to the first partial page address mapping table.

Description

Flash memory management method and flash memory

Technical Field

The present disclosure relates to a flash memory management method and a flash memory, and more particularly, to a flash memory management method and a flash memory for improving a random writing performance.

Background

In performance evaluation of flash memory, the random write speed (or 4K random write speed) is an important evaluation index. In randomly writing data, the flash memory controller must continuously generate a page mapping table and perform an operation of writing the page mapping table to the flash memory or reading the page mapping table from the flash memory to the random access memory. Frequent updates of the page mapping table cause a decrease in random writing speed.

Disclosure of Invention

The present disclosure provides a flash memory management method and a flash memory, which effectively prevent a speed of random writing from decreasing.

The present disclosure provides a flash memory management method, including: generating a plurality of partial page address mapping tables in a random access memory; and when a first partial page address mapping table of the partial page address mapping table is released, moving data stored in a second partial page address mapping table which is newly generated in the partial page address mapping table to the first partial page address mapping table.

The present disclosure proposes a flash memory, comprising: the memory unit module comprises a plurality of entity memory groups, and each entity memory group comprises a plurality of entity memory pages; and the controller is coupled with the storage unit module. The controller generates a plurality of partial page address mapping tables in the random access memory; and when a first partial page address mapping table of the partial page address mapping table is released, moving data stored in a second partial page address mapping table which is newly generated in the partial page address mapping table to the first partial page address mapping table.

Based on the above, the flash memory management method and the flash memory of the present disclosure will move the data stored in the second part of the page address mapping table that is generated newly to the first part of the page address mapping table when the first part of the page address mapping table of the random access memory is released. Therefore, the speed of the random writing of the flash memory can be effectively prevented from being reduced.

In order to make the aforementioned and other features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a block diagram of a flash memory according to an embodiment of the present disclosure.

Fig. 2A to 2D are schematic diagrams illustrating a flash memory management method according to an embodiment of the disclosure.

FIG. 3 is a diagram illustrating a partial page address mapping table according to an embodiment of the present disclosure.

FIG. 4 is a flowchart illustrating a method for managing a flash memory according to an embodiment of the disclosure.

[ notation ] to show

100: flash memory

110: controller

120: memory cell module

200: partial page address mapping table queue

201: indicator symbol

211. 212, 300: partial page address mapping table

SE 1-SE 4: column-setting column

301: mapping physical memory set

302: mapping physical page addresses

303: mapping segments

S401 and S402: method for managing flash memory

Detailed Description

Referring to fig. 1, a flash memory 100 according to an embodiment of the present disclosure includes a controller 110 and a memory cell module 120 coupled to the controller 110. The controller 110 may perform management operations with respect to the memory cell module 120. The memory unit module 120 includes a plurality of physical banks (or called physical blocks). Each physical memory set includes a plurality of physical memory pages (or called physical pages, physical pages). Each physical memory page includes a plurality of segments (or segments), each of which is, for example, 4 kbytes in size.

Referring to fig. 2A and fig. 1, fig. 2A shows an example of a Partial Page address Mapping Table (PPMT) queue 200 stored in a random access memory of the flash memory 100. The PPMT queue 200 may include PPMT groups 0 through M. Each PPMT group may include page 0 through page N, and each page may store one PPMT data. In the initial state where none of the pages of the respective PPMT group have stored PPMT data, the indicator 201 would refer to the address of page 0 of PPMT group 0. It should be noted that in the full page address mapping, one logical page is mapped to one physical page; in partial page address mapping, however, a logical page may map to segments of multiple different physical pages.

Referring to FIG. 2B and FIG. 1, after performing multiple random write operations (e.g., 4K random write operations), PPMTs are sequentially built in the PPMT queue 200. For example, page 0 to page N of PPMT group 0 and page 1 of PPMT group 1 store the PPMTs that can be used by the controller 110, that is, the controller 110 can obtain the logical-physical mapping relationship of the partial page address mapping according to the PPMTs (i.e., page 0 to page N of PPMT group 0 and PPMT of page 0 and page 1 of PPMT group 1 are in the first state). After the PPMT is established, the indicator 201 refers to the address of page 2 of the PPMT group 1 to indicate the address of the next PPMT to be established.

Referring to fig. 2C and fig. 1, when the partial page address mapping table (PPMT)211 (also referred to as a first partial page address mapping table) is released by the controller 110 (i.e., the contents of the PPMT211 are cleared), the controller 110 does not move the data of the PPMT211 to the release queue, but moves the mapping data stored in the newly generated partial page address mapping table (PPMT)212 (also referred to as a second partial page address mapping table) to the PPMT 211.

Referring to fig. 2D and fig. 1, after the data stored in the PPMT 212 is moved to the PPMT211, the controller 110 points the indicator 201 to the address of the page 1 of the PPMT group 1, and sets the PPMT of the page 1 of the PPMT group 1 to the second state, in which the controller 110 cannot obtain the logical-physical mapping relationship according to the PPMT of the page 1 of the PPMT group 1.

By the above method of PPMT rearrangement, the number of updates of PPMT can be effectively reduced and the access operations of PPMT between the RAM and the memory unit module 120 can be reduced.

Referring to fig. 3, a partial page address mapping table 300 according to an embodiment of the present disclosure includes section fields SE1 to SE 4. Each segment includes a record mapping entity page address, a mapping segment, and a mapping entity memory set. Taking the segment SE1 as an example, the mapped physical memory set 301 recorded in the segment SE1 is the physical memory set B₁The mapped physical page address 302 recorded in the section field SE1 is P₁(i.e., physical memory set B₁P of (A) to₁Page) and the mapping section 303 recorded in the section field SE1 is S₁(i.e., physical memory set B₁P of (A) to₁S th of page₁Segmented data). Through the recorded contents of the section fields SE1 to SE4, the data in the logical page address corresponding to the partial page address mapping table 300 can be known and stored in: physical memory set B₁P in (1)₁S th of page₁Segmented, physical memory set B₂P in (1)₂S th of page₂Segmented, physical memory set B₃P in (1)₃S th of page₃Segment and physical memory set B₄P in (1)₄S th of page₄And (5) segmenting. Although the above embodiments illustrate the partial page address mapping table 300 as including four section fields, the disclosure is not limited thereto. In another embodiment, the partial page address mapping table 300 may also include eight or other number of section fields.

Referring to FIG. 4, in step S401, a plurality of partial page address mapping tables are generated in the RAM.

In step S402, when the first partial page address mapping table of the partial page address mapping tables is released, data stored in the second partial page address mapping table newly generated in the partial page address mapping tables is moved to the first partial page address mapping table.

In summary, the flash memory management method and the flash memory of the present disclosure move the data stored in the second part of the page address mapping table that is generated newly to the first part of the page address mapping table when the first part of the page address mapping table of the random access memory is released. By reforming the partial page address mapping table by the flash memory management method disclosed by the invention, the updating times of the partial page address mapping table can be greatly reduced, namely, the times of reading the partial page address mapping table from the flash memory to the random access memory and writing the partial page address mapping table into the flash memory from the random access memory. In addition, the flash memory management method of the present disclosure does not require the use of a release queue. Therefore, the speed of the random writing of the flash memory can be effectively prevented from being reduced.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.

Claims

1. A method for flash memory management, comprising:

generating a plurality of partial page address mapping tables in a random access memory; and

when a first partial page address mapping table of the plurality of partial page address mapping tables is released, data stored in a second partial page address mapping table which is newly generated in the plurality of partial page address mapping tables is moved to the first partial page address mapping table.

2. The flash memory management method of claim 1, further comprising: data of the first partial page address mapping table is not moved to a release queue.

3. The method of claim 1, wherein each of the partial page address mapping tables includes a plurality of segment fields, each of the segment fields including a mapped physical page address, a mapped segment, and a mapped physical memory bank.

4. The flash memory management method of claim 1, wherein the first partial page address mapping table is in a first state, wherein in the first state a controller can obtain logical entity mapping relationships from the first partial page address mapping table.

5. The flash memory management method of claim 4, further comprising: setting the second partial page address mapping table to a second state in which the controller cannot obtain the logical entity mapping relationship according to the second partial page address mapping table.

6. A flash memory, comprising:

the memory unit module comprises a plurality of entity memory groups, and each entity memory group comprises a plurality of entity memory pages; and

a controller coupled to the memory cell module, wherein the controller generates a plurality of partial page address mapping tables in a random access memory; and

7. The flash memory of claim 6, wherein the controller does not move data of the first portion of the page address mapping table to a release queue.

8. The flash memory of claim 6 wherein each of the partial page address mapping tables includes a plurality of segment fields, each of the segment fields including a mapped physical page address, a mapped segment, and a mapped physical memory bank.

9. The flash memory of claim 6, wherein the first partial page address mapping table is in a first state, wherein in the first state the controller can obtain logical entity mapping relationships from the first partial page address mapping table.

10. The flash memory of claim 9, wherein the controller sets the second partial page address mapping table to a second state, wherein in the second state the controller cannot obtain the logical entity mapping relationship from the second partial page address mapping table.