CN111668093A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN111668093A CN111668093A CN201910172297.2A CN201910172297A CN111668093A CN 111668093 A CN111668093 A CN 111668093A CN 201910172297 A CN201910172297 A CN 201910172297A CN 111668093 A CN111668093 A CN 111668093A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
A semiconductor device and a method of forming the same, the method comprising: providing a substrate; forming a first mask layer on the surface of the substrate, wherein the first mask layer is internally provided with a first opening and a second opening; forming a second mask layer on the first mask layer, wherein the first opening and the second opening are filled with the second mask layer; doping first doping ions in part of the second mask layer in the first opening to form a first split doped mask layer, wherein the first split doped mask layer penetrates through the first opening along a first direction; doping second doping ions in part of the second mask layer in the second opening to form a second split doped mask layer, wherein the second split doped mask layer penetrates through the second opening along the first direction; after the first division doping mask layer and the second division doping mask layer are formed, etching to remove the second mask layer; and after the second mask layer is removed, the substrate is etched by taking the first split doped mask layer, the second split doped mask layer and the first mask layer as masks. The method improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous progress of semiconductor technology, semiconductor devices are being developed toward higher element density and higher integration. Line width is one of the main parameters of semiconductor devices, and reducing line width can improve integration and reduce the size of semiconductor devices.
When the line width shrinks below the limit of the photolithography process, a Double Patterning Technique (DPT) is used to reduce the line width. The double patterning technique is to divide a set of high-density circuit patterns into two or more sets of circuit patterns with lower density, and then print the circuit patterns onto a target wafer. There are many different methods for realizing double pattern exposure, but the basic steps are printing half of the pattern, developing and etching; then spin coating a layer of photoresist again, printing the other half of the pattern, and finally finishing the whole photoetching process by utilizing a hard mask or selective etching.
However, when fabricating small-linewidth metal layers, the ability of the photolithography process results in metal layer edge shrink (Line-end short). The smaller the line width, the more severe the metal layer edge shrinkage. The conventional method is to perform Optical Proximity Correction (OPC) on the photomask to correct the metal layer shrinkage. When the metal layer shrinks too severely, the correction amount of the required optical proximity effect correction is too large, so that the patterns of two adjacent metal layers on the photomask are overlapped, and the optical proximity effect correction method fails. In this case, a Line-end cut process (Line-end cut) has to be added. The cutting process is to cut off two adjacent overlapped metal layers by utilizing the metal layer cutting photoetching and metal layer cutting etching processes added by the cutting mask after lines of the overlapped metal layers are formed.
However, the performance of the semiconductor device formed by the existing process is still poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including: providing a substrate; forming a first mask layer on the surface of a substrate, wherein the first mask layer is internally provided with first openings and second openings which are arranged at intervals along a first direction; forming a second mask layer on the first mask layer, wherein the first opening and the second opening are filled with the second mask layer; doping first doping ions in part of the second mask layer in the first opening to form a first split doped mask layer, wherein the first split doped mask layer penetrates through the first opening along a first direction; doping second doping ions in part of the second mask layer in the second opening to form a second split doped mask layer, wherein the second split doped mask layer penetrates through the second opening along the first direction; after the first division doping mask layer and the second division doping mask layer are formed, etching to remove the second mask layer; and after the second mask layer is removed, the substrate is etched by taking the first split doped mask layer, the second split doped mask layer and the first mask layer as masks.
Optionally, the material of the second mask layer includes: polysilicon, silicon dioxide, silicon nitride, titanium oxide, or titanium nitride.
Optionally, the first doping ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, indium ions, or thallium ions.
Optionally, the second doping ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, indium ions, or thallium ions.
Optionally, after the first split doped mask layer is formed, a second split doped mask layer is formed.
Optionally, after forming the second split doped mask layer, forming the first split doped mask layer.
Optionally, the method for first dividing the doped mask layer includes: forming a first blocking layer on the surface of the second mask layer, wherein the first blocking layer is internally provided with a first blocking opening, and the first blocking opening exposes the surface of the second mask layer in part of the first opening; performing first ion implantation on the second mask layer by taking the first barrier layer as a mask to form a first split doped mask layer; and removing the first barrier layer after the first division mask doping layer is formed.
Optionally, the method for second division of the doped mask layer includes: forming a second barrier layer on the surface of the second mask layer, wherein the second barrier layer is internally provided with a second barrier opening, and the second barrier opening exposes the surface of the second mask layer in part of the second opening; performing second ion implantation on the second mask layer by taking the second barrier layer as a mask to form a second split doped mask layer; and removing the second barrier layer after forming the second division mask doping layer.
Optionally, the first doping ion and the second doping ion are the same.
Optionally, the process of removing the second mask layer by etching has a first etching rate for the second mask layer, and has a second etching rate for the first division-doped mask layer and the second division-doped mask layer, and a ratio of the first etching rate to the second etching rate is 5-20.
Optionally, the width of the first split doped mask layer along the second direction is 20nm to 66 nm.
Optionally, the width of the second split doped mask layer along the second direction is 20nm to 66 nm.
Optionally, the substrate includes a plurality of discrete first regions, a plurality of discrete second regions, and a peripheral region, the first regions and the second regions are arranged at intervals along the first direction, the adjacent first regions and second regions are adjacent to each other, and the peripheral region surrounds the first regions and the second regions; the first mask layer covers the substrate surfaces of the first area, the second area and the peripheral area.
Optionally, the forming method of the first mask layer includes: forming an initial first mask layer on the first area, the second area and the peripheral area substrate; a first layer on the surface of the initial first mask layer; forming a first patterned layer on the first layer surface, the first patterned layer exposing the first layer surface over a first region; etching the first layer by taking the first patterning layer as a mask, and forming a first groove in the first layer, wherein the first groove exposes the surface of the initial first mask layer on the first region; after the first groove is formed, removing the first patterning layer; after the first patterning layer is removed, forming a second patterning layer on the surface of the first layer, wherein the first layer on the second area is exposed out of the second patterning layer; etching the first layer by taking the second patterning layer as a mask to form a second groove, wherein the second groove exposes the surface of the initial first mask layer on the second region; after the second groove is formed, removing the second patterned layer; and after the second patterning layer is removed, etching the initial first mask layer exposed by the first groove and the second groove by taking the first layer as a mask to form a first mask layer, wherein the first mask layer is internally provided with a first opening and a second opening.
Optionally, the method further includes: after the first patterning layer is removed and before a second patterning layer is formed, forming a side wall mask layer on the side wall of the first groove, wherein the side wall mask layer is positioned on the surface of the initial first mask layer; after the first patterning layer is removed, forming a second patterning layer on the surfaces of the first layer and the side wall mask layer, wherein the first layer and part of the side wall mask layer on the second region are exposed by the second patterning layer; after the second patterning layer is removed, etching the first groove and the initial first mask layer exposed by the second groove by taking the first layer and the side wall mask layer as masks to form a first mask layer; the second mask layer covers the side wall mask layer.
Optionally, the material of the first layer comprises: polysilicon, silicon dioxide, silicon nitride, titanium oxide, or titanium nitride.
Optionally, the material of the side wall mask layer includes: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
Optionally, the method for forming the side wall mask layer includes: forming an initial side wall mask layer on the side wall and the bottom of the first groove and the surface of the first layer; and etching the initial side wall mask layer until part of the bottom surface of the first groove is exposed, and forming a side wall mask layer on the side wall of the first groove.
Optionally, the method further includes: after the second mask layer is removed, etching the substrate by taking the first division doping mask layer, the second division doping mask layer and the first mask layer as masks, and forming a first groove and a second groove in the substrate, wherein the first groove is positioned in a first region of the substrate, the first grooves are respectively positioned at two sides of the first division doping mask layer along the second direction, the second grooves are positioned in a second region of the substrate, and the second grooves are respectively positioned at two sides of the second division mask layer along the second direction; after the first groove and the second groove are formed, removing the first division doping mask layer, the second division doping mask layer and the first mask layer; removing the first split doped mask layer, the second split doped mask layer and the first mask layer, and then forming a first interconnection layer in the first groove; and forming a second interconnection layer in the second groove, wherein the first interconnection layer and the second interconnection layer are separated.
The invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor device provided by the technical scheme of the invention, the first division doping mask layer is formed in the first opening through the ion implantation process, so that the materials of the first division doping mask layer and the second mask layer are different, and after the second mask layer is removed, the first opening is divided by the first division doping mask layer along the second direction. Similarly, the second split doping mask layer splits the second opening along the second direction. The first division mask layer and the second division doping mask layer are formed by adopting ion implantation, the size of the ion implantation mask is smaller, the first division doping mask layer and the second division doping mask layer formed by the ion implantation mask are smaller in size perpendicular to the first direction, so that the distance between the adjacent first grooves in the first direction is smaller, the distance between the adjacent second grooves in the first direction is smaller, the areas of the first grooves and the second grooves are relatively larger under the condition that the areas of the bottoms of the first openings and the second openings are not changed, the areas of the subsequently formed first interconnection layer and the second interconnection layer are also larger, the resistances of the first interconnection layer and the second interconnection layer are smaller, and the performance of the semiconductor device is improved.
Further, a side wall mask layer is formed on the side wall of the first groove, the side wall mask layer and the first layer are used as masks, a first opening and a second opening are formed in the initial first mask layer, and the first opening and the second opening are isolated by the initial first mask layer at the bottom of the side wall mask layer. The side wall mask layer is formed on the side wall of the first groove, so that the exposed area of the first groove is reduced, and the size of the formed first opening is smaller. I.e. the lithographic opening of the first patterned layer is smaller in the case of larger, smaller size first openings are realized. Meanwhile, since the side wall of the first groove is formed with the side wall mask layer, in the process of forming the second groove, the opening of the second patterning layer for forming the second groove can be larger, part of the surface of the side wall mask layer is exposed, the side wall mask layer is different from the first layer in material, and in the process of removing the first layer of the second area, even if the side wall mask layer is exposed, the side wall mask layer cannot be removed, so that the second groove with smaller size can be formed under the condition of photoetching opening of the larger second patterning layer, and the second opening with smaller size is formed subsequently. Therefore, the first mask layer of the smaller first opening and second opening can be formed with a smaller size in the case of the larger photolithography openings of the first patterning layer and the second patterning layer.
Drawings
Fig. 1 to 7 are schematic structural views of a semiconductor device formation process;
fig. 8 to 29 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the prior art semiconductor devices is poor.
Fig. 1 to 7 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1 and 2, fig. 1 is a top view of a semiconductor device, fig. 2 is a cross-sectional view of a cutting line a-a1 in fig. 1, providing a substrate 100, the substrate 100 comprising a plurality of discrete first regions a01, a plurality of discrete second regions a02, the first regions a01 and the second regions a02 being arranged at intervals along a first direction X, adjacent first regions a01 and second regions a02 being contiguous; forming a first preliminary mask layer 111 on the first and second regions a01 and a02 of the substrate 100; a second initial mask layer 110 is formed on the surface of the first initial mask layer 111.
Referring to fig. 3, a portion of the second preliminary mask layer 110 on the first region a01 is removed, and a first groove 101 is formed in the second preliminary mask layer 110.
Referring to fig. 4, the second preliminary mask layer 110 on a portion of the second region a02 is removed, and a second division groove 102 is formed in the second preliminary mask layer 110, the second division groove 102 dividing the second preliminary mask layer 110 of the second region a02 in a second direction, the second direction being perpendicular to the first direction.
Referring to fig. 5, after forming the second dividing groove 102, a mask sidewall 120 is formed on the sidewall of the first groove 101, and a filling mask layer 130 is formed in the second dividing groove 102 during the process of forming the mask sidewall 120.
Referring to fig. 6, after the filling mask layer 130 and the mask sidewall spacers 120 are formed, a first division mask layer 140 is formed in the first groove 101, and the first division mask layer 140 divides the first groove 101 in the second direction.
Referring to fig. 7, after the first division mask layer 140 is formed, the second initial mask layer 110 filling the second region a02 on both sides of the mask layer 130 is removed to form a second groove; after the second grooves are formed, the first division mask layer 140, the filling mask layer 130, the mask sidewall spacers 120 and the second initial mask layer 110 are used as masks to etch the first initial mask layer 111, and first main grooves and second main grooves are formed in the first initial mask layer 111.
Since the second division groove 102 is formed by the photolithography process and the etching process, even though the latest photolithography technique is used, the dimension of the second division groove 102 in the second direction is still large, so that the formed filling mask layer 130 is also large in the second direction. Meanwhile, the first division mask layer 140 is also formed by a photolithography process and an etching process, and the size of the first division mask layer 140 along the second direction is also large. Under the condition that the areas of the first region and the second region are fixed, the sizes of the first groove and the second groove are relatively small, the sizes of the corresponding first main groove and the second main groove are also small, the shapes of the first main groove and the second main groove are transferred into the substrate subsequently, the sizes of the first interconnection layer and the second interconnection layer formed in the substrate are also small, and the resistances of the first interconnection layer and the second interconnection layer are large, so that the performance of the semiconductor device is poor.
In the invention, a first mask layer is formed on a substrate, and a first opening and a second opening are formed in the first mask layer; forming a second mask layer on the first mask layer; and respectively forming a first division doping mask layer and a second division doping mask layer in the first opening and the second opening, wherein the first division doping mask layer and the second division doping mask layer are formed by ion implantation of the second mask layer, the second mask layer is removed, the first division doping mask layer and the second division doping mask layer are reserved, and the first division doping mask layer and the second division doping mask layer formed by ion implantation have smaller sizes along the second direction. And then, taking the first division doping mask layer, the second division doping mask layer and the first mask layer as masks, and forming a first groove and a second groove in the substrate, wherein the areas of the first groove and the second groove are relatively larger, so that the sizes of the subsequently formed first interconnection layer and the second interconnection layer are larger, the resistances of the first interconnection layer and the second interconnection layer are smaller, and the method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 8 to 29 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 8, fig. 8 is a top view of a semiconductor device, providing a substrate 200.
The substrate 200 includes a plurality of discrete first regions a1, a plurality of discrete second regions a2, and a peripheral region B, the first regions a1 and the second regions a2 being spaced apart along a first direction, adjacent first regions a1 and second regions a2 being contiguous, the peripheral region B surrounding the first regions a1 and the second regions a 2.
The plurality of first regions a1 are arranged along the first direction X, and the plurality of second regions a2 are arranged along the first direction X.
The first and second zones a1 and a2 arranged at intervals in the first direction X mean that: only one second region a2 is provided between the adjacent first regions a1, and only one first region a1 is provided between the adjacent second regions a 2.
In the present embodiment, three first zones a1 and two second zones a2 are exemplified. In other embodiments, other values may be selected for the number of first and second zones.
In other embodiments, the number of first zones and second zones is equal.
In this embodiment, the substrate 200 includes: the etching device comprises a substrate and a layer to be etched, wherein the layer to be etched is positioned on the surface of the substrate.
The substrate may be single crystal silicon, polycrystalline silicon, or silicon germanium in an amorphous structure, may be silicon-on-insulator (SOI), and may include other materials (e.g., iii-v compounds such as gallium arsenide).
The material of the layer to be etched comprises: silicon oxide or low-K dielectric material (K3.9 or less).
Then, forming a first mask layer on the surface of the substrate 200, wherein the first mask layer is provided with first openings and second openings, and the first openings and the second openings are arranged at intervals along a first direction; please refer to fig. 9 to 17 for a method of forming the first opening and the second opening.
Referring to fig. 9 and 10, fig. 9 is a schematic view based on fig. 8, and fig. 10 is a cross-sectional view of a cutting line M-N in fig. 9; an initial first mask layer 201 is formed on the substrate 200.
The initial first mask layer 201 covers the surface of the substrate 200 in the first region a1, the second region a2, and the peripheral region B. (FIG. 9)
The material of the initial first mask layer 201 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
The materials selected for the initial first mask layer 201 all belong to hard mask materials.
In this embodiment, before forming the initial first mask layer 201, the method further includes: and forming an etching stop layer on the surface of the substrate.
The material of the etching stop layer comprises: silicon oxide, silicon nitride, or silicon oxynitride.
The etching stop layer protects the substrate when the initial first mask layer is etched.
In this embodiment, the material of the initial first mask layer 201 is silicon oxide. The etching stop layer is made of silicon nitride.
Then, a first layer 202 is arranged on the surface of the initial first mask layer 201; forming a first patterned layer 203 on the surface of the first layer 202, the first patterned layer 203 exposing the surface of the first layer 202 over a first area a 1; the first patterned layer 203 is used as a mask to etch the first layer 202, a first groove 204 is formed in the first layer 202, and the first groove 204 exposes the surface of the initial first mask layer 201 on the first region a 1.
The first layer 202 provides a mask layer for a subsequent formation of a first mask layer.
The material of the first layer 202 includes: polysilicon, silicon dioxide, silicon nitride, titanium oxide, or titanium nitride.
In this embodiment, the material of the first layer 202 is polysilicon.
The material of the first layer 202 is different from that of the initial first mask layer 201, so that loss of the first layer 202 can be reduced when the initial first mask layer 201 is etched, and the stability of pattern transfer is high in the process of transferring the pattern in the first layer 202 to the initial first mask layer 201.
The material of the first patterned layer 203 includes one or more of photoresist or bottom anti-reflective coating.
In this embodiment, the material of the first patterning layer 203 is a photoresist.
After the first groove 204 is formed, the method further includes: the first patterned layer 203 is removed.
The process of removing the first patterned layer 203 is an ashing process.
Referring to fig. 11 and 12, fig. 11 is a schematic view based on fig. 9, and fig. 12 is a cross-sectional view of a cutting line M-N in fig. 11; after the first groove 204 is formed, a side wall mask layer 210 is formed on the side wall of the first groove 204, and the side wall mask layer 210 is located on the surface of the initial first mask layer 201.
The sidewall mask layer 210 is subsequently used as a mask layer together with the first layer 202 to form a first opening of the first mask layer, which can reduce the size of the subsequently formed first opening.
The material of the sidewall mask layer 210 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
The method for forming the sidewall mask layer 210 includes: forming an initial sidewall mask layer (not shown) on the sidewalls and bottom of the first recess 204 and the surface of the first layer 202; the initial sidewall mask layer is etched back until a portion of the bottom surface of the first groove 204 and the top surface of the first layer 202 are exposed, and a sidewall mask layer 210 is formed on the sidewall of the first groove 204.
The process for forming the initial side wall mask layer comprises the following steps: one or more of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The material of the side wall mask layer 210 is different from the material of the initial first mask layer 201, and the material of the side wall mask layer 210 is different from the first layer 202.
In this embodiment, the sidewall mask layer 210 is made of silicon nitride.
In an embodiment, the sidewall mask layer is not formed.
Referring to fig. 13 and 14, fig. 14 is a cross-sectional view of a cutting line M-N in fig. 13; after forming the sidewall mask layer 210, a second patterned layer 205 is formed on the surface of the first layer 202, and the first layer 202 on the second region a2 is exposed by the second patterned layer 205.
The second patterned layer 205 is a mask layer when forming the second groove.
The material of the second patterned layer 205 includes: one or more of a photoresist or a bottom antireflective coating.
In this embodiment, the material of the second patterned layer 205 is photoresist.
The second patterned layer 205 fills the first recess 204.
Referring to fig. 15 and 16, fig. 16 is a cross-sectional view of a cutting line M-N in fig. 15; the second patterned layer 205 is used as a mask to etch and remove the first layer 202 in the second region a2, and a second groove 206 is formed in the first layer 202, wherein the second groove 206 exposes the surface of the initial first mask layer 201 in the second region a 2.
The process of etching away the first layer 202 on the second region a2 includes a dry etching process.
In this embodiment, the first layer 202 and the sidewall mask layer 210 expose a portion of the surface of the initial first mask layer 201 in the first region a1, and also expose the surface of the initial first mask layer 201 in the second region a 2.
After forming the second recess 206, the second patterned layer 205 is removed.
The process of removing the second patterned layer 205 includes an ashing process.
The ashing process is simple to remove the second patterned layer 205.
Referring to fig. 17, the cross-sectional directions of fig. 17 and fig. 16 are the same; after removing the second patterning layer 205, the first mask layer 201 exposed by the first groove 204 and the second groove 206 is etched by using the first layer 202 as a mask, so as to form a first mask layer 231, wherein the first mask layer 231 has a first opening 221 and a second opening 222 therein.
The first opening 221 exposes a portion of the surface of the first region A1 of the substrate 200, and the second opening 222 exposes the surface of the second region A2 of the substrate 200.
In this embodiment, after removing the second patterned layer 205, the initial first mask layer 201 is etched by using the first layer 202 and the sidewall mask layer 210 as masks, so as to form a first mask layer 231.
The first mask layer 231 provides a mask layer for the subsequent etching of the substrate 200.
The first mask layer 231 is formed after the initial first mask layer 201 is etched, so that the material of the first mask layer 231 is the same as that of the initial first mask layer 201.
The first opening 221 defines the location and shape of the subsequently formed first slot and the second opening 222 defines the location and shape of the subsequently formed second slot.
The process of etching the initial first mask layer 201 exposed by the first recess 204 and the second recess 206 includes a dry etching process.
It should be noted that, the bottom surface portion of the first groove 204 is covered by the sidewall mask layer 210, so that the exposed area of the first groove 204 is smaller, and the size of the formed first opening 221 is smaller. I.e. the lithographic opening of the first patterned layer is smaller when larger, a smaller size of the first opening 221 is achieved. Since the sidewall mask layer 210 is formed on the sidewall of the first recess 204, during the formation of the second recess 206, the opening of the second patterned layer 205 for forming the second recess 206 may be larger, exposing a portion of the surface of the sidewall mask layer 210, and the material of the sidewall mask layer 210 is different from that of the first layer 202, and during the removal of the first layer 202 in the second region a2, even if the sidewall mask layer 210 is exposed, the second recess 206 with a smaller size is formed, and the second opening 222 with a smaller size is formed subsequently. Therefore, the first mask layer 231 can be formed with a smaller first opening 221 and second opening 222 with a smaller photolithography opening of the larger first patterning layer and second patterning layer.
Referring to fig. 18, the cross-sectional directions of fig. 18 and 17 are the same; a second mask layer 211 is formed on the first mask layer 231, and the first opening 221 and the second opening 222 are filled with the second mask layer 211.
The material of the second mask layer 211 includes: polysilicon, silicon dioxide, silicon nitride, titanium oxide, or titanium nitride.
In this embodiment, before forming the second mask layer 211, the method further includes: the first layer 202 is removed.
In other implementations, the first layer may not be removed, and the second mask layer 211 covers the surface of the first layer.
The first layer 202 is removed to ensure that the second mask layer 211 formed subsequently can fill the first opening 221 and the second opening 222.
In this embodiment, the second mask layer 211 is made of polysilicon.
In this embodiment, the second mask layer 211 covers the sidewall mask layer 210, and the second mask layer 211 fills the first groove 204 and the second groove 206.
Referring to fig. 19 and 20, fig. 20 is a cross-sectional view of a cutting line M-N in fig. 19; after forming the second mask layer 211, implanting first doping ions into a portion of the second mask layer 211 in the first opening 221 to form a first divisional doping mask layer 230, wherein the first divisional doping mask layer 230 crosses the surface of the substrate 200 in the first opening 221 along a first direction X, and the first divisional doping mask layer 230 divides the second mask layer 211 in the first opening 221 along a second direction perpendicular to the first direction X.
The method of the first divisional doped mask layer 230 includes: forming a first barrier layer 207 on the surface of the second mask layer 211, wherein the first barrier layer 207 has a first barrier opening therein, and the first barrier opening exposes a portion of the surface of the second mask layer 211 in the first opening 221; with the first blocking layer 207 as a mask, a first ion implantation is performed on the second mask layer 211 to form a first split doped mask layer 230.
The width of the first division-doped mask layer 230 along the second direction is 20nm to 66 nm.
The first division doping mask layer 230 has first doping ions therein.
The first dopant ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, indium ions, or thallium ions.
The first division doping mask layer 230 is formed by doping the second mask layer 211 with first doping ions, and the first doping ions enter into ion gaps of the second mask layer, so that the doped second mask layer is stable in state.
The material of the first barrier layer comprises: photoresist or bottom antireflective coating.
In this embodiment, the method further includes: after the first division mask doping layer 230 is formed, the first blocking layer 207 is removed.
Referring to FIGS. 21 and 22, FIG. 22 is a cross-sectional view taken along line M1-N1 of FIG. 21; second doping ions are implanted into a portion of the second mask layer 211 in the second opening 222 to form a second split doped mask layer 240, the second split doped mask layer 240 crosses the surface of the substrate 200 in the second opening 222 along the first direction X, and the second split doped mask layer 240 splits the second mask layer 211 in the second opening 222 along the second direction.
The method for dividing the doped mask layer 240 includes: forming a second blocking layer 208 on the surface of the second mask layer 211, wherein a second blocking opening is formed in the second blocking layer 208, and the second blocking opening exposes a part of the surface of the second mask layer 211 in the second opening 222; and performing second ion implantation on the second mask layer 211 by using the second blocking layer 208 as a mask to form a second split doped mask layer 240.
The width of the second division doping mask layer 240 along the second direction is 20nm to 66 nm.
The second split doping mask layer 240 has second doping ions therein.
The second dopant ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, indium ions, or thallium ions.
In this embodiment, the first doping ions and the second doping ions are the same, and the first doping ions and the second doping ions are boron ions.
In one embodiment, the first doping ion and the second doping ion are different.
In this embodiment, the method further includes: after forming second division mask doped layer 240, second barrier layer 208 is removed.
In this embodiment, after the first split doped mask layer is formed, a second split doped mask layer is formed.
In one embodiment, the first split doped mask layer is formed after the second split doped mask layer is formed.
In other embodiments, the second split-doping mask layer is formed during the process of forming the first split-doping mask layer.
The first divisional doped mask layer 230 and the second divisional doped mask layer 240 are formed by ion implantation, so that as long as the sizes of the first blocking opening and the second blocking opening are small, the sizes of the first divisional doped mask layer 230 and the second divisional doped mask layer 240 along the second direction are both small, so that the distance between the subsequent adjacent first grooves in the second direction is small, the distance between the subsequent adjacent second grooves in the second direction is also small, and the areas of the first grooves and the second grooves are relatively large under the condition that the areas of the bottoms of the first opening 221 and the second opening 222 are not changed, so that the areas of the subsequently formed first interconnection layer and the second interconnection layer are relatively large, and the performance of the semiconductor device is improved.
Referring to fig. 23 to 25, fig. 24 is a cross-sectional view taken along line M1-N1 in fig. 23, and fig. 25 is a cross-sectional view taken along line M-N in fig. 23; after the first division doped mask layer 230 and the second division doped mask layer 240 are formed, the second mask layer 211 is etched and removed.
Specifically, the second mask layer 211 in the first area a1, the second area a2, and the peripheral area B is removed by etching, and the surface of the first mask layer 231 is exposed.
After the second mask layer 211 in the first area a1, the second area a2 and the peripheral area B is removed by etching, the first opening 211 is divided by the first division doping mask layer 230 along the second direction, and the second opening 222 is divided by the second division doping mask layer 240 along the second direction.
The process of removing the second mask layer 211 of the first area a1, the second area a2 and the peripheral area B by etching includes: a dry etching process or a wet etching process.
In this embodiment, the process of removing the second mask layer 211 in the first area a1, the second area a2, and the peripheral area B by etching is a wet etching process. The wet etching process comprises the following steps: the etching solution used includes: dilute hydrochloric acid and ammonia.
In the process of removing the second mask layer 211 in the first area a1, the second area a2 and the peripheral area B by etching, the second mask layer 211 for removing the first area a1, the second area a2 and the peripheral area B has a first etching rate, and the first divided doped mask layer 230 and the second divided doped mask layer 240 have a second etching rate, and the first etching rate is greater than the second etching rate.
In a specific embodiment, the ratio of the first etching rate to the second etching rate is 5-20.
The first etching rate is greater than the second etching rate, so that the second mask layer 211 in the first area a1, the second area a2 and the peripheral area B can be removed, and the consumption of the first divisional doped mask layer 230 and the second divisional doped mask layer 240 is low.
Referring to fig. 26 and 27, fig. 26 is the same as fig. 24 in cross-sectional direction, and fig. 27 is the same as fig. 25 in cross-sectional direction; after removing the second mask layer 211 in the first area a1, the second area a2 and the peripheral area B, etching the substrate 200 by using the first divided doped mask layer 230, the second divided doped mask layer 240 and the first mask layer 231 as masks, and forming a first groove 251 and a second groove 252 in the substrate 200, wherein the first groove 251 is located in the first area a1 of the substrate 200, the first groove 251 is located on two sides of the first divided doped mask layer 230 along the second direction, respectively, the second groove 252 is located in the second area a2 of the substrate 200, and the second groove 252 is located on two sides of the second divided doped mask layer 240 along the second direction, respectively.
In this embodiment, after removing the second mask layer 211 in the first area a1, the second area a2 and the peripheral area B, the substrate 200 is etched by using the first division-doping mask layer 230, the second division-doping mask layer 240, the sidewall mask layer 210 and the first mask layer 231 as masks, and a first trench 251 and a second trench 252 are formed in the substrate 200.
The first groove 251 provides a space for a first interconnect layer to be subsequently formed.
The second trench 252 provides space for a subsequently formed second interconnect layer.
The process of etching the substrate 200 includes: a dry etching process or a wet etching process.
In this embodiment, the process of etching the substrate 200 is a dry etching process.
Referring to fig. 28 and 29, fig. 28 is the same as fig. 26 in cross-sectional direction, and fig. 29 is the same as fig. 27 in cross-sectional direction; forming a first interconnection layer 261 in the first groove 251; a second interconnection layer 262 is formed in the second trench 252, and the first interconnection layer 261 and the second interconnection layer 262 are separated.
In this embodiment, the method further includes: before the first interconnection layer 261 and the second interconnection layer 262 are formed, the first division doped mask layer 230, the second division doped mask layer 240, the sidewall mask layer 210 and the first mask layer 231 are removed.
In this embodiment, in forming the first interconnect layer 261, the second interconnect layer 262 is formed.
The method for forming the first interconnection layer 261 and the second interconnection layer 262 includes: forming an interconnection material layer on the surface of the substrate 200, wherein the interconnection material layer fills the first groove 251 and the second groove 252; the interconnection material layer is planarized until the surface of the substrate 200 is exposed, a first interconnection layer 261 is formed in the first groove 251, and a second interconnection layer 262 is formed in the second groove 252.
The material of the interconnect material layer includes: a metallic material, the metallic material comprising: copper or cobalt.
In this embodiment, the material of the interconnect material layer is copper.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a first mask layer on the surface of a substrate, wherein the first mask layer is internally provided with first openings and second openings which are arranged at intervals along a first direction;
forming a second mask layer on the first mask layer, wherein the first opening and the second opening are filled with the second mask layer;
doping first doping ions in part of the second mask layer in the first opening to form a first split doped mask layer, wherein the first split doped mask layer penetrates through the first opening along a first direction;
doping second doping ions in part of the second mask layer in the second opening to form a second split doped mask layer, wherein the second split doped mask layer penetrates through the second opening along the first direction;
after the first division doping mask layer and the second division doping mask layer are formed, etching to remove the second mask layer;
and after the second mask layer is removed, the substrate is etched by taking the first split doped mask layer, the second split doped mask layer and the first mask layer as masks.
2. The method according to claim 1, wherein the material of the second mask layer comprises: polysilicon, silicon dioxide, silicon nitride, titanium oxide, or titanium nitride.
3. The method according to claim 1, wherein the first dopant ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, indium ions, or thallium ions.
4. The method according to claim 1, wherein the second dopant ions include: arsenic ions, boron ions, phosphorus ions, gallium ions, indium ions, or thallium ions.
5. The method of claim 1, wherein the second split-dopant mask layer is formed after the first split-dopant mask layer is formed.
6. The method of claim 1, wherein the first split-doping mask layer is formed after the second split-doping mask layer is formed.
7. The method for forming a semiconductor device according to claim 1, wherein the first division doping mask layer method comprises: forming a first blocking layer on the surface of the second mask layer, wherein the first blocking layer is internally provided with a first blocking opening, and the first blocking opening exposes the surface of the second mask layer in part of the first opening; performing first ion implantation on the second mask layer by taking the first barrier layer as a mask to form a first split doped mask layer; and removing the first barrier layer after the first division mask doping layer is formed.
8. The method for forming a semiconductor device according to claim 1, wherein the second division doping mask layer method comprises: forming a second barrier layer on the surface of the second mask layer, wherein the second barrier layer is internally provided with a second barrier opening, and the second barrier opening exposes the surface of the second mask layer in part of the second opening; performing second ion implantation on the second mask layer by taking the second barrier layer as a mask to form a second split doped mask layer; and removing the second barrier layer after forming the second division mask doping layer.
9. The method according to claim 1, wherein the first dopant ion and the second dopant ion are the same.
10. The method for forming the semiconductor device according to claim 9, wherein the process for removing the second mask layer by etching has a first etching rate for the second mask layer, and has a second etching rate for the first division-doped mask layer and the second division-doped mask layer, and a ratio of the first etching rate to the second etching rate is 5 to 20.
11. The method of claim 1, wherein the first split-doping mask layer has a width along the second direction of 20nm to 66 nm.
12. The method of claim 1, wherein the second split-doping mask layer has a width along the second direction of 20nm to 66 nm.
13. The method of claim 1, wherein the substrate comprises a plurality of discrete first regions, a plurality of discrete second regions, and a peripheral region, the first and second regions being spaced apart along the first direction, adjacent first and second regions being contiguous, the peripheral region surrounding the first and second regions; the first mask layer covers the substrate surfaces of the first area, the second area and the peripheral area.
14. The method for forming a semiconductor device according to claim 13, wherein the method for forming the first mask layer includes: forming an initial first mask layer on the first area, the second area and the peripheral area substrate; a first layer on the surface of the initial first mask layer; forming a first patterned layer on the first layer surface, the first patterned layer exposing the first layer surface over a first region; etching the first layer by taking the first patterning layer as a mask, and forming a first groove in the first layer, wherein the first groove exposes the surface of the initial first mask layer on the first region; after the first groove is formed, removing the first patterning layer; after the first patterning layer is removed, forming a second patterning layer on the surface of the first layer, wherein the first layer on the second area is exposed out of the second patterning layer; etching the first layer by taking the second patterning layer as a mask to form a second groove, wherein the second groove exposes the surface of the initial first mask layer on the second region; after the second groove is formed, removing the second patterned layer; and after the second patterning layer is removed, etching the initial first mask layer exposed by the first groove and the second groove by taking the first layer as a mask to form a first mask layer, wherein the first mask layer is internally provided with a first opening and a second opening.
15. The method for forming a semiconductor device according to claim 14, further comprising: after the first patterning layer is removed and before a second patterning layer is formed, forming a side wall mask layer on the side wall of the first groove, wherein the side wall mask layer is positioned on the surface of the initial first mask layer; after the first patterning layer is removed, forming a second patterning layer on the surfaces of the first layer and the side wall mask layer, wherein the first layer and part of the side wall mask layer on the second region are exposed by the second patterning layer; after the second patterning layer is removed, etching the first groove and the initial first mask layer exposed by the second groove by taking the first layer and the side wall mask layer as masks to form a first mask layer; the second mask layer covers the side wall mask layer.
16. The method according to claim 14, wherein a material of the first layer comprises: polysilicon, silicon dioxide, silicon nitride, titanium oxide, or titanium nitride.
17. The method for forming the semiconductor device according to claim 15, wherein the material of the sidewall mask layer comprises: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
18. The method for forming the semiconductor device according to claim 17, wherein the method for forming the side wall mask layer comprises: forming an initial side wall mask layer on the side wall and the bottom of the first groove and the surface of the first layer; and etching the initial side wall mask layer until part of the bottom surface of the first groove is exposed, and forming a side wall mask layer on the side wall of the first groove.
19. The method for forming a semiconductor device according to claim 1, further comprising: after the second mask layer is removed, etching the substrate by taking the first division doping mask layer, the second division doping mask layer and the first mask layer as masks, and forming a first groove and a second groove in the substrate, wherein the first groove is positioned in a first region of the substrate, the first grooves are respectively positioned at two sides of the first division doping mask layer along the second direction, the second grooves are positioned in a second region of the substrate, and the second grooves are respectively positioned at two sides of the second division mask layer along the second direction; after the first groove and the second groove are formed, removing the first division doping mask layer, the second division doping mask layer and the first mask layer; removing the first split doped mask layer, the second split doped mask layer and the first mask layer, and then forming a first interconnection layer in the first groove; and forming a second interconnection layer in the second groove, wherein the first interconnection layer and the second interconnection layer are separated.
20. A semiconductor device formed by the method of any of claims 1 to 19.
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| CN105719956A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| US20190067286A1 (en) * | 2017-08-24 | 2019-02-28 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor structure and fabrication method thereof |
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| US20020081854A1 (en) * | 2000-12-22 | 2002-06-27 | Patrick Morrow | Method for making a dual damascene interconnect using a multilayer hard mask |
| CN103578921A (en) * | 2012-08-10 | 2014-02-12 | 南亚科技股份有限公司 | Patterning technology |
| CN105719956A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
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