CN115775726A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region; forming a plurality of first sacrificial structures which are separated from each other on the first area and the second area; forming a first side wall on the side wall surface of the first sacrificial structure on the second area; after forming a first side wall on the side wall surface of the first sacrificial structure on the second area, modifying the first sacrificial structure on the first area to form a plurality of second sacrificial structures; after the second sacrificial structure is formed, removing the first sacrificial structure; after removing the first sacrificial structure, the layer to be etched is patterned according to the second sacrificial structure on the first region and the first side wall on the second region. The method has the advantages of large process window and low process difficulty.

Description

Method for forming semiconductor structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor structure.

Background

With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance is improved along with the progress of miniaturization of devices. In more and more advanced processes, it is required to realize as many devices as possible in as small an area as possible.

In an advanced process node, a semiconductor structure with a smaller critical dimension is formed by adopting a self-aligned multi-patterning process, so that more devices can be realized in a smaller area, and the integration level of the semiconductor device is improved.

However, in the prior art, in order to meet the requirement of size design, the process window is small and the process difficulty is large.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method for forming a semiconductor structure, so that the process window of the manufacturing process is large and the process difficulty is low.

In order to solve the above technical problem, an aspect of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region; forming a plurality of first sacrificial structures which are separated from each other on the first area and the second area; forming a first side wall on the side wall surface of the first sacrificial structure on the second area; after forming a first side wall on the side wall surface of the first sacrificial structure on the second area, modifying the first sacrificial structure on the first area to form a plurality of second sacrificial structures; after the second sacrificial structure is formed, removing the first sacrificial structure; after removing the first sacrificial structure, the layer to be etched is patterned according to the second sacrificial structure on the first region and the first side wall on the second region.

Optionally, the method for forming a plurality of first sacrificial structures separated from each other on the first region and the second region includes: forming a sacrificial material layer on the first and second regions; forming a first photoetching pattern layer on the sacrificial material layer; and etching the sacrificial material layer by taking the first photoetching pattern layer as a mask until the surface of the layer to be etched is exposed.

Optionally, the width of the second sacrificial structure is greater than the thickness of the first sidewall.

Optionally, the method for forming the first sidewall on the sidewall surface of the first sacrificial structure on the second region includes: forming first side walls on the side wall surfaces of the first sacrificial structures; forming a second photoetching pattern layer on the surface of the layer to be etched and the surfaces of the first sacrificial structures, wherein the second photoetching pattern layer exposes the first sacrificial structures and the first side walls on the first area; and etching the first side wall on the first area by taking the second photoetching pattern layer as a mask until the first side wall on the first area is removed.

Optionally, the method for modifying the first sacrificial structure on the first region to form a plurality of second sacrificial structures includes: and after removing the first side wall on the first area, carrying out an ion implantation process on the first sacrificial structure on the first area by taking the second photoetching pattern layer as a mask.

Optionally, the ions implanted in the ion implantation process include boron ions.

Optionally, the parameters of the ion implantation process further include: the injection energy range is 10 keV-20 keV; the implantation dose range is 10E14cm ² ～10E16cm ² 。

Optionally, after forming the second sacrificial structure, the method for removing the first sacrificial structure includes: after forming the second sacrificial structure, removing the second photoetching pattern layer; and etching the first sacrificial structure on the first area after removing the second photoetching pattern layer.

Optionally, the process for etching the first sacrificial structure on the first region includes a wet etching process.

Optionally, the etchant used in the wet etching process includes ammonia water.

Optionally, the layer to be etched includes: a substrate; a first layer of masking material is located on the substrate.

Optionally, the method for patterning the layer to be etched according to the second sacrificial structure on the first region and the first sidewall on the second region includes: etching the first mask material layer by taking the plurality of second sacrificial structures and the first side walls as masks, forming a plurality of first mask structures on the substrate of the first region, and forming a plurality of second mask structures on the substrate of the second region; forming second side walls on the side walls of the first mask structures and the second mask structures respectively; and etching the substrate by using the second side walls as masks, forming a plurality of first fin groups in the first region, and forming a plurality of second fin groups in the second region, wherein each first fin group comprises 2 mutually-separated fin parts, the side walls of the 2 fin parts in the first fin group are spaced at a first interval, each second fin group comprises 2 mutually-separated fin parts, the side walls of the 2 fin parts in the second fin group are spaced at a second interval, and the first interval is larger than the second interval.

Optionally, the second sacrificial structure includes amorphous silicon doped with boron, the first sidewall includes silicon nitride, the first mask structure and the second mask structure include amorphous silicon, and the second sidewall includes silicon nitride.

Optionally, the layer to be etched further includes: the first protective layer is positioned on the surface of the first mask material layer, and the forming method of the semiconductor structure further comprises the following steps: before the first mask material layer is etched by taking the plurality of second sacrificial structures and the first side walls as masks, the first protective layer is also etched; after the first mask structure and the second mask structure are formed and before the second side wall is formed, the first protective layer is removed.

Optionally, the material of the first protective layer includes silicon oxide.

Optionally, the layer to be etched further includes a second protective layer located between the substrate and the first mask material layer, and the method for forming the second sidewall on the sidewalls of the first mask structure and the second mask structure includes: forming second side wall films on the surfaces of the second protective layer, the surfaces of the first mask structures and the surfaces of the second mask structures; and etching the second side wall film by adopting an anisotropic etching process until the second side wall film on the surface of the second protective layer, the top surface of the first mask structure and the top surface of the second mask structure is removed.

Optionally, the material of the second protective layer includes silicon oxide.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, in the process of patterning the layer to be etched, the first side wall and the second sacrificial structure are used for transferring the pattern distance to the layer to be etched. Because the first side wall is formed on the side wall surface of the first sacrificial structure on the second area, and after the first side wall is formed on the side wall surface of the first sacrificial structure on the second area, the first sacrificial structure on the first area is modified to form a plurality of second sacrificial structures, the first side wall and the second sacrificial structures can be formed according to 1 photoetching pattern layer, so that overlay deviation does not exist between the first side wall and the second sacrificial structures, the pattern precision transmitted to the layer to be etched is high, the process window of the manufacturing process is large, and the process difficulty is low.

Drawings

FIGS. 1-3 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure;

fig. 4 to 14 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

As described in the background, the manufacturing process of the prior art has a small process window and a large process difficulty in order to meet the requirement of size design. The analysis will now be described with reference to specific examples.

Fig. 1 to fig. 3 are schematic cross-sectional views of steps of a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II; a first sacrificial material layer 110 is formed on the substrate 100.

With continued reference to fig. 1, a second sacrificial material layer (not shown) is formed on the first sacrificial material layer 110; forming a lithographically patterned layer (not shown) over the second layer of sacrificial material; and etching the second sacrificial material layer by using the photoetching patterned layer as a mask until the surface of the first sacrificial material layer 110 is exposed, and forming a plurality of second sacrificial structures 120 which are mutually separated on the first sacrificial material layer 110.

With continued reference to fig. 1, second sidewalls 121 are formed on sidewalls of the second sacrificial structure 120.

Referring to fig. 2, the first sacrificial material layer 110 is etched using the second sidewalls 121 as a mask, and a plurality of first sacrificial structures 111 separated from each other are formed on the substrate 100.

With continued reference to fig. 2, a first sidewall 112 is formed on the sidewall of the first sacrificial structure 111.

Referring to fig. 3, the substrate 100 is etched using the first sidewalls 112 as a mask to form a plurality of fins 101.

In the above embodiment, the minimum distance W (as shown in fig. 3) between adjacent fins 101 can be made smaller than the limit dimension of the photolithography process by a Self-Aligned multiple Patterning (SAQP) process.

However, the minimum pitch W of the fins 101 formed by the above method in the first region I and the second region II is the same, and is defined according to the thickness D (shown in fig. 1) of the second sidewall 121. When the size design requirement of the plurality of fins 101, that is, the minimum pitch W needs to be smaller than the limit size of the photolithography process, and the minimum pitch W on the first region I and the second region II needs to be different, the plurality of fins 101 formed by the above forming method cannot meet the size design requirement.

In order to solve the problems of the above-described embodiments, another method of forming a semiconductor structure is proposed in which a first sacrificial structure and a second sacrificial structure having different widths are formed on a first region and a second region, respectively, according to at least 2 patterning layers. And then, forming side walls on the side walls of the first sacrificial structure and the second sacrificial structure so as to respectively transfer the patterns with different intervals to the substrates of the first region and the second region.

However, since it is necessary to form the first sacrificial structure and the second sacrificial structure through at least 2 patterning layers, there is an overlay deviation between the at least 2 patterning layers. Therefore, on the one hand, there is an overlay deviation between the patterns of the first sacrificial structure and the second sacrificial structure, resulting in poor pattern accuracy. On the other hand, in order to avoid unqualified performance and reliability of the semiconductor structure, the overlay deviation needs to be within a preset range, so that the forming process window of the semiconductor structure is small and the process difficulty is large.

In order to solve the above technical problems, a technical solution of the present invention provides a method for forming a semiconductor structure, in which a first sidewall is formed on a sidewall surface of a first sacrificial structure on a second region, and after a first sidewall is formed on a sidewall surface of the first sacrificial structure on the second region, the first sacrificial structure on the first region is modified to form a plurality of second sacrificial structures, so that a process window of a manufacturing process is large and a process difficulty is low.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 4 to 14 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 4, a layer to be etched 200 is provided, wherein the layer to be etched 200 includes a first region I and a second region II.

In this embodiment, the layer to be etched 200 includes: a substrate 210, and a first masking material layer 220 on the substrate 210.

The material of the substrate 210 comprises a semiconductor material.

In the present embodiment, the material of the substrate 210 includes silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.

The first mask material layer 220 provides material for subsequently forming a plurality of first mask structures and a plurality of second mask structures.

In the present embodiment, the material of the first mask material layer 220 includes amorphous silicon.

In this embodiment, the layer to be etched 200 further includes: a first protective layer 221 on the surface of the first mask material layer 220.

Since the first protection layer 221 is located on the surface of the first mask material layer 220, on one hand, in the process of performing the subsequent modification treatment on the first sacrificial structure on the first region I, the first protection layer 221 can protect the first mask material layer 220, and the risk that the material property of the first mask material layer 220 is changed by the modification treatment is reduced. On the other hand, the first protection layer 221 can also protect the first mask material layer 220 in the subsequent processes of forming and removing the second lithography pattern layer, and reduce the damage to the first mask material layer 220 caused by the processes of forming and removing the second lithography pattern layer. In addition, the first protection layer 221 can also protect the first mask material layer 220 in the subsequent process of removing the first sacrificial structure, so as to prevent the first mask material layer 220 from being damaged by the etching process for removing the first sacrificial structure. Therefore, a plurality of first mask structures and a plurality of second mask structures with good quality and good appearance can be formed through the first mask material layer 220, and then the transferred pattern precision can be improved better.

In this embodiment, the material of the first protection layer 221 includes silicon oxide.

In this embodiment, the layer to be etched 200 further includes: a second protective layer 222 located between the substrate 210 and the first masking material layer 220.

Because the second protection layer 222 is located between the substrate 210 and the first mask material layer 220, the substrate 210 can be protected by the second protection layer 222 in the subsequent etching process for forming a plurality of first mask structures and a plurality of second mask structures, and the damage to the substrate 210 caused by the etching process is reduced, so that the transferred pattern precision is better improved.

In the present embodiment, the material of the second protection layer 222 is different from the material of the first mask material layer 220. Therefore, in the etching process of subsequently forming the plurality of first mask structures and the plurality of second mask structures, the etching process can have different etching rates on the material of the second protection layer 222 and the material of the first mask material layer 220, so as to better protect the protection effect of the substrate 210.

In the present embodiment, the material of the second protection layer 222 is different from the material of the substrate 210. Therefore, after the fin portion is formed subsequently, in the etching process for removing the material of the second protection layer 222, the material of the substrate 210 and the material of the second protection layer 222 can have a larger etching selection ratio, so that the fin portion and the substrate 210 are damaged little or not by the etching process for removing the second protection layer 222.

In this embodiment, the material of the second protection layer 222 includes silicon oxide.

In other embodiments, the layer to be etched does not include the second protective layer.

Referring to fig. 5, a plurality of first sacrificial structures 240 are formed on the first region I and the second region II, which are separated from each other.

In this embodiment, the method for forming several first sacrificial structures 240 separated from each other on the first region I and the second region II includes: forming a sacrificial material layer (not shown) on the first and second regions I and II; forming a first lithographic pattern layer (not shown) on the sacrificial material layer; and etching the sacrificial material layer by taking the first photoetching pattern layer as a mask until the surface of the layer to be etched 200 is exposed.

In the present embodiment, the process of forming the sacrificial material layer includes a chemical vapor deposition process, a physical vapor deposition process, and the like.

In this embodiment, the process of etching the sacrificial material layer includes at least one of a dry etching process and a wet etching process.

In this embodiment, the material of the first lithography pattern layer includes a photoresist.

In the present embodiment, after forming the first sacrificial structures 240, the first lithography pattern layer is removed.

In the present embodiment, the width of the first sacrificial structure 240 on the first region I is different from the width of the first sacrificial structure 240 on the second region II.

In other embodiments, the width of the first sacrificial structure on the first region is the same as the width of the first sacrificial structure on the second region.

In the present embodiment, the material of the first sacrificial structure 240 includes amorphous silicon.

Next, a first sidewall is formed on the sidewall of the first sacrificial structure 240 in the second region II. Specifically, please refer to fig. 6 to 8 for the step of forming the first sidewall on the sidewall surface of the first sacrificial structure 240 on the second region II.

Referring to fig. 6, first sidewalls 241 are formed on sidewall surfaces of the first sacrificial structures 240.

The first sidewalls 241 on the second region II are used to define a distance between sidewalls of 2 fins in the subsequently formed second fin group (e.g., the second distance W2 shown in fig. 13).

In this embodiment, the method for forming the first sidewalls 241 on the sidewall surfaces of the plurality of first sacrificial structures 240 includes: forming a first sidewall material film (not shown) on the surface of the layer to be etched 200 and the surfaces of the first sacrificial structures 240; and etching the first side wall material film by adopting an anisotropic etching process until the surface of the layer to be etched 200 and the top surfaces of the first sacrificial structures 240 are exposed.

In this embodiment, the forming process of the first sidewall material film includes a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the anisotropic etching process for etching the first sidewall material film includes a plasma etching process.

In this embodiment, the material of the first sidewall 241 is different from that of the first protection layer 221. Therefore, the etching process for subsequently removing the first sacrificial structure 240 on the second region II can have a higher etching selectivity for the materials of the first protection layer 221 and the first sidewall 241, so as to better protect the first mask material layer 220 in the subsequent process of removing the first sacrificial structure 240 on the second region II.

In this embodiment, the material of the first sidewall spacers 241 includes silicon nitride.

Specifically, the material of the first sidewall 241 includes Si ₃ N ₄ 。

Referring to fig. 7, a second photo-etching pattern layer 250 is formed on the surface of the layer to be etched 200 and the first sacrificial structures 240, and the second photo-etching pattern layer 250 exposes the first sacrificial structures 240 and the first sidewalls 241 on the first region I.

The second lithography pattern layer 250 is used for covering the first sacrificial structure 240 and the first sidewall 241 on the second region II while exposing the first sacrificial structure 240 and the first sidewall 241 on the first region I, so that the first sidewall 241 on the first region I can be separately removed in the following, and the first sacrificial structure 240 on the first region I can be separately modified in the following to form a second sacrificial structure. The second lithography pattern layer 250 is not used for directly defining the pattern shape, so the pattern precision requirement of the second lithography pattern layer 250 is lower, and the overlay precision requirement is lower, thereby the process window of the manufacturing process is better increased, and the process difficulty is reduced.

In this embodiment, the material of the second lithography pattern layer 250 includes photoresist.

Referring to fig. 8, the first sidewall 241 on the first region I is etched by using the second photolithography pattern layer 250 as a mask until the first sidewall 241 on the first region I is removed.

The material of the first sacrificial structure 240 is different from the material of the first sidewall 241, so that in the etching process for etching the first sidewall 241 on the first region I, the material of the first sidewall 241 and the material of the first sacrificial structure 240 can have a larger etching selectivity ratio, so that the first sacrificial structure 240 of the first region I is retained while the first sidewall 241 is removed. Thereby, the first sidewall 241 is formed on the sidewall surface of the first sacrificial structure 240 on the second region II.

The process for etching the first side wall on the first region I comprises at least one of a dry etching process and a wet etching process.

Preferably, a dry etching process is adopted in this embodiment.

Referring to fig. 9, after forming first sidewalls 241 on the sidewall surfaces of the first sacrificial structures 240 on the second region II, the first sacrificial structures 240 on the first region I are modified to form a plurality of second sacrificial structures 242.

The second sacrificial structures 242 are used to define the spacing between the sidewalls of the 2 fins in the first fin group to be formed later (the first spacing W1 shown in fig. 13).

Preferably, the width of the second sacrificial structure 242 is greater than the thickness of the first sidewall 241.

Thus, not only the to-be-etched layer 200 of the first region I and the to-be-etched layer 200 of the second region II are respectively transferred with the pattern pitches (the first pitch W1 and the second pitch W2 as shown in fig. 13) of different sizes through the second sacrificial structure 242 and the first sidewall 241, but also the to-be-etched layer 200 of the second region II can form a pattern pitch (the first pitch W1 as shown in fig. 13) smaller than the limit size of the photolithography process, so as to satisfy the size design requirement for the semiconductor structure while improving the integration degree of the semiconductor structure.

In this embodiment, the method for modifying the first sacrificial structures 240 on the first region I to form the plurality of second sacrificial structures 242 includes: after removing the first sidewall 241 on the first region I, performing an ion implantation process on the first sacrificial structure 240 on the first region I by using the second lithography pattern layer 250 as a mask.

Through the ion implantation process, the material characteristics of the first sacrificial structure 240 can be changed, so that in the etching process for subsequently removing the first sacrificial structure 240 on the second region II, the material of the first sacrificial structure 240 and the material of the second sacrificial structure 242 can have a higher etching selectivity ratio, so that the second sacrificial structure 242 is retained while the first sacrificial structure 240 is removed. In this embodiment, the ions implanted in the ion implantation process include boron ions. The material of the second sacrificial structure 242 comprises boron-doped amorphous silicon.

Specifically, by doping amorphous silicon with boron (the material of the second sacrificial structure 242), the etching rate of a solution such as ammonia water can be reduced in a subsequent wet etching process, so that the etching selectivity of the amorphous silicon with respect to undoped silicon (the material of the first sacrificial structure 240) is improved. In this embodiment, the parameters of the ion implantation process further include: the range of the implantation energy is 10 keV-20 keV; the implantation dose range is 10E14cm ² ～10E16cm ² 。

In one aspect, the implant energy and implant dose determine the concentration of boron in the material of the second sacrificial structure 242. When the implantation energy and the implantation dose are too small, the concentration of boron is too low, so that the second sacrificial structure 242 is easily worn during the subsequent removal of the first sacrificial structure 240, which is not favorable for improving the precision of the pattern transferred to the layer to be etched 200. On the other hand, too large an implant energy and implant dose may result in diffusion of the implanted boron, which may have an effect on the underlying device material. Therefore, selecting a suitable implant dose range and implant energy range,that is, the implantation energy ranges from 10keV to 20keV, and the implantation dose ranges from 10E14cm ² ～10E16cm ² On one hand, the loss of the second sacrificial structure 242 due to the etching process for removing the first sacrificial structure 240 is reduced, and on the other hand, the influence on the lower device material can be further avoided.

Referring to fig. 10, after forming the second sacrificial structure 242, the first sacrificial structure 240 is removed.

In this embodiment, after forming the second sacrificial structure 242, the method of removing the first sacrificial structure 240 includes: after forming the second sacrificial structure 242, the second lithography pattern layer 250 is removed; after removing the second lithographic pattern layer 250, the first sacrificial structure 240 on the first region I is etched.

In this embodiment, the process of removing the second lithography pattern layer 250 includes an ashing process, and the like.

The process of etching the first sacrificial structure 240 on the first region I includes at least one of a dry etching process and a wet etching process.

Preferably, a wet etching process is used to etch the first sacrificial structure 240. The selectivity of the wet etching process is good, so that the first sacrificial structure 240 can be better removed, and the loss of the first sidewall 241 and the second sacrificial structure 242 is reduced.

In this embodiment, the etchant used in the wet etching process includes ammonia. Therefore, the material of the first sacrificial structure 240 and the material of the second sacrificial structure 242 have a higher etching selection ratio, and the material of the first sacrificial structure 240 and the material of the first sidewall 241 also have a higher etching selection ratio, so that the first sidewall 241 and the second sacrificial structure 242 are retained while the first sacrificial structure 240 is removed.

Then, the layer to be etched 200 is patterned according to the second sacrificial structure 242 on the first region I and the first sidewall 241 on the second region II.

During the process of patterning the layer to be etched 200, the first sidewalls 241 and the second sacrificial structures 242 are used to transfer pattern pitches (the first pitch W1 and the second pitch W2 shown in fig. 13) to the layer to be etched. Because the first sidewall 241 is formed on the sidewall surface of the first sacrificial structure 240 in the second region II, and after the first sidewall 241 is formed on the sidewall surface of the first sacrificial structure 240 in the second region II, the first sacrificial structure 240 in the first region I is modified to form a plurality of second sacrificial structures 242, the first sidewall 241 and the second sacrificial structure 242 can be formed according to 1 lithography pattern layer (first lithography pattern layer), so that overlay deviation does not exist between the first sidewall 241 and the second sacrificial structure 242, and thus, the pattern precision transferred to the layer to be etched 200 is high, and the process window of the manufacturing process is large and the process difficulty is low.

Please refer to fig. 11 to 14 for the specific steps of patterning the layer to be etched 200.

Referring to fig. 11, the first masking material layer 220 is etched using the second sacrificial structures 242 and the first sidewalls 241 as masks, so as to form first masking structures 261 on the substrate 210 in the first region I and second masking structures 262 on the substrate 210 in the second region II.

In this embodiment, the process of etching the first mask material layer 220 includes at least one of a dry etching process and a wet etching process.

In this embodiment, the material of the first mask structure 261 includes amorphous silicon.

In the present embodiment, the material of the second mask structure 262 includes amorphous silicon.

In this embodiment, before etching the first mask material layer 220 by using the plurality of second sacrificial structures 242 and the first sidewalls 241 as masks, the first protection layer 221 is further etched.

In the present embodiment, after the first and second mask structures 261 and 262 are formed, the first protective layer 221 is removed.

With reference to fig. 11, after removing the first protection layer 221, second sidewalls 230 are formed on sidewalls of the first mask structures 261 and the second mask structures 262, respectively.

In this embodiment, the method for forming the second sidewall spacers 230 on the sidewalls of the first mask structure 261 and the second mask structure 262 includes: forming a second sidewall film (not shown) on the surface of the second protection layer 222, the surfaces of the first mask structures 261 and the surfaces of the second mask structures 262; and etching the second side wall film by using an anisotropic etching process until the second side wall film on the surface of the second protection layer 222, the top surface of the first mask structure 261 and the top surface of the second mask structure 262 is removed.

In this embodiment, the process of etching the second sidewall film includes a plasma etching process.

In this embodiment, the material of the second sidewall spacers 230 includes silicon nitride.

Specifically, the material of the second sidewall 230 includes Si ₃ N ₄ 。

Referring to fig. 12, after forming the second sidewalls 230, the first mask structure 261 and the second mask structure 262 are removed.

In this embodiment, the process of removing the first mask structure 261 and the second mask structure 262 includes at least one of a dry etching process and a wet etching process.

Referring to fig. 13 and 14, fig. 13 is a schematic cross-sectional view taken along the direction X1-X2 in fig. 14, fig. 14 is a schematic perspective view of fig. 13, the substrate 210 is etched by using the second sidewalls 230 as masks, a plurality of first fin groups a are formed in the first region I, and a plurality of second fin groups B are formed in the second region II.

Each first fin group a includes 2 fins 211 separated from each other, and sidewalls of the 2 fins 211 in the first fin group a have a first pitch W1 therebetween.

Each second fin group B includes 2 fins 221 separated from each other, and sidewalls of the 2 fins 211 in the second fin group B have a second pitch W2 therebetween, and the first pitch W1 is greater than the second pitch W2.

Thus, while the fins 221 with a smaller pitch (the second pitch W2) are formed on the second region II by the Self-aligned multi-Patterning process (SAQP), the fins 221 with a larger pitch (the first pitch W1) are formed on the first region I by the Self-aligned Double Patterning process (SADP).

In the present embodiment, after the first fin group a and the second fin group B are formed, the second sidewalls 230 are removed.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (17)

1. A method of forming a semiconductor structure, comprising:

providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region;

forming a plurality of first sacrificial structures which are separated from each other on the first area and the second area;

forming a first side wall on the side wall surface of the first sacrificial structure on the second area;

after forming a first side wall on the side wall surface of the first sacrificial structure on the second area, modifying the first sacrificial structure on the first area to form a plurality of second sacrificial structures;

after the second sacrificial structure is formed, removing the first sacrificial structure;

and after the first sacrificial structure is removed, patterning the layer to be etched according to a second sacrificial structure on the first region and the first side wall on the second region.

2. The method of forming a semiconductor structure according to claim 1, wherein the method of forming a plurality of first sacrificial structures on the first and second regions separately from each other comprises: forming a sacrificial material layer on the first and second regions; forming a first photoetching pattern layer on the sacrificial material layer; and etching the sacrificial material layer by taking the first photoetching pattern layer as a mask until the surface of the layer to be etched is exposed.

3. The method for forming the semiconductor structure according to claim 1, wherein the width of the second sacrificial structure is greater than the thickness of the first sidewall.

4. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first sidewall on the sidewall surface of the first sacrificial structure over the second region comprises: forming first side walls on the side wall surfaces of the first sacrificial structures; forming a second photoetching pattern layer on the surface of the layer to be etched and the surfaces of the first sacrificial structures, wherein the second photoetching pattern layer exposes the first sacrificial structures and the first side walls on the first area; and etching the first side wall on the first area by taking the second photoetching pattern layer as a mask until the first side wall on the first area is removed.

5. The method of claim 4, wherein modifying the first sacrificial structures over the first region to form the plurality of second sacrificial structures comprises: and after removing the first side wall on the first area, carrying out an ion implantation process on the first sacrificial structure on the first area by taking the second photoetching pattern layer as a mask.

6. The method of claim 5, wherein the ions implanted in the ion implantation process comprise boron ions.

7. The method of forming a semiconductor structure of claim 6, wherein the parameters of the ion implantation process further comprise: the injection energy range is 10 keV-20 keV; the implantation dose range is 10E14cm ² ～10E16 cm ² 。

8. The method of forming a semiconductor structure of claim 5, wherein removing the first sacrificial structure after forming the second sacrificial structure comprises: after forming the second sacrificial structure, removing the second photoetching pattern layer; and etching the first sacrificial structure on the first area after removing the second photoetching pattern layer.

9. The method of forming a semiconductor structure of claim 8, wherein the process of etching the first sacrificial structure over the first region comprises a wet etch process.

10. The method of claim 9, wherein the wet etching process uses an etchant comprising ammonia.

11. The method of forming a semiconductor structure of claim 1, wherein the layer to be etched comprises: a substrate; a first masking material layer is located on the substrate.

12. The method of forming a semiconductor structure of claim 11, wherein patterning the layer to be etched according to the second sacrificial structure on the first region and the first sidewall on the second region comprises: etching the first mask material layer by taking the plurality of second sacrificial structures and the first side walls as masks, forming a plurality of first mask structures on the substrate of the first area, and forming a plurality of second mask structures on the substrate of the second area; forming second side walls on the side walls of the first mask structures and the second mask structures respectively; and etching the substrate by taking the second side walls as masks, forming a plurality of first fin groups in the first region, and forming a plurality of second fin groups in the second region, wherein each first fin group comprises 2 mutually-discrete fin parts, a first space is formed between the side walls of the 2 fin parts in the first fin group, each second fin group comprises 2 mutually-discrete fin parts, a second space is formed between the side walls of the 2 fin parts in the second fin group, and the first space is larger than the second space.

13. The method of claim 12, wherein the material of the second sacrificial structure comprises boron-doped amorphous silicon, the material of the first sidewall spacers comprises silicon nitride, the material of the first and second mask structures comprises amorphous silicon, and the material of the second sidewall spacers comprises silicon nitride.

14. The method of forming a semiconductor structure of claim 12, wherein the layer to be etched further comprises: the first protective layer is positioned on the surface of the first mask material layer, and the forming method of the semiconductor structure further comprises the following steps: before the first mask material layer is etched by taking the plurality of second sacrificial structures and the first side walls as masks, the first protective layer is also etched; after the first mask structure and the second mask structure are formed and before the second side wall is formed, the first protective layer is removed.

15. The method of forming a semiconductor structure of claim 14, wherein a material of the first protective layer comprises silicon oxide.

16. The method of claim 12, wherein the layer to be etched further comprises a second protective layer between the substrate and the first masking material layer, and wherein the method of forming second sidewalls on the sidewalls of the first and second masking structures comprises: forming second side wall films on the surfaces of the second protective layer, the surfaces of the first mask structures and the surfaces of the second mask structures; and etching the second side wall film by adopting an anisotropic etching process until the second side wall film on the surface of the second protective layer, the top surface of the first mask structure and the top surface of the second mask structure is removed.

17. The method of forming a semiconductor structure of claim 16, wherein a material of the second protective layer comprises silicon oxide.

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