CN111555949A - VPN application development platform and monitoring method thereof - Google Patents
VPN application development platform and monitoring method thereof Download PDFInfo
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- CN111555949A CN111555949A CN201911046424.0A CN201911046424A CN111555949A CN 111555949 A CN111555949 A CN 111555949A CN 201911046424 A CN201911046424 A CN 201911046424A CN 111555949 A CN111555949 A CN 111555949A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3031—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a motherboard or an expansion card
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/045—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply hybrid encryption, i.e. combination of symmetric and asymmetric encryption
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/02—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
- H04L67/025—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP] for remote control or remote monitoring of applications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/06—Protocols specially adapted for file transfer, e.g. file transfer protocol [FTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a VPN application development platform, which comprises an FPGA, a USB module, a JTAG interface, a Flash, an RTC clock module, an SD interface, a cryptographic algorithm chip, a gigabit Ethernet communication circuit, a DDR and an eMMC; the gigabit Ethernet communication circuit is connected with the FPGA and is used for connecting external equipment for data communication; the cryptographic algorithm chip is connected with the FPGA and is used for realizing an SM1 symmetric algorithm, an SM2 asymmetric algorithm and an SM3 hash algorithm; the Flash is connected with the FPGA and used as a configuration circuit of the FPGA; the USB module is connected with the FPGA, the JTAG interface is connected with the Flash, the PC sends a programmed data file to the USB module, and the USB module finishes erasing and programming the Flash through the JTAG interface after receiving the data file, thereby realizing remote online upgrade of the FPGA program. The SM1 symmetric algorithm, the SM2 asymmetric algorithm and the SM3 hash algorithm are realized through the FPGA, and the data security is ensured.
Description
Technical Field
The invention relates to the technical field of power distribution network equipment, in particular to a VPN application development platform and a monitoring method thereof.
Background
The automation of the power distribution network is an important means for improving the reliability and quality of power supply, expanding the power supply capacity and realizing the efficient and economic operation of the power distribution network, and is also one of the important bases for realizing the intelligent power grid. The distribution network has wide distribution, more quantity and is distributed dispersedly. In view of the particularity of the power distribution network, the mixing of multiple communication modes is a necessary way for the development and popularization of power distribution automation. Optical fiber communication is the most ideal distribution automation communication mode; second, carrier communication and communication using a wireless public network are widely used communication means. However, the communication data of the existing distribution network automation equipment has the problem of low safety and is very easy to be illegally acquired.
Disclosure of Invention
The invention aims to overcome the technical problems and provide a VPN application development platform for secure data communication.
In order to achieve the purpose, the invention adopts the following technical scheme:
a VPN application development platform comprises an FPGA, a USB module, a JTAG interface, a Flash, an RTC clock module, an SD interface, a cryptographic algorithm chip, a gigabit Ethernet communication circuit, a DDR and an eMMC; the gigabit Ethernet communication circuit is connected with the FPGA and is used for connecting external equipment for data communication; the cryptographic algorithm chip is connected with the FPGA and is used for realizing an SM1 symmetric algorithm, an SM2 asymmetric algorithm and an SM3 hash algorithm; the DDR is connected with the FPGA and used for meeting the requirements of a platform system and application operation; the SD interface is connected with the FPGA and is used for externally connecting an SD card; the eMMC is connected with the FPGA and used for meeting the requirements of a platform system and application operation; the RTC clock module is connected with the FPGA and used for setting and storing a system clock; the Flash is connected with the FPGA and used as a configuration circuit of the FPGA; the USB module is connected with the FPGA, the JTAG interface is connected with the Flash, the PC sends a data file to be programmed to the USB module, and the USB module finishes erasing and programming the Flash through the JTAG interface after receiving the data file, so that the remote online upgrade of the FPGA program is realized.
Furthermore, the gigabit ethernet communication circuit comprises an ethernet control chip and a network port, and the FPGA is connected to the network port through the ethernet control chip.
Further, the network port is an RJ45 network port, the model is HanRun HR872230H, and a network transformer is arranged in the RJ45 network port.
Further, the Ethernet control chip is an Intel I350.
Further, the model of the FPGA is a 7Z015 chip of Xilinx company.
Further, the cryptographic algorithm chip is an NRSEC3000 chip.
The system further comprises a monitoring module for monitoring the operating condition of the platform, wherein the monitoring module comprises a single chip microcomputer system and a watchdog circuit; the FPGA is connected with the single chip microcomputer system, the single chip microcomputer system is connected with the watchdog circuit, and the watchdog circuit is connected with the FPGA.
Further, the method comprises a monitoring method for the application and a monitoring method for the system.
Further, the method for monitoring the application specifically comprises the following steps: an application program in the FPGA sends a timer reset instruction of the watchdog circuit to the single chip microcomputer system at regular time; and when the singlechip system does not receive the instruction on time, immediately sending a system reset command to the watchdog circuit, and immediately resetting the whole system after the watchdog circuit receives the command.
Further, the method for monitoring the system specifically comprises the following steps: the background daemon process of the FPGA sends a heartbeat instruction to the single chip microcomputer system at regular time, when the single chip microcomputer system does not receive the heartbeat instruction on time, a system reset command is immediately sent to the watchdog circuit, and the watchdog circuit immediately resets the whole system after receiving the command.
The invention has the beneficial effects that:
1. the SM1 symmetric algorithm, the SM2 asymmetric algorithm and the SM3 hash algorithm are realized through the FPGA, and the data security is ensured.
2. The invention realizes the remote online upgrade of the FPGA program through the USB module.
Drawings
FIG. 1: the invention discloses a circuit structure block diagram of a first embodiment of a VPN application development platform.
FIG. 2: the invention relates to a series connection diagram of an FPGA, a JTAG interface and a Flash.
FIG. 3: the invention relates to an upgrading circuit diagram of a USB module.
FIG. 4: the invention discloses a circuit structure block diagram of a second embodiment of a VPN application development platform.
FIG. 5: the invention discloses a schematic diagram of a method for monitoring an application program of a VPN application development platform.
FIG. 6: a schematic diagram of a monitoring method of a system of a VPN application development platform is provided.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
Example one
As shown in fig. 1, a VPN application development platform includes an FPGA, a USB module, a JTAG interface, Flash, an RTC clock module, an SD interface, a cryptographic algorithm chip, a gigabit ethernet communication circuit, a DDR, and an eMMC.
The FPGA is a 7Z015 chip of Xilinx company, and a Linux system and an application program are arranged in the FPGA.
The gigabit Ethernet communication circuit comprises an Ethernet control chip and a network port, the FPGA is connected with the network port through the Ethernet control chip, the network port is an RJ45 network port, the model is HanRun HR872230H, a network transformer is arranged in the RJ45 network port, the Ethernet control chip is Intel I350, and the gigabit Ethernet communication circuit is used for connecting external equipment to perform data communication.
The cryptographic algorithm chip is connected with the FPGA and used for realizing an SM1 symmetric algorithm, an SM2 asymmetric algorithm and an SM3 hash algorithm, the cryptographic algorithm chip is an NRSEC3000 chip, and the chip realizes the SM1 symmetric algorithm, the SM2 asymmetric algorithm and the SM3 hash algorithm required by national commercial cryptographic products. The system has ISO7816 and SPI interfaces and supports a plurality of communication rates, and the provided safety mechanisms including a frequency detection mechanism, program and data encryption storage, code protection and the like can effectively resist physical attack and fragmentation detection. The SM1 and SM2 algorithms based on the NRSEC3000 encryption chip can conveniently realize a mixed encryption mechanism, construct a safe and efficient cryptosystem, and can be used in application occasions with higher requirements on information safety. The communication of the NRSEC3000 encryption chip adopts a 'one-question-one-answer' mode, namely, the processor sends a command to the NRSEC3000 encryption chip, and the chip returns an answer result. Each algorithmic function supported by the chip is performed by one or more interactive processes.
The DDR is connected with the FPGA, the memory capacity of the DDR is 256Mbyte storage space, and the DDR is mainly used for further meeting the requirements of system and application operation.
The SD interface is connected with the FPGA and used for being externally connected with an SD card to realize data interaction.
The eMMC is connected with the FPGA and mainly used for storing a boot file, a kernel file and a root file system required by the system and quickly accessing an application program and data of a user during operation.
The RTC clock module is connected with the FPGA and used for setting and storing a system clock;
as shown in figure 2, Flash and FPGA are connected in series by using a JTAG interface, the Flash is used as a configuration circuit of the FPGA, a TDI signal of the JTAG interface is sent to a TDI interface of the Flash, a TDO interface of the Flash is connected with a TDL of the FPGA, the TDO of the FPGA is connected with the TDO of the JTAG interface to form a daisy chain form, the TMS and the TCK are directly connected, and when a JTAG download line is used, the Flash can be burnt.
As shown in fig. 3, the USB module is a CY7068013A chip, the PD0-PD7 of the USB module is connected to the FPGA as a data line, and the PD8-PD11 of the USB module are configured as an I/O interface connected to a JTAG interface of the FPGA. And after receiving the data file, the USB module simulates JTAG time sequence in accordance with IEEE STD 1149.1 standard by using software of four I/O ports PD8-PD11 to complete the erasing and programming of Flash, thereby realizing the remote online upgrade of the FPGA program.
Example two
Because the application occasion of the system usually requires unattended operation and long-term non-stop work, which requires that the system can be automatically recovered under the condition of crash or crash, as shown in fig. 4, a monitoring module for monitoring the operating condition of the platform is added on the basis of the first embodiment, and the monitoring module comprises a single chip microcomputer system and a watchdog circuit; the FPGA is connected with the single chip microcomputer system, the single chip microcomputer system is connected with the watchdog circuit, and the watchdog circuit is connected with the FPGA. Through the independent single chip microcomputer system and the watchdog circuit, the FPGA system can be monitored and reset.
EXAMPLE III
The invention also provides a method for monitoring the application program of the VPN application development platform, which comprises the following steps: as shown in fig. 5, an application program in the FPGA sends a timer reset instruction of the watchdog circuit to the single chip microcomputer system at regular time; at the moment, the operation lamp flickers once, when the singlechip microcomputer system does not receive the instruction on time, a system reset command is immediately sent to the watchdog circuit, the watchdog circuit immediately resets the whole system after receiving the command, and before resetting, the operation lamp flickers rapidly.
Example four
The invention also provides a monitoring method of the system of the VPN application development platform, which comprises the following steps: as shown in fig. 6, the background daemon process of the FPGA sends a heartbeat instruction to the single chip microcomputer system at regular time, at this time, the operation lamp flashes once, when the single chip microcomputer system does not receive the instruction on time, a system reset command is immediately sent to the watchdog circuit, the watchdog circuit immediately resets the whole system after receiving the command, and before resetting, the operation lamp flashes rapidly.
The invention adopts two-stage system monitoring design (namely application program monitoring and system monitoring) to respectively monitor the normal operation of the application program and the system, thereby ensuring that the system can automatically recover the operation when the system fails.
Finally, it should be noted that: the above embodiments are only used to illustrate the present invention and do not limit the technical solutions described in the present invention; thus, while the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.
Claims (10)
1. A VPN application development platform, characterized by: the device comprises an FPGA, a USB module, a JTAG interface, a Flash, an RTC clock module, an SD interface, a cryptographic algorithm chip, a gigabit Ethernet communication circuit, a DDR and an eMMC; the gigabit Ethernet communication circuit is connected with the FPGA and is used for connecting external equipment for data communication; the cryptographic algorithm chip is connected with the FPGA and is used for realizing an SM1 symmetric algorithm, an SM2 asymmetric algorithm and an SM3 hash algorithm; the DDR is connected with the FPGA and used for meeting the requirements of a platform system and application operation; the SD interface is connected with the FPGA and is used for externally connecting an SD card; the eMMC is connected with the FPGA and used for meeting the requirements of a platform system and application operation; the RTC clock module is connected with the FPGA and used for setting and storing a system clock; the Flash is connected with the FPGA and used as a configuration circuit of the FPGA; the USB module is connected with the FPGA, the JTAG interface is connected with the Flash, the PC sends a data file to be programmed to the USB module, and the USB module finishes erasing and programming the Flash through the JTAG interface after receiving the data file, so that the remote online upgrade of the FPGA program is realized.
2. The VPN application development platform according to claim 1, wherein: the gigabit Ethernet communication circuit comprises an Ethernet control chip and a network port, and the FPGA is connected with the network port through the Ethernet control chip.
3. The VPN application development platform according to claim 2, wherein: the net port is an RJ45 net port, the model is Hanrun HR872230H, and a network transformer is arranged in the RJ45 net port.
4. The VPN application development platform according to claim 2, wherein: so the ethernet control chip is intel 350.
5. The VPN application development platform according to claim 1, wherein: the FPGA is a 7Z015 chip of Xilinx company.
6. The VPN application development platform according to claim 1, wherein: the cryptographic algorithm chip is an NRSEC3000 chip.
7. The VPN application development platform according to claim 1, wherein: the monitoring module is used for monitoring the operating condition of the platform and comprises a single chip microcomputer system and a watchdog circuit; the FPGA is connected with the single chip microcomputer system, the single chip microcomputer system is connected with the watchdog circuit, and the watchdog circuit is connected with the FPGA.
8. A monitoring method for a VPN application development platform according to claim 7, characterised in that: the method comprises a monitoring method for an application and a monitoring method for a system.
9. The monitoring method of the VPN application development platform according to claim 8, wherein: the application monitoring method specifically comprises the following steps: an application program in the FPGA sends a timer reset instruction of the watchdog circuit to the single chip microcomputer system at regular time; and when the singlechip system does not receive the instruction on time, immediately sending a system reset command to the watchdog circuit, and immediately resetting the whole system after the watchdog circuit receives the command.
10. The monitoring method of the VPN application development platform according to claim 8, wherein: the monitoring method for the system specifically comprises the following steps: the background daemon process of the FPGA sends a heartbeat instruction to the single chip microcomputer system at regular time, when the single chip microcomputer system does not receive the heartbeat instruction on time, a system reset command is immediately sent to the watchdog circuit, and the watchdog circuit immediately resets the whole system after receiving the command.
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| CN201911046424.0A CN111555949A (en) | 2019-10-30 | 2019-10-30 | VPN application development platform and monitoring method thereof |
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| CN201911046424.0A CN111555949A (en) | 2019-10-30 | 2019-10-30 | VPN application development platform and monitoring method thereof |
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Application publication date: 20200818 |