CN111147045B - Zero clearing method and system for superconducting circuit - Google Patents
Zero clearing method and system for superconducting circuit Download PDFInfo
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- CN111147045B CN111147045B CN201911340498.5A CN201911340498A CN111147045B CN 111147045 B CN111147045 B CN 111147045B CN 201911340498 A CN201911340498 A CN 201911340498A CN 111147045 B CN111147045 B CN 111147045B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/86—Generating pulses by means of delay lines and not covered by the preceding subgroups
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
Abstract
The invention provides a zero clearing method and a zero clearing system for a superconducting circuit, which comprise the following steps: sending a zero clearing instruction signal to an instruction input interface of a non-destructive read register, outputting data to a first magnetic flux sub-separation device by the non-destructive read register according to a high-frequency local clock signal, separating the output data into a zero clearing signal and a trigger signal by the first magnetic flux sub-separation device, and inputting the zero clearing signal to a superconducting register between each pipeline stage of the superconducting processor; inputting a low-frequency system clock signal to a second magnetic flux sub-separating device, wherein the second magnetic flux sub-separating device divides the low-frequency system clock signal into a first low-frequency system clock pulse and a second low-frequency system clock pulse; the first D trigger outputs signal pulse according to the trigger signal and the first low-frequency system clock pulse, the second magnetic flux sub-separation device outputs delay pulse according to the signal pulse and the second low-frequency system clock pulse, and the nondestructive reading register resets according to the delay pulse to stop outputting the zero clearing signal.
Description
Technical Field
The invention relates to the field of design of superconducting circuit components in a superconducting computer, in particular to a zero clearing method and a zero clearing system for a superconducting circuit.
Background
The superconducting circuit technology is an important technical development direction of future computers, countries such as the United states, Japan, England, south Africa and the like all focus on the research and development work of superconducting devices, and many units in China also continuously develop the research and development work of superconducting devices, computers and the like. The existing superconducting circuit components are designed based on traveling wave water flow, and the traditional trigger concept is not provided, so that the register function is difficult to realize. Internationally, research and development institutions such as the United states, Japan and the like propose to construct serial shift registers by using limited units, but the read and write of the registers can only be shifted serially, so that the performance is relatively low. And no specific design has been proposed for the zero clearing signal generating device required in the multi-stage flowing water superconducting processor.
The shortcomings and deficiencies of existing superconducting circuit technologies are that most processor circuit designs are based on traveling wave pipelining, without the traditional pipelining mechanism. This results in low operating efficiency, failure to fully exploit the high speed advantage of superconducting circuits, and difficulty in compatibility with current computer software systems. The invention research aiming at the zero clearing signal generating device of the superconducting register is in a blank state at present.
Disclosure of Invention
The invention aims to solve the problem that when a superconducting processor circuit is designed in a superconducting register, after a zero clearing instruction signal is obtained, an effective zero clearing signal which meets the actual working time sequence requirement needs to be provided for a corresponding superconducting register. Therefore, a superconducting circuit zero clearing signal generating device is provided.
Aiming at the defects of the prior art, the invention provides a zero clearing method of a superconducting circuit, which comprises the following steps:
step 1, sending a zero clearing instruction signal to an instruction input interface of a non-destructive readout register, wherein the non-destructive readout register outputs data to a first magnetic flux sub-separation device according to a high-frequency local clock signal, the first magnetic flux sub-separation device separates the output data into a zero clearing signal and a trigger signal, and inputs the zero clearing signal to a superconducting register between pipeline stages of a superconducting processor;
and 3, outputting a signal pulse by the first D trigger according to the trigger signal and the first low-frequency system clock pulse, outputting a delay pulse by the second magnetic flux sub-separation device according to the signal pulse and the second low-frequency system clock pulse, and resetting the nondestructive reading register according to the delay pulse to stop outputting the zero clearing signal.
The zero clearing method of the superconducting circuit is characterized in that the high-frequency local clock signal provides a clock signal for a logic gate which adopts a traveling wave running water working mode in the superconducting processor.
The zero clearing method of the superconducting circuit is characterized in that the low-frequency system clock signal is a clock signal provided by a multistage pipeline circuit controlled by a superconducting register in a superconducting processor.
The time interval between the clear instruction signal and the high-frequency local clock signal is larger than the reaction time of the nondestructive read register to the clock signal.
The clearing method of the superconducting circuit is characterized in that the clearing instruction signal, the high-frequency local clock signal, the output data, the clearing signal, the trigger signal, the clearing signal, the low-frequency system clock signal, the first low-frequency system clock pulse and the second low-frequency system clock pulse are all single magnetic flux subpulses.
The invention also provides a zero clearing system of the superconducting circuit, which comprises the following components:
the module 1 sends a zero clearing instruction signal to an instruction input interface of a non-destructive readout register, the non-destructive readout register outputs data to a first magnetic flux sub-separation device according to a high-frequency local clock signal, the first magnetic flux sub-separation device separates the output data into a zero clearing signal and a trigger signal, and the zero clearing signal is input to a superconducting register between pipeline stages of a superconducting processor;
the module 2 inputs a low-frequency system clock signal to a second magnetic flux sub-separation device, and the second magnetic flux sub-separation device splits the low-frequency system clock signal into a first low-frequency system clock pulse and a second low-frequency system clock pulse;
the module 3 and the first D trigger output signal pulses according to the trigger signal and the first low-frequency system clock pulse, the second magnetic flux sub-separation device outputs delay pulses according to the signal pulses and the second low-frequency system clock pulse, and the nondestructive reading register resets according to the delay pulses to stop outputting the zero clearing signal.
The high-frequency local clock signal provides a clock signal for a logic gate which adopts a traveling wave running water working mode in the superconducting processor.
The low-frequency system clock signal is a clock signal provided by a multistage pipeline circuit controlled by a superconducting register in a superconducting processor.
The time interval between the clear instruction signal and the high-frequency local clock signal is larger than the reaction time of the nondestructive read register to the clock signal.
The zero clearing system of the superconducting circuit is characterized in that the zero clearing instruction signal, the high-frequency local clock signal, the output data, the zero clearing signal, the trigger signal, the zero clearing signal, the low-frequency system clock signal, the first low-frequency system clock pulse and the second low-frequency system clock pulse are single magnetic flux subpulses.
According to the scheme, the invention has the advantages that:
the zero clearing signal generating device designed by the invention can provide a practical zero clearing signal for the superconducting processor based on the multi-stage flowing water, and can effectively clear the superconducting registers between the flowing water stages in time under the abnormal conditions of instruction correlation, data correlation and the like of the superconducting processor pipeline so as to process the next instruction. The zero clearing signal required by the superconducting processor needs to be continuously generated according to a certain frequency, and a time period which is long enough is covered to ensure the zero clearing effect.
Drawings
FIG. 1 is a schematic diagram of a signal interface of a clear signal generator according to the present invention;
FIG. 2 is a timing diagram of the operation of the zero clearing signal generating device according to the present invention;
FIG. 3 is a schematic diagram of the internal combination of the clear signal generator according to the present invention.
Detailed Description
In the process of designing a pipeline-based superconducting processor, the inventor needs to provide a zero clearing signal which meets the timing requirement for a superconducting circuit register. There is no practical zero clearing signal generator in the prior art. Therefore, the invention is used in the design of the superconducting circuit, and provides a specific zero clearing signal generating device and a method which meet the actual working time sequence requirement of the superconducting circuit for the superconducting register after obtaining a zero clearing instruction signal.
The invention comprises the following key points:
the key point 1 is that the zero clearing signal generating device comprises a zero clearing instruction signal input port, a high-frequency local clock input port, a low-frequency system clock input port and a zero clearing signal output port;
the key point 2, after receiving a clear instruction signal, the clear signal generating device starts to output a clear signal at a clear signal output port according to the high-frequency local clock frequency;
the key point 3 is that the zero clearing output signal starts from the receipt of the zero clearing instruction signal until the end of covering the next complete low-frequency system clock cycle;
key point 4, one implementation of the zero clearing signal generating means is based on the existing superconducting circuit element composition;
at the key point 5, the clear signal generating device is used for a superconducting fast single-flux sub-circuit, and in the superconducting circuit related to the patent, the input and output signals of the logic gate and the clock signal for driving the circuit to work are single-flux sub-pulses.
In order to make the aforementioned features and effects of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
The zero clearing signal generating device provided by the invention comprises at least three signal input ports and one signal output port. The system comprises a zero clearing instruction signal input port, a high-frequency local clock input port, a low-frequency system clock input port and a zero clearing signal output port. For a superconducting circuit, the input and output signals are single magnetic flux sub-pulses. A schematic diagram of the component signal interface is shown in fig. 1.
The zero clearing signal generating device provided by the invention has the working effects that after a zero clearing instruction signal is received, the zero clearing signal is started to be output at the zero clearing signal output port according to the high-frequency local clock frequency, and the zero clearing output signal is generated from the zero clearing instruction signal until the next complete low-frequency system clock period is covered. Particularly, when the clear instruction signal and the low-frequency system clock signal arrive at the same time, two low-frequency system clock cycles are continuously output according to the time sequence relation of the actual physical circuit. The timing relationship in operation is shown in fig. 2. Each black triangle in fig. 2 represents a single flux quantum pulse. The signal is generated by a system control circuit, for example, a processor initialization signal, or when an abnormal interrupt occurs in the pipeline, a clear instruction is issued to the clear signal generation unit by the processor control unit.
The zero clearing signal output by the zero clearing signal output port is used for zero clearing the superconducting register between the pipeline stages of the superconducting processor, and in order to ensure the zero clearing effect, the signal output time length is greater than one low-frequency system clock period and less than two system clock periods. The clear output signal will be coupled to the reset signal interface of the superconducting register.
A concrete realization of the zero clearing signal generating device is based on the existing superconducting circuit components in the current superconducting circuit technology. The internal assembly diagram is shown in fig. 3. In this implementation, the device uses two flux splitter devices (splitter SPLs), two D flip-flops (data flip-flop DFFs), and a non-destructive read-out NDRO. In this implementation, the clock input port of the NDRO logic gate is connected to the high frequency local clock, the data input port of the NDRO logic gate is connected to the clear command signal line, the data output port of the NDRO logic gate is connected to an SPL device S1, one of the two output ports of S1 is a clear signal output port, and the other is connected to the first DFF logic gate D1. The output of D1 is coupled to the input of a second DFF logic gate D2. The output of D2 is connected to the reset port reset of the NDRO logic gate. The input port of another SPL device S2 is connected with the low frequency system clock signal, and the two output ports are respectively connected with the clock signals of D1 and D2. The NDRO register operates to output a stored state as a magnetic flux quantum pulse signal after each clock signal arrives. If the register stores state 1, the SFQ pulse is continuously output according to the clock signal. If state 0, then no pulse is issued. In the invention, after the first clear instruction is issued, the NDRO becomes state 1, and after one system clock period, the NDRO is reset to state 0. The SPL is a divider, one signal in and then two signals out simultaneously. Here, the input signal of the SPL device S1 is the output pulse of the NDRO. Then the signal is divided into two parts, and one output is the output port of the whole zero clearing signal device. The other is referred to as the second output port, and the signal is not output to the outside of the device, but is input to the inside of the DFF inside the device, and is used to clear the status of the NDRO. Allow NDRO to reset one system clock cycle later. S2 is another SPL element, which is used to process the clock signal. Whether the input is the system clock, the output is the system clock, because each DFF flip-flop needs to be clocked, the two output signals of S2 are the clocks provided to the two DFFs.
All "signals" in this invention refer to magnetic flux quantum pulses. But the function is different at different places. Some are clock signals and some are data signals. The superconducting circuit operates by these magnetic flux pulses. There is no conventional level signal.
However, the magnetic flux pulse in the superconducting SFQ circuit cannot be directly divided into two and three parts, as in the electrical signal in the normal circuit, and therefore an element such as SPL is required to divide one pulse into two.
The NDRO logic gate operates such that if a signal is input to din input, a pulse signal is output from dout output after each subsequent clock signal. Until the reset port has a reset signal input, then the dout port no longer continues to output with the clock signal.
The working principle of the SPL separator is that after a signal is input at an input port, pulse signals are respectively output at two signal output ports. Wherein the time delay between the input and output signals and the time delay between the two output signals is dependent on the process of the specific implementation.
The working principle of the DFF flip-flop is that before a clock signal arrives, if a din signal input port has a signal input, a dout output end outputs a pulse signal after the clock arrives. On the contrary, if the signal input port has no signal input, the output port does not output signals after the clock arrives.
In particular, it is within the scope of the invention to implement the function of the clearing device using other superconducting element combinations or using a single component.
The following example describes the operation of the zero clearing device in fig. 3 in detail:
step 1: the high-frequency local clock signal is continuously input, and the clock signal provides a high-frequency clock for a logic gate which adopts a travelling wave running water working mode in the superconducting processor.
Step 2: the low frequency system clock signal is input continuously and provides low frequency clock for the superconductive processor with the multistage pipeline circuit controlled with superconductive register. Each cycle of the clock is an instruction pipeline cycle. Each low frequency system clock cycle therefore contains several high frequency local clock cycles.
And step 3: the clear instruction input port waits for the arrival of a clear instruction signal.
And 4, step 4: if a single magnetic flux quantum pulse is input into the zero clearing instruction input port, the zero clearing signal output port outputs a single magnetic flux quantum pulse after each next high-frequency local clock signal arrives.
And 5: after the zero clearing signal output port starts to continuously output the single magnetic flux quantum pulse, waiting for the low-frequency system clock to input a first pulse signal, continuously outputting the zero clearing signal at the moment, waiting for the low-frequency system clock to input a second pulse signal, and stopping outputting the pulse signal by the zero clearing signal port after the work delay of the device.
Step 6: and (4) the superconducting circuit zero clearing device returns to the step 1 to continuously wait for the input of the zero clearing command signal.
And 7: the low frequency system clock and the high frequency local clock pulses do not require simultaneous arrival.
And 8: after the low frequency system clock input is split into S2 signals, it is not required to arrive at the clock signal input terminals of D1 and D2 exactly at the same time, but after a low frequency system clock pulse X1 arrives, if there is a signal input at the input terminal of D1, X1 will trigger D1 to output a signal pulse DATA1, which is input to the input terminal of D2, and for D2, DATA1 is required to arrive later than the clock pulse X1. Thus, after waiting for the next low frequency clock pulse X2 to arrive, D2 outputs the signal DATA2 to the reset port of NDRO. Therefore, the reset signal is sent out after delaying for more than one low-frequency system clock period, and the time span of the output of the zero clearing signal is ensured to be more than one low-frequency system clock period.
And step 9: the zero clearing instruction input signal and the high-frequency local clock input signal meet the working timing relation of the NDRO logic gate, the time interval between the zero clearing instruction input signal and the high-frequency local clock input signal is larger than the reaction time of the NDRO to the clock signal so as to ensure that the input instruction signal is effective, and the NDRO ensures that the output end has signal output after a zero clearing instruction input signal pulse arrives.
Step 10: the input interval of two adjacent clear command signals is required to be longer than the processing time of the internal signals of the equipment, for example, after the first clear command is input, the feedback signal output by the D2 reaches the reset port of the NDRO after the input of the subsequent two low-frequency system clock signals, and the NDRO does not output signals after the input of the subsequent high-frequency local clock. The second clear instruction requires input after completion of the one duty cycle to avoid timing confusion.
The following are system examples corresponding to the above method examples, and this embodiment can be implemented in cooperation with the above embodiments. The related technical details mentioned in the above embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
The invention also provides a zero clearing system of the superconducting circuit, which comprises the following components:
the module 1 sends a zero clearing instruction signal to an instruction input interface of a non-destructive readout register, the non-destructive readout register outputs data to a first magnetic flux sub-separation device according to a high-frequency local clock signal, the first magnetic flux sub-separation device separates the output data into a zero clearing signal and a trigger signal, and the zero clearing signal is input to a superconducting register between pipeline stages of a superconducting processor;
the module 2 inputs a low-frequency system clock signal to a second magnetic flux sub-separation device, and the second magnetic flux sub-separation device splits the low-frequency system clock signal into a first low-frequency system clock pulse and a second low-frequency system clock pulse;
the module 3 and the first D trigger output signal pulses according to the trigger signal and the first low-frequency system clock pulse, the second magnetic flux sub-separation device outputs delay pulses according to the signal pulses and the second low-frequency system clock pulse, and the nondestructive reading register resets according to the delay pulses to stop outputting the zero clearing signal.
The high-frequency local clock signal provides a clock signal for a logic gate which adopts a traveling wave running water working mode in the superconducting processor.
The low-frequency system clock signal is a clock signal provided by a multistage pipeline circuit controlled by a superconducting register in a superconducting processor.
The time interval between the clear instruction signal and the high-frequency local clock signal is larger than the reaction time of the nondestructive read register to the clock signal.
The zero clearing system of the superconducting circuit is characterized in that the zero clearing instruction signal, the high-frequency local clock signal, the output data, the zero clearing signal, the trigger signal, the zero clearing signal, the low-frequency system clock signal, the first low-frequency system clock pulse and the second low-frequency system clock pulse are single magnetic flux subpulses.
Claims (10)
1. A method for zeroing a superconducting circuit, comprising:
step 1, sending a zero clearing instruction signal to an instruction input interface of a non-destructive readout register, wherein the non-destructive readout register outputs data to a first magnetic flux sub-separation device according to a high-frequency local clock signal, the first magnetic flux sub-separation device separates the output data into a zero clearing signal and a trigger signal, and inputs the zero clearing signal to a superconducting register between pipeline stages of a superconducting processor;
step 2, inputting a low-frequency system clock signal to a second magnetic flux sub-separation device, wherein the second magnetic flux sub-separation device splits the low-frequency system clock signal into a first low-frequency system clock pulse and a second low-frequency system clock pulse;
and 3, outputting a signal pulse by the first D trigger according to the trigger signal and the first low-frequency system clock pulse, outputting a delay pulse by the second D trigger according to the signal pulse and the second low-frequency system clock pulse, and resetting the nondestructive reading register according to the delay pulse to stop outputting the zero clearing signal.
2. The method of claim 1, wherein the high frequency local clock signal provides a clock signal to a logic gate in a superconducting processor operating in a traveling wave pipeline mode.
3. The method of claim 1, wherein the low frequency system clock signal is a clock signal provided by a multi-stage pipeline circuit controlled by a superconducting register in the superconducting processor.
4. The method of clearing a superconducting circuit of claim 1 wherein the time interval between the clear command signal and the high frequency local clock signal is greater than the reaction time of the non-destructive read register to the clock signal.
5. The method of clearing a superconducting circuit as claimed in claim 1, wherein the clear command signal, the high frequency local clock signal, the output data, the clear signal, the trigger signal, the clear signal, the low frequency system clock signal, the first low frequency system clock pulse and the second low frequency system clock pulse are all single flux sub-pulses.
6. A zero clearing system for a superconducting circuit, comprising:
the module 1 sends a zero clearing instruction signal to an instruction input interface of a non-destructive readout register, the non-destructive readout register outputs data to a first magnetic flux sub-separation device according to a high-frequency local clock signal, the first magnetic flux sub-separation device separates the output data into a zero clearing signal and a trigger signal, and the zero clearing signal is input to a superconducting register between pipeline stages of a superconducting processor;
the module 2 inputs a low-frequency system clock signal to a second magnetic flux sub-separation device, and the second magnetic flux sub-separation device splits the low-frequency system clock signal into a first low-frequency system clock pulse and a second low-frequency system clock pulse;
the module 3 and the first D trigger output signal pulses according to the trigger signal and the first low-frequency system clock pulse, the second D trigger outputs delay pulses according to the signal pulses and the second low-frequency system clock pulse, and the nondestructive reading register resets according to the delay pulses to stop outputting the zero clearing signal.
7. The zeroing system for a superconducting circuit of claim 6, wherein the high frequency local clock signal provides a clock signal for logic gates in a superconducting processor that operates in a traveling wave pipeline mode.
8. The zero clearing system for superconducting circuit of claim 6 wherein the low frequency system clock signal is a clock signal provided by a multi-stage pipeline circuit in the superconducting processor controlled by the superconducting registers.
9. The zero clearing system for superconducting circuits of claim 6 wherein the time interval between the zero clearing command signal and the high frequency local clock signal is greater than the reaction time of the non-destructive read register to the clock signal.
10. The zero clearing system for a superconducting circuit of claim 6, wherein the zero clearing command signal, the high frequency local clock signal, the output data, the zero clearing signal, the trigger signal, the zero clearing signal, the low frequency system clock signal, the first low frequency system clock pulse and the second low frequency system clock pulse are all single flux sub-pulses.
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| CN112114875B (en) * | 2020-08-27 | 2023-06-02 | 中国科学院计算技术研究所 | Superconducting parallel register file device |
| CN112116094B (en) * | 2020-08-27 | 2022-08-30 | 中国科学院计算技术研究所 | Superconducting pipeline circuit and processor |
| CN113065301A (en) * | 2021-04-20 | 2021-07-02 | 中国科学院上海微系统与信息技术研究所 | Method for increasing working range of superconducting integrated circuit |
| CN113128172B (en) * | 2021-04-23 | 2023-10-27 | 中国科学院计算技术研究所 | Superconducting register file device and control method thereof |
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