TWI751796B - Processor that can directly start output by external signal - Google Patents

Abstract

The present invention is a processor that can be directly activated and output by an external signal, mainly consisting of an input unit. unit, an output unit and a timing counting control module, and the timing counting control module is electrically connected with the input unit and the output unit, wherein a trigger signal is obtained from the input unit, and the timing counting control module The output unit is controlled to output a programmable pulse signal according to the trigger signal, whereby the processor can instantly generate and output the programmable pulse signal according to the trigger signal without passing through the internal core logic block, so as to improve the control accuracy the goal of.

Description

The output processor can be directly activated by an external signal

The present invention relates to a processor, especially a processor whose output can be directly activated by an external signal.

Generally speaking, processors such as Micro Processing Unit (MPU) and Micro Control Unit (MCU) are usually composed of internal core logic blocks, peripheral function blocks and input and output interfaces. As shown in FIG. 5, a known processor 600 includes an internal core logic block 610 (operation logic unit 611), a peripheral function block 620 (timer counter 621, program memory 622, register 623) and an input and output interface 630 (input port 631, output port 632), the processor 600 controls the operation of the peripheral functional block 620 and the input and output interface 630 through the internal core logic block 610. transmitted or received signals. In order to optimize the performance of the processor 600, usually the processor 600 further includes an interrupt generator 640, and the interrupt generator 640 is used to cause the processor 600 to interrupt the execution of the existing program, and then execute another program, and then Continue the execution of the existing program after completing the execution of another program, by interrupting the operation without waiting for the completion of the existing program.

However, although the known processor has introduced the operation mode of the interrupt operation, the known processor still needs to wait for dozens of clock cycles before outputting the required signal, that is, the existing interrupt operation still causes the signal output to fail. delay, therefore, the need for a better solution is really pending.

In view of the above-mentioned deficiencies of the prior art, the main purpose of the present invention is to provide a processor that can be directly activated and output by an external signal, which can generate a programmable signal according to an external trigger signal without going through the internal core logic block of the processor. Pulse signal, thereby achieving the purpose of improving the control accuracy.

The main technical means adopted to achieve the above purpose is to make the aforementioned processor whose output can be directly activated by an external signal to include: an input unit; an output unit; a timing counting control module, which is electrically connected to the input unit and the output unit , a register, electrically connected with the timing counting control module; and an internal core logic block, electrically connected with the register; wherein, a trigger signal is obtained from the input unit, the timing counting control module The group controls the output unit to output a programmable pulse signal according to the trigger signal, and the processor does not use the internal core logic block to control the output unit to output the programmable pulse signal.

With the above structure, the timing count control module can generate the programmable pulse signal according to the trigger signal, so that the processor can generate the programmable pulse signal according to the external trigger signal without waiting for the operation of the internal core logic block. Programmable pulse signal to achieve the purpose of improving control accuracy.

10: Input unit

20, 20a, 20b: timing counting control module

21: Flip-flop

22: The first logic gate

221: the first input terminal

222: The second input terminal

223: output terminal

23: The second logic gate

231: the first input

232: the second input

233: output terminal

24: Timing counting unit

30: Output unit

40, 40a, 40b: scratchpad

50: Internal core logic block

100, 100': Processor

600: Processor

610: Internal core logic block

611: Operational logic unit

620: Peripheral functional blocks

621: timer counter

622: Program memory

623: Scratchpad

630: Input and output interface

631: input port

632: Lost port

640: Interrupt Generator

CLK: clock input terminal

Clock: Internal clock signal

D: input terminal

event: overflow signal

gated clock: gated clock signal

ONtrigger: trigger signal

ONlatch: Latch signal

Pprogram: Programmable pulse signal

Q: output terminal

R: reset terminal

D-FF Reset: reset signal

S: setting terminal

Ta, Ta1, Tb, Tc, Tc1: time point

Vh: logic high potential

FIG. 1 is a block diagram of a system architecture according to an embodiment of the present invention.

FIG. 2 is a block diagram of yet another system architecture according to an embodiment of the present invention.

FIG. 3 is a structural block diagram of an embodiment of the timing counting control module of the present invention.

FIG. 4 is a timing diagram of an embodiment of the present invention.

FIG. 5 is a schematic diagram of a system architecture of a known processor.

For an embodiment of the present invention, the processor that can be directly activated and output by an external signal, please refer to FIG. 1 , the processor 100 at least includes an input unit 10 , a timing counting control module 20 , an output unit 30 , a temporary memory 40 and an internal core logic block 50 . The input unit 10 is used for receiving a trigger signal ONtrigger. The timing counting control module 20 is electrically connected to the input unit 10 for receiving the trigger signal ONtrigger through the input unit 10 , the output unit 30 is electrically connected to the timing counting control module 20 , and the output unit 30 uses To output a programmable pulse signal Pprogram generated by the timing counting control module 20, the register 40 is electrically connected with the timing counting control module 20, and the internal core logic block 50 is electrically connected with the register 40 connect. In other words, the timing control module 20 is used for controlling the output unit 30 to output the programmable pulse signal Pprogram according to the trigger signal ONtrigger. In this way, the processor 100 can generate the programmable pulse signal Pprogram in real time according to the external trigger signal ONtrigger and the timing counting control module 20 without waiting for the operation of the internal core logic block 50 to avoid the internal The delay caused by the core logic block 50 achieves the purpose of improving precise control.

In one embodiment, the trigger signal is an internal trigger signal of the processor 100 or an external trigger signal received by an external circuit of the processor 100 .

In one embodiment, the processor 100 can be implemented as a controller applied to a switching power converter, a motor drive controller or an automatic response controller, and the present invention is not limited thereto.

In one embodiment, the input unit 10 and the output unit 30 are input and output ports of the processor 100 .

In one embodiment, the programmable pulse signal Pprogram is a pulse width modulation signal, a clock signal or a single shot signal, and the invention is not limited thereto.

In one embodiment, in order to match the circuit design, the processor 100 can be further configured with a plurality of timing counting control modules. As shown in FIG. 2, in this embodiment, a processor 100' can be configured with two timing counting control modules (ie, the timing counting control module 20a and a timing counting control module 20b). The group 20a is electrically connected to a register 40a, the timing counting control module 20b is electrically connected to a register 40b, the register 40a, the register 40b and the internal core logic block 50 are electrically connected connection, and in this embodiment, the timing counting control module 20b can be used to realize the function of signal delay or counting, and the present invention is not limited thereto.

In another embodiment, the timing and counting control module 20a can also be used to realize the function of signal delay to delay the trigger signal ONtrigger, and then the timing and counting control module 20b can be used to generate the programmable pulse signal Pprogram, and the present invention Not limited by this.

To further illustrate the timing counting control module 20 of the present invention, please refer to FIG. 3 , which at least includes a flip-flop 21 , a first logic gate 22 , a second logic gate 23 and a timing counting unit 24 , The flip-flop 21 is electrically connected to the first logic gate 22 , the first logic gate 22 is electrically connected to the second logic gate 23 , the timing counting unit 24 is electrically connected to the first logic gate 22 and the second logic gate 22 The logic gate 23 is electrically connected, wherein the embodiment disclosed in FIG. 3 is only used as an example, and is not used to limit the present invention.

Further, the flip-flop 21 has an input terminal D, an output terminal Q, a clock input terminal CLK, a setting terminal S and a reset terminal R. The input terminal D and the setting terminal S are used to receive a logic high level Vh, the clock input terminal CLK is used to receive the trigger signal ONtrigger, the output terminal Q is used to output a latch signal ONlatch, the reset terminal R It is used to receive a reset signal D-FF Reset. Therefore, the flip-flop 21 is used to be triggered by the trigger signal ONtrigger and change the state of the latch signal ONlatch (for example, from a low voltage level to a high voltage level) ), and is used to change the state of the latch signal ONlatch according to the reset signal D-FF Reset (eg, from a high voltage level to a low voltage level).

In one embodiment, the flip-flop is a D-type flip-flop, and the present invention is not limited thereto.

The first logic gate 22 has a first input terminal 221, a second input terminal 222 and an output terminal 223. The first input terminal 221 is electrically connected to the timing counting unit 24 for receiving an overflow signal event , the second input end 222 is electrically connected to the output end Q of the flip-flop 21 and receives the latch signal ONlatch, the output end 223 is used for outputting the programmable pulse signal Pprogram, the first logic gate 22 is used for The programmable pulse signal Pprogram is generated according to the overflow signal event and the latch signal ONlatch.

The second logic gate 23 has a first input terminal 231, a second input terminal 232 and an output terminal 233. The first input terminal 231 is used for receiving an internal clock signal Clock. The second input terminal 232 is connected to the The output terminal 223 of the first logic gate 22 is electrically connected to receive the programmable pulse signal Pprogram, and the output terminal 233 is electrically connected to the timing counting unit 24 for outputting a gated clock signal to the timing counting The clock input end of the unit 24, the second logic gate 23 is used for generating the gated clock signal gated clock according to the internal clock signal Clock and the programmable pulse signal Pprogram.

In an embodiment, the first logic gate 22 and the second logic gate 23 can be implemented by AND gates, and the present invention is not limited thereto.

Further, the overflow signal event is a control signal generated when the timing counting unit 24 counts up or down when an overflow occurs. For example, in hexadecimal, when the timing counting unit 24 counts up and overflows by counting up from FFFF, the overflow signal event is generated.

In one embodiment, the overflow signal event is a signal triggered by a low level, that is, when the overflow signal event is converted from a high voltage level to a low voltage level, the corresponding circuit is made to perform a corresponding action.

The operation method of the timing counting control module 20 will be described below with reference to FIG. 4 and the aforementioned timing counting control module 20 as an example. It should be noted that the following high voltage level and low voltage level are only In order to illustrate the present invention, but not to limit the present invention, those skilled in the art to which the present invention pertains can alternatively use a high voltage level or a low voltage level to complete the present invention according to their needs. Please refer to FIG. 3 and FIG. 4 at the same time. First, at time point Ta, the trigger signal ONtrigger is converted from a low voltage level to a high voltage level, so the flip-flop 21 is driven to make the latch signal ONlatch from a low voltage level. The bit is converted to a high voltage level, and at the same time, because the overflow signal event is a high voltage level, the programmable pulse signal Pprogram is converted from a low voltage level to a high level due to the latch signal ONlatch and the overflow signal event. At the same time, through the internal clock signal Clock and the programmable pulse signal Pprogram, the corresponding gated clock signal is generated. At time Ta1, the trigger signal ONtrigger is converted from a high voltage level to a low voltage level, and the latch signal ONlatch, the overflow signal event, the programmable pulse signal Pprogram and the reset signal D-FF Reset remain unchanged . At the time point Tb, the latch signal ONlatch still maintains a high voltage level, the overflow signal event is converted from a high voltage level to a low voltage level, so the programmable pulse signal Pprogram is converted from a high voltage level to a low voltage level. bit. At time point Tc, the reset signal D-FF Reset is converted from a high voltage level to a low voltage level, the flip-flop 21 is reset, so the latch signal ONlatch is converted from a high voltage level to a low voltage level and a high voltage level . At time point Tc1, the reset signal Reset goes from low The voltage level is converted to a high voltage level. Here, an operation cycle is completed, and the timing control module 20 returns to the initial state to wait for the next trigger signal ONtrigger.

In this embodiment, the timing counting control module 20 not only generates the programmable pulse signal Pprogram according to the trigger signal ONtrigger, but also generates the gated clock signal gated clock which is the clock signal of the timing counting unit 24, In other words, the timing control module 20 generates one or more pulse signals according to the trigger signal ONtrigger.

In another embodiment, the actions of the timing counting unit 24 may be synchronized by enabling/halt the counting of the timing counting unit 24 .

In another embodiment, the timing counting control module 20 may include two timing counting units (24A, 24B), and the timing counting units (24A, 24B) have a counting start difference value (for example: timing The count value of the counting unit 24B is greater than that of the counting unit 24A), so that the counting units (24A, 24B) count simultaneously with the same clock, and the trigger signal ONtrigger directly latches the value of the counting unit 24B at that time, and Compared with the value of the timing counting unit 24A, when the timing counting unit 24A catches up with the timing counting unit 24B, the overflow signal event is generated.

To sum up, because the timing control module 20 of the present invention can generate the programmable pulse signal Pprogram in real time according to the trigger signal ONtrigger, the processor 100 does not need to perform operations through the internal core logic block 50, Influenced by the capability or delay of the internal core logic block 50, the programmable pulse signal Pprogram required by the peripheral circuit can be quickly and accurately generated, so as to realize the function of controlling the high-level system with a low-level processor, which not only reduces the system control cost, And achieve the purpose of improving the control accuracy.

10: Input unit

20: Timing count control module

30: Output unit

40: Scratchpad

50: Internal core logic block

100: Processor

ONtrigger: trigger signal

Pprogram: Programmable pulse signal

Claims (14)

A processor whose output can be directly activated by an external signal, comprising: an input unit to obtain a trigger signal; an output unit; a first timing counting control module electrically connected with the input unit and the output unit, the first A timing counting control module further includes: a flip-flop, which has a clock input terminal, an output terminal and a reset terminal, the clock input terminal receives the trigger signal, the output terminal outputs a latch signal, the The reset terminal receives a reset signal; a register is electrically connected to the first timing counting control module; and an internal core logic block is electrically connected to the register; wherein the first timing The flip-flop of the counting control module outputs the latch signal according to the trigger signal to control the output unit to output a programmable pulse signal, wherein the processor does not use an internal core logic block to control the output unit Output the programmable pulse signal. The processor of claim 1, wherein the processor further comprises: a second timing counting control module, which is electrically connected to the first timing counting control module and the output unit, and is disposed in the first timing counting control module Between a timing counting control module and the output unit; and a second register, electrically connected to the second timing counting control module and the internal core logic block, and configured in the second timing counting control module module and this internal core logic block. The processor of claim 1, wherein the timing counting control module further comprises: a first logic gate having a first input end, a second input end and an output end, the first input end receiving an overflow signal, the second input terminal is electrically connected to the output terminal of the flip-flop to receive the latch signal, the output terminal of the first logic gate outputs the programmable pulse signal; a second logic gate The gate has a first input end, a second input end and an output end, the first input end of the second logic gate receives an internal clock signal, the second input end of the second logic gate is connected to The input end of the first logic gate is electrically connected to receive the programmable pulse signal, the output end of the second logic gate outputs a gate-controlled clock signal; and a timing counting unit is connected with the first logic gate The first input terminal is electrically connected to the output terminal of the second logic gate. The processor of claim 3, wherein, at a first point in time, the trigger signal, the latch signal, the overflow signal, the reset signal and the programmable pulse signal are at a first voltage level ; At a second time point, the overflow signal is converted from the first voltage level to a second voltage level, the latch signal and the reset signal are the first voltage level, and the programmable pulse signal is composed of The first voltage level is converted to the second voltage level, and the trigger signal is the second voltage level; at a third time point, the reset signal and the latch signal are converted from the first voltage level to The second voltage level, the trigger signal, the programmable pulse signal, and the overflow signal are the second voltage level, wherein the first time point is earlier than the second time point, and the second time point is earlier than the third time. The processor of claim 4, wherein at a fourth time point, the trigger signal is converted from the first voltage level to the second voltage level, the fourth time point is later than the first time point and earlier at the second point in time. The processor of claim 5, wherein at a fifth time point, the reset signal is converted from the second voltage level to the first voltage level, and the fifth time point is later than the third time point. The processor of claim 4, 5 or 6, wherein the first voltage level is a high voltage level, and the second voltage level is a low voltage level. The processor of claim 3, wherein the flip-flop is a D-type flip-flop. The processor of claim 3, wherein the first logic gate and the second logic gate are a sum gate. The processor of claim 3, wherein the counting of the timing counting unit is controlled to synchronize the actions of the timing counting unit. The processor of claim 3, wherein the timing counting control module includes two timing counting units, the timing counting units have a count start difference value from each other, and the timing counting units are latched by the trigger signal The value of one of the timing counting units generates the overflow signal when the other one of the timing counting units catches up with the value of one of the timing counting units. The processor of claim 1, wherein the trigger signal is an external trigger signal from outside the processor. The processor of claim 1, wherein the programmable pulse signal is a pulse width modulation signal, a clock signal or a click signal. The processor of claim 1, wherein the timing count control module generates a plurality of pulse signals including the programmable pulse signal according to the trigger signal.

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