CN111081646A - Stack packaging structure and manufacturing method thereof - Google Patents
Stack packaging structure and manufacturing method thereof Download PDFInfo
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- CN111081646A CN111081646A CN201911355283.0A CN201911355283A CN111081646A CN 111081646 A CN111081646 A CN 111081646A CN 201911355283 A CN201911355283 A CN 201911355283A CN 111081646 A CN111081646 A CN 111081646A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052802 copper Inorganic materials 0.000 claims abstract description 37
- 239000010949 copper Substances 0.000 claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 235000012431 wafers Nutrition 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 16
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 45
- 238000000465 moulding Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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Abstract
The invention discloses a stack packaging structure, comprising: a first carrier plate; the chip embedding groove is arranged on the front surface of the first carrier plate; the first carrier plate through window penetrates through the upper surface and the lower surface of the first carrier plate and is isolated from the chip embedded groove; the chip is arranged in the chip embedding groove with the front side facing upwards; the second carrier plate is arranged on the back surface of the first carrier plate; the giant copper column is arranged on the upper surface of the second carrier plate and extends into the first carrier plate through window; and the plastic packaging layer covers the front surface of the first carrier plate and fills a gap between the giant copper column and the first carrier plate through window and a gap between the chip and the chip embedding groove. The layout wiring layer is arranged above the plastic packaging layer and is electrically connected to the chip bonding pad and the giant copper pillar; and the external solder balls are arranged above the layout wiring layer and are electrically connected to the layout wiring layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level stacked packaging structure and a manufacturing method thereof.
Background
With the continuous development of microelectronic technology, users have higher and higher requirements on miniaturization, multiple functions, low power consumption and high reliability of systems, and especially in recent years, blowout required by portable handheld terminal markets, such as portable computers, smart phones, tablet computers and the like, has higher integration level and interconnection capacity. Three-dimensional stack packaging is a very effective technical approach to meet the above requirements.
In the existing wafer-level three-dimensional stacked package structure, a highly difficult TSV structure is generally required to be manufactured, and the process is complex and the cost is high. In addition, the single-sided plastic package assisted by the carrier plate easily causes warpage due to the difference of the stress of the plastic package material and the stress of the wafer, so that the reliability of the packaging structure is affected.
Aiming at the problems of complex process, high cost and the like of the conventional wafer-level three-dimensional stacked packaging structure due to a high-difficulty TSV structure, the invention provides a wafer-level stacked packaging structure and a manufacturing method thereof.
Disclosure of Invention
In order to solve the problem of package structure warpage caused by different materials on the upper and lower surfaces of the conventional three-dimensional package on package structure, according to an embodiment of the present invention, a package on package structure is provided, which includes:
a first carrier plate;
the chip embedding groove is arranged on the front surface of the first carrier plate;
the first carrier plate through window penetrates through the upper surface and the lower surface of the first carrier plate and is isolated from the chip embedded groove;
the chip is arranged in the chip embedding groove with the front side facing upwards;
the second carrier plate is arranged on the back surface of the first carrier plate;
the giant copper column is arranged on the upper surface of the second carrier plate and extends into the first carrier plate through window;
and the plastic packaging layer covers the front surface of the first carrier plate and fills a gap between the giant copper column and the first carrier plate through window and a gap between the chip and the chip embedding groove.
The layout wiring layer is arranged above the plastic packaging layer and is electrically connected to the chip bonding pad and the giant copper pillar; and
and the external solder balls are arranged above the layout wiring layer and are electrically connected to the layout wiring layer.
In one embodiment of the invention, the inner wall of the chip embedding groove is also provided with a signal shielding structure.
In an embodiment of the invention, the top view pattern of the through windows of the first carrier is rectangular or circular or an array thereof.
In one embodiment of the invention, the chip is pasted with the back surface to the bottom of the chip embedding groove through the pasting glue.
In an embodiment of the invention, the bonding pads of the chip and the top surfaces of the giant copper pillars are lower than the front surface of the first carrier.
In an embodiment of the invention, the bonding pads of the chip and the top surfaces of the giant copper pillars are higher than the front surface of the first carrier.
In an embodiment of the present invention, an interconnection line and/or an active device and/or a passive device is further disposed in the second carrier board.
In one embodiment of the invention, the package on package structure is a package structure formed by wafer level stacking.
According to another embodiment of the present invention, a method for manufacturing a wafer level stack package structure is provided, including:
forming a chip embedding groove and a first carrier plate through window on a first carrier plate;
mounting a chip on the front surface in the chip embedding groove;
forming a huge copper column on the front surface of the second carrier plate;
aligning the back surface of the first carrier plate and the front surface of the second carrier plate and then bonding the wafers;
forming a plastic packaging layer covering the front surface of the first carrier plate through plastic packaging;
forming a layout wiring layer above the plastic packaging layer; and
and forming external solder balls on the layout wiring layer.
In another embodiment of the invention, after the back surface of the first carrier board is aligned with the front surface of the second carrier board, the huge copper pillar is located in the through window of the first carrier board; and the plastic packaging layer fills a gap between the giant copper column and the first carrier plate through window and a gap between the chip and the chip embedding groove.
The invention provides a wafer-level stacked packaging structure and a manufacturing method thereof, wherein a cavity capable of placing a chip is formed in a first carrier plate in advance, so that the height of the packaging structure is reduced; meanwhile, the shielding structure is arranged in the cavity, so that signal interference is reduced; forming a through hole/window in the first carrier plate; through the bonding of the second carrier plate and the first carrier plate, the matching of the conductive copper column of the second carrier plate and the through hole/window of the first carrier plate is realized, and the electric/signal interconnection is realized; and finally, forming integral plastic package, re-arranging wiring and externally connecting solder balls on the first carrier plate to form a final package structure. According to the wafer level stacked packaging structure and the manufacturing method thereof, the stacked packaging is realized through wafer bonding, the upper layer and the lower layer of signals are interconnected through the copper columns in the silicon grooves, the high-difficulty TSV process can be avoided, and therefore the cost is reduced; in addition, the warpage of the packaging structure is reduced by wafer-level bonding, the yield and reliability of products are improved, and the packaging capacity is improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional view of a wafer level stacked package structure 100 according to an embodiment of the invention.
Fig. 2A-2G illustrate a process of forming the wafer level stacked package structure 100 according to one embodiment of the invention.
Fig. 3 illustrates a flow diagram 300 for forming the wafer level stacked package structure 100 according to one embodiment of the invention.
Fig. 4 is a cross-sectional view of a wafer level stacked package structure 400 according to another embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a wafer-level stacked packaging structure and a manufacturing method thereof, wherein a cavity capable of placing a chip is formed in a first carrier plate in advance, so that the height of the packaging structure is reduced; meanwhile, the shielding structure is arranged in the cavity, so that signal interference is reduced; forming a through hole/window in the first carrier plate; through the bonding of the second carrier plate and the first carrier plate, the matching of the conductive copper column of the second carrier plate and the through hole/window of the first carrier plate is realized, and the electric/signal interconnection is realized; and finally, forming integral plastic package, re-arranging wiring and externally connecting solder balls on the first carrier plate to form a final package structure. According to the wafer level stacked packaging structure and the manufacturing method thereof, the stacked packaging is realized through wafer bonding, the upper layer and the lower layer of signals are interconnected through the copper columns in the silicon grooves, the high-difficulty TSV process can be avoided, and therefore the cost is reduced; in addition, the warpage of the packaging structure is reduced by wafer-level bonding, the yield and reliability of products are improved, and the packaging capacity is improved.
A wafer level stacked package structure according to an embodiment of the invention is described in detail below with reference to fig. 1. Fig. 1 is a cross-sectional view of a wafer level stacked package structure 100 according to an embodiment of the invention, as shown in fig. 1, the wafer level stacked package structure 100 further includes a first carrier 110, a chip burying groove 120, a first carrier through window 130, a chip 140, a second carrier 150, a giant copper pillar 160, a molding compound layer 170, a layout wiring layer 180, and an external solder ball 190.
The first carrier 110 is typically a wafer-level silicon carrier. In an embodiment of the invention, the first carrier 110 is a thinned wafer, and the thickness is 150 to 300 microns.
The chip embedding groove 120 is disposed on the front surface of the first carrier 110 and extends toward the interior of the first carrier 110. In one embodiment of the present invention, the chip burying groove 120 is a groove having a trapezoidal section with a depth of 100 to 200 μm. In another embodiment of the present invention, the chip embedding groove 120 may also be a vertical groove having a rectangular cross section. In another embodiment of the present invention, the inner wall of the chip burying groove 120 is further provided with a signal shielding structure, such as a metal wall.
The first carrier through window 130 penetrates through the upper and lower surfaces of the first carrier 110, and is precisely arranged at a specific position of the first carrier 110 by patterning. In one embodiment of the present invention, the first carrier through window 130 is a directional recess in a top view. In another embodiment of the present invention, the first carrier through window 130 is a circular through hole or another through hole. In another embodiment of the present invention, the first carrier through window 130 may also be a pattern array penetrating through the first carrier 110.
The chip 140 is arranged in the chip embedded groove 120 by positive mounting of the chip, the chip pad 245 of the chip 140 faces upward, and the back of the chip is fixed at the bottom of the chip embedded groove 120 by the chip adhesive. The chip 140 may be a logic processing chip such as a processor, an FPGA, and an MCU, or may also be a memory chip such as a DRAM, a FLASH, and an EPROOM, or other types of chips such as an SOC and a sensor.
The second carrier 150 is disposed on the back surface of the first carrier 110 in a bonding manner. The second carrier 150 may also be a wafer-level silicon carrier. In one embodiment of the present invention, the second carrier 150 is internally provided with an interconnection line 155. In yet another embodiment of the present invention, active or passive devices may also be included in the second carrier 150.
The giant copper pillar 160 is electrically connected to the interconnection 155 of the second carrier 150 and disposed in the first carrier through window 130.
The molding compound layer 170 covers the front surface of the first carrier 110, and fills the gap between the huge copper pillar 160 and the first carrier through window 130, and the gap between the chip 140 and the chip embedded groove 120. In one embodiment of the present invention, the material of the molding layer 170 is resin.
A layout wiring layer 180 is disposed over the molding layer 170, the layout wiring layer 180 being electrically connected to the chip pad 145 and the giant copper pillar 160. In one embodiment of the present invention, the wiring layer may be a single layer or multiple layers, wherein an interlayer conductive via is further provided between adjacent layers of the layout wiring layer 180 to implement electrical and/or signal interconnection, and an external connection pad (not shown) is further provided on the outermost layer of the layout wiring layer 180.
The external solder balls 190 are disposed on the layout wiring layer 180 and electrically connected to the layout wiring layer 180. In one embodiment of the present invention, the external solder balls 190 are formed by ball-mounting, plating, and the like, and may be lead-free solder balls or conductive copper pillars, which serve as electrical and/or signal interconnections between the package structure and external circuits and systems.
A method of forming the wafer level stacked package structure 100 according to an embodiment of the invention is described in detail below with reference to fig. 2A to 2D and fig. 3. Fig. 2A-2G illustrate a process of forming the wafer level stacked package structure 100 according to one embodiment of the invention; fig. 3 illustrates a flow diagram 300 for forming the wafer level stacked package structure 100 according to one embodiment of the invention.
First, in step 310, as shown in fig. 2A, the top view of fig. 2A is a top view, and the bottom view is a cross-sectional view, a chip-embedding groove 220 and a first carrier plate through-window 230 are formed on a first carrier plate 210, wherein the chip-embedding groove 220 is located on the front surface of the first carrier plate 210. In an embodiment of the present invention, the silicon wafer of the first carrier plate 210, the chip-embedding groove 220 and the first carrier plate through-hole 230 are respectively formed by a patterned etching. In one embodiment of the present invention, a signal shielding structure 225, such as a metal wall, is further disposed in the chip embedding recess 220.
Next, in step 320, as shown in fig. 2B, the chip 240 is mounted on the front surface in the chip embedding recess 220, with the chip pad 245 of the chip 240 facing upward. In one embodiment of the present invention, the chip 240 is attached to the bottom of the chip embedding groove 220 by attaching the chip 240 to the back surface thereof with a chip adhesive.
Then, in step 330, as shown in fig. 2C, a giant copper pillar 260 is formed on the front surface of the second carrier 250. In one embodiment of the present invention, the second carrier 250 has an interconnection 255 therein. In yet another embodiment of the present invention, the second carrier 250 may also have active or passive devices therein.
Next, in step 340, as shown in fig. 2D, after aligning the back surface of the first carrier 210 and the front surface of the second carrier 250, wafer bonding is performed, wherein the giant copper pillar 260 on the front surface of the second carrier 250 is located in the first carrier through window 230 of the first carrier 210. In an embodiment of the present invention, the bonding of the first carrier plate 210 and the second carrier plate 250 may be electrostatic bonding, or may be welding bonding through a welding material.
Then, in step 350, as shown in fig. 2E, a molding layer 270 covering the front surface of the first carrier 210 is formed by molding. The plastic layer 270 fills the gap between the giant copper pillar 260 and the through window 230 of the first carrier and the gap between the chip 240 and the chip embedding groove 220, and forms a plastic layer on the front surface of the first carrier 210.
Next, in step 360, as shown in fig. 2F, a layout wiring layer 280 is formed on the molding layer 270, and the layout wiring layer 280 is electrically connected to the chip pad 245 of the chip 240 and the giant copper pillar 260. In an embodiment of the present invention, the routing layer 280 may be a single layer or multiple layers, and the routing layer 280 further includes a planar routing layer and a vertical via interconnect, wherein an external connection pad is further disposed on the outermost routing layer. In one embodiment of the present invention, the corresponding layout wiring layer 280 may be formed by a patterned electroplating process.
Finally, in step 370, as shown in fig. 2G, external solder balls 290 are formed on the layout wiring layer 280, and the external solder balls 290 are electrically connected to the layout wiring layer 280. Specifically, the external solder balls 290 are formed by ball-mounting, electroplating, or other processes, and may be lead-free solder balls or conductive copper pillars, which serve as electrical and/or signal interconnections between the package structure and external circuits and systems.
A wafer level stacked package structure according to another embodiment of the invention will be described in detail with reference to fig. 4. Fig. 4 is a cross-sectional view of a wafer level stacked package structure 400 according to another embodiment of the invention. As shown in fig. 4, the wafer level stacked package structure 400 further includes a first carrier 410, a chip embedding recess 420, a first carrier through window 430, a chip 440, a second carrier 450, a macro copper pillar 460, a molding layer 470, a layout wiring layer 480, and external solder balls 490.
The wafer level stacked package structure 400 is different from the wafer level stacked package structure 100 described above only in that the bonding pads 445 of the chip 440 and the huge copper pillars 460 protrude to the upper surface of the first carrier 410. The thickness of the corresponding first carrier 410 can be thinner, and the etching of the first carrier through the window 430 is more convenient.
Based on the wafer level stacked packaging structure and the manufacturing method thereof provided by the invention, the height of the packaging structure is reduced by forming a cavity capable of placing a chip in the first carrier plate in advance; meanwhile, the shielding structure is arranged in the cavity, so that signal interference is reduced; forming a through hole/window in the first carrier plate; through the bonding of the second carrier plate and the first carrier plate, the matching of the conductive copper column of the second carrier plate and the through hole/window of the first carrier plate is realized, and the electric/signal interconnection is realized; and finally, forming integral plastic package, re-arranging wiring and externally connecting solder balls on the first carrier plate to form a final package structure. According to the wafer level stacked packaging structure and the manufacturing method thereof, the stacked packaging is realized through wafer bonding, the upper layer and the lower layer of signals are interconnected through the copper columns in the silicon grooves, the high-difficulty TSV process can be avoided, and therefore the cost is reduced; in addition, the warpage of the packaging structure is reduced by wafer-level bonding, the yield and reliability of products are improved, and the packaging capacity is improved.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A package on package structure comprising:
a first carrier plate;
the chip embedding groove is arranged on the front surface of the first carrier plate;
the first carrier plate through window penetrates through the upper surface and the lower surface of the first carrier plate and is isolated from the chip embedded groove;
the chip is arranged in the chip embedding groove with the front side facing upwards;
the second carrier plate is arranged on the back surface of the first carrier plate;
the giant copper column is arranged on the upper surface of the second carrier plate and extends into the first carrier plate through window;
and the plastic packaging layer covers the front surface of the first carrier plate and fills a gap between the giant copper column and the first carrier plate through window and a gap between the chip and the chip embedding groove.
The layout wiring layer is arranged above the plastic packaging layer and is electrically connected to the chip bonding pad and the giant copper pillar; and
and the external solder balls are arranged above the layout wiring layer and are electrically connected to the layout wiring layer.
2. The package on package structure of claim 1, wherein the inner wall of the chip embedding recess is further provided with a signal shielding structure.
3. The package on package structure of claim 1, wherein the first carrier through hole has a rectangular or circular top view or an array thereof.
4. The package on package structure of claim 1, wherein the die is mounted on its backside by a mounting adhesive to the bottom of the die embedding recess.
5. The package on package structure of claim 1, wherein the bonding pads of the chip and the top surface of the giant copper pillar are lower than the front surface of the first carrier.
6. The package on package structure of claim 1, wherein the bonding pads of the chip and the top surface of the giant copper pillar are higher than the front surface of the first carrier.
7. The package on package structure of claim 1, wherein the second carrier board further has interconnect lines and or active devices and or passive devices disposed therein.
8. The package on package structure of claim 1, wherein the package on package structure is a wafer level stack formed package structure.
9. A method for manufacturing a wafer level stack package structure comprises the following steps:
forming a chip embedding groove and a first carrier plate through window on a first carrier plate;
mounting a chip on the front surface in the chip embedding groove;
forming a huge copper column on the front surface of the second carrier plate;
aligning the back surface of the first carrier plate and the front surface of the second carrier plate and then bonding the wafers;
forming a plastic packaging layer covering the front surface of the first carrier plate through plastic packaging;
forming a layout wiring layer above the plastic packaging layer; and
and forming external solder balls on the layout wiring layer.
10. The method of claim 9, wherein the giant copper pillar is located in the through-hole of the first carrier after aligning the backside of the first carrier with the front side of the second carrier; and the plastic packaging layer fills a gap between the giant copper column and the first carrier plate through window and a gap between the chip and the chip embedding groove.
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| CN201911355283.0A CN111081646B (en) | 2019-12-25 | 2019-12-25 | Stack packaging structure and manufacturing method thereof |
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| CN201911355283.0A CN111081646B (en) | 2019-12-25 | 2019-12-25 | Stack packaging structure and manufacturing method thereof |
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| CN111081646A true CN111081646A (en) | 2020-04-28 |
| CN111081646B CN111081646B (en) | 2021-08-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471160A (en) * | 2021-06-29 | 2021-10-01 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| WO2023133977A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method for semiconductor structure |
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| CN111081646B (en) | 2021-08-10 |
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