CN109786362B

CN109786362B - External fan crystal grain laminated structure without welding pad and manufacturing method thereof

Info

Publication number: CN109786362B
Application number: CN201711119770.8A
Authority: CN
Inventors: 陈士弘
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2017-11-14
Filing date: 2017-11-14
Publication date: 2021-01-05
Anticipated expiration: 2037-11-14
Also published as: CN109786362A

Abstract

The invention discloses a pad-free outer fan crystal grain laminated structure, which comprises a first crystal grain positioned on a substrate; a first dielectric layer conformally covering the first crystal grain; a first redistribution layer on the first dielectric layer; a first plug electrically connecting the first die and the first redistribution layer; a first cover layer conformally covering the first circuit redistribution layer; the second crystal grain is attached to the first covering layer; a second dielectric layer conformally covering the second crystal grain; a second redistribution layer on the second dielectric layer; a second plug electrically connecting the second die and the second redistribution layer; a second cover layer conformally covering the second redistribution layer; the patterned conducting layer is positioned on the second covering layer; the interlayer connection structure connects the first redistribution layer and the second redistribution layer to the patterned conductive layer, respectively.

Description

External fan crystal grain laminated structure without welding pad and manufacturing method thereof

Technical Field

The invention relates to a three-dimensional packaging structure and a manufacturing method thereof. More particularly, to a bumpless fan-out chip stacking structure and a method for fabricating the same.

Background

As electronic products are required to be portable, have more high digital signal processing functions, higher storage capacity and flexibility, circuits with different functions (such as circuits with different functions of digital logic, memory, analog/radio frequency or others) and passive components (such as capacitors, resistors, connectors and antennas) need to be integrated to form a Multi-Chip Module (MCM). Particularly in applications in mobile communication electronic systems, integration of the circuitry on a Printed Circuit Board (PCB) is not allowed due to the low power and small volume of the unit components required. Accordingly, System-on-a-chip (SoC) and System In Package (SIP) technologies have been developed.

System-on-a-chip technology integrates a complete computer system (e.g., including a Central Processing Unit (CPU), memory, graphics processor, and peripheral circuits) into a single chip. With the rapid evolution of semiconductor technology from micro meter to nano meter, although the number of devices that can be accommodated in a single chip will increase, the development cost and time of a system-on-a-chip will rapidly increase due to the bottleneck of process scaling and the difficulty of heterogeneous integration.

The system-in-package technology integrates a plurality of packaged chips manufactured by different processes and materials to form a system. Although it has the advantages of miniaturization, Heterogeneous integration (Heterogeneous), system cost reduction, product time to market reduction, and product performance improvement. However, the substrates (substrates) of the individual packaged chips are connected by wire bonding or flip chip technology (flip chip) as an interconnection structure. Therefore, when the number of stacked chips in the system increases, the more wire bonding or pad space that needs to be reserved increases the package thickness and volume, which is not favorable for system miniaturization. In addition, since the flip chip technology uses the melted solder bumps to bond the packaged chips in the stacked layers, when the number of stacked chips in the system increases, not only a higher thermal budget (thermal budget) is required, but also the solder bumps of the packaged chips at the bottom of the stacked layers are subject to excessive thermal stress, which may cause overflow and damage, thereby causing system failure.

Therefore, there is a need to provide an advanced pad-less out-fan die stack structure and a method for fabricating the same to solve the problems of the prior art.

Disclosure of Invention

One embodiment of the present disclosure discloses a padless overlay structure for an outer fan die, comprising: the semiconductor device includes a substrate, a first die, a first dielectric Layer, a first Redistribution Layer (RDL), a first plug, a first cover Layer, a second die, a second dielectric Layer, a second RDL, a second plug, a second cover Layer, a patterned conductive Layer, and an interlayer connection structure. The first crystal grain is positioned on the substrate. A first dielectric layer conformally (conformally) covers the first die and contacts the substrate. The first circuit redistribution layer is located on the first dielectric layer. The first plug penetrates through the first dielectric layer to electrically connect the first die and the first redistribution layer. The first covering layer conformally covers the first redistribution layer and is in contact with the first dielectric layer. The second die is attached to the first cap layer. The second dielectric layer conformally covers the second crystal grains and is in contact with the first covering layer. The second redistribution layer is disposed on the second dielectric layer. The second plug penetrates through the second dielectric layer to electrically connect the second grain and the second circuit redistribution layer. The second covering layer conformally covers the second circuit redistribution layer and is in contact with the second dielectric layer. The patterned conductive layer is located on the second covering layer. The interlayer connection structure connects the first redistribution layer and the second redistribution layer to the patterned conductive layer, respectively.

Another embodiment of the present disclosure discloses a method for manufacturing a pad-less out-fan die stack structure, comprising the following steps: first, a substrate is provided, and at least one first die is fixed on the substrate. Forming a first dielectric layer conformally covering the first crystal grains and contacting the substrate; forming a first redistribution layer on the first dielectric layer; at least one first plug is formed through the first dielectric layer to electrically connect the first die and the first redistribution layer. And forming a first covering layer conformally covering the first circuit redistribution layer and contacting the first dielectric layer. Then, at least one second die is attached to the first cap layer. Forming a second dielectric layer conformally covering the second crystal grains and contacting with the first covering layer; forming a second redistribution layer on the second dielectric layer; forming at least one second plug through the second dielectric layer to electrically connect the second die and the second redistribution layer; and forming a second covering layer, conformally covering the second circuit redistribution layer and contacting with the second dielectric layer. Subsequently, a patterned conductive layer is formed on the second cover layer, and the first redistribution layer and the second redistribution layer are respectively connected to the patterned conductive layer through an interlayer connection structure.

In accordance with the above embodiments, the present disclosure provides a bumpless fan-out die stack structure and a method for fabricating the same. At least one Good Die (KGD) is bonded and fixed on a substrate; and covering the good bare crystal with a dielectric layer in a conformal manner; forming a circuit redistribution layer on the dielectric layer, electrically connecting the signal input/output end of the good bare die with the circuit redistribution layer through the plug, and fanning out the pin position of the signal input/output to a landing area (landing area) far away from the good bare die through a connecting wire of the circuit redistribution layer; the circuit redistribution layer is conformally covered by the dielectric covering layer to form an interconnection structure consisting of at least one good die and the circuit redistribution layer. Then, using the dielectric covering layer as a substrate, and repeating the above steps, a plurality of interconnection structures including at least one good die and a circuit redistribution layer are vertically stacked on the dielectric covering layer. And then, forming a patterned conductive layer on the structure of the grain lamination, and respectively connecting the falling area of each circuit redistribution layer to the patterned conductive layer through an interlayer connection structure penetrating through the grain lamination structure so as to be connected with an external circuit.

Because the die lamination structure is a dielectric layer and a covering layer which are laminated on the substrate in a conformal way, the good die is directly packaged, and the good die does not need to be packaged in advance by an additional substrate, so that the packaging step can be simplified, and the packaging thickness and the volume of the die lamination structure are reduced. In addition, as the good bare chips can be mutually interconnected through the interlayer connecting structure penetrating through the die laminated structure, no routing or welding pad space is required to be reserved, the die laminated structure can accommodate more good bare chips, and the packaging density is greatly increased.

Drawings

For a better understanding of the foregoing and other aspects of the present disclosure, reference will now be made in detail to the following description taken in conjunction with the accompanying drawings, in which:

fig. 1A to fig. 1J are schematic cross-sectional views illustrating a process for fabricating a pad-less out-fan-die stacked structure according to an embodiment of the present disclosure.

[ notation ] to show

10: the carrier substrate 100: external fan crystal grain laminated structure without welding pad

101: base material 101 a: surface of a substrate

102: a first die

102 a: back side 102b of first die: input/output terminal of first die

103: the release film 104: a first dielectric layer

105: first

wire redistribution layers

105a, 111a, 116 a: connecting part

105b-105f, 111b-111d, 116b-116 d: landing zone

106: first plug 107: through hole

108: first cover layer 109: second crystal grain

109 a: back side 109b of first die: input/output terminal of first die

110: second dielectric layer 111: second line redistribution layer

112: second plug 113: second cover layer

114: third crystal grain 115: a third dielectric layer

116: third-line redistribution layer 117: third plug

118: third cover layer 119: patterned conductive layer

119a-119 f: conductive portion 120: interlayer connection structure

120a-120 j: interlayer contacts 121a-121 f: opening of the container

122a-122 j: through-hole 123: dielectric film

Detailed Description

The present specification provides a pad-free out-fan die stack structure and a method for manufacturing the same, which can simplify the packaging steps, reduce the packaging thickness and volume of the die stack structure, and greatly increase the packaging density. In order to make the aforementioned embodiments, as well as other objects, features, and advantages of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below.

It should be noted, however, that the specific embodiments and methods are not to be considered as limiting the invention. The invention may be embodied with other features, elements, methods, and parameters. The preferred embodiments are provided only to illustrate the technical features of the present invention, and not to limit the scope of the claims of the present invention. Those skilled in the art will recognize that equivalent modifications and variations can be made in light of the following description without departing from the spirit of the invention. Like elements in different embodiments and drawings will be denoted by like reference numerals.

Referring to fig. 1A to 1J, fig. 1A to 1J are schematic cross-sectional views illustrating a process for manufacturing a pad-less fan-out die stacked structure 100 according to an embodiment of the present disclosure. The method of making the padless fan-die laminate structure 100 includes the steps of: first, a substrate 101 is provided. In some embodiments of the present disclosure, the substrate 101 may be a substrate or a film made of a dielectric material, such as silicon oxide, silicon nitride, a plasticized material, or other suitable materials. For example, in the present embodiment, the substrate 101 may be a plasticized film, such as a Polyimide (PI) film, formed on a carrier substrate 10 by spin coating (spin coating), deposition or direct coating.

In addition, in some embodiments of the present disclosure, a release film (release film)103 may be optionally formed on the carrier substrate 10 before the substrate 101 is formed. In the present embodiment, the release film 103 may be a plasticized film (as illustrated in fig. 1A) disposed between the carrier substrate 10 and the substrate 101. In other embodiments of the present disclosure, a dielectric film 123 may be optionally formed on the release film 103 before the substrate 101. In the present embodiment, the dielectric film 123 may be a silicon oxide layer located between the release film 103 and the substrate 101.

Next, at least one first die 102 is fixed on the substrate 101 and contacts the substrate 101. In some embodiments of the present description, the first die 102 is a good die that has been verified; and the thickness of the first crystal grains 102 from the front side (front side) to the back side (back side)102a is substantially less than 50 micrometers (μm). In the present embodiment, the thickness of the first crystal grains 102 is substantially between 25 microns and 30 microns. The fixing of the first die 102 may include attaching the back side 102a of the first die 102 to the surface 101a of the substrate 101, and exposing an Input/Output (I/O) terminal 102B at the front end of the first die 102 (as shown in fig. 1B).

Thereafter, a first dielectric layer 104 is formed to conformally cover the first crystal grains 102 and contact the surface 101a of the substrate 101 (as shown in fig. 1C). In some embodiments of the present disclosure, the material of the first dielectric layer 104 may be any dielectric material. For example, in the present embodiment, the first dielectric layer 104 may be a silicon dioxide layer formed by a deposition process; and the thickness of the first dielectric layer 104 is substantially less than 50 microns. The material, size and fabrication method of the first dielectric layer 104 are not limited thereto. In other embodiments, the first dielectric layer 104 may also be silicon nitride, a plasticized material, or the like. The manner of forming the first dielectric layer 104 may include a spin-on process on the first grains 102 and the surface 101a of the substrate 101; or directly attaching a dielectric material tape (tape) to the first die 102 and the surface 101a of the substrate 101.

Then, a first redistribution layer 105 is formed on the first dielectric layer 104; and a first plug 106 is formed through the first dielectric layer 104 to electrically connect the first die 102 and the first redistribution layer 105 (as shown in fig. 1D). In some embodiments of the present description, the formation of the first redistribution layer 105 may include the following steps: first, a metal layer, such as a copper or aluminum metal layer, is formed on the first dielectric layer 104 by a deposition process. The metal layer is then patterned by an etching process to expose a portion of the first dielectric layer 104. The first redistribution layer 105 includes at least one connection portion 105a, at least one landing zone 105b, and at least one connection line (not shown) for connecting the landing zone 105b to the connection portion 105 a.

The method for forming the first plug 106 includes the steps of: before the first redistribution layer 105 is formed, at least one via 107 is formed in the first dielectric layer 104, aligned with the signal input/output port 102b of the first die 102, and the signal input/output port 102b of the first die 102 is exposed. And filling the via hole 107 with a metal material while forming the first redistribution layer 105, thereby forming a first plug 106 electrically contacting the first redistribution layer 105. In the present embodiment, the connecting portion 105a and the i/o terminal 102b of the first die 102 are longitudinally overlapped with the first plug 106 (along the Z-axis direction) and electrically contact each other. Landing zone 105b is laterally (along the X-axis) away from first die 102. In other words, the i/o terminal 102b of the first die 102 can be electrically connected to the landing zone 105b through the first plug 106, the connecting portion 105a, and a connecting wire (not shown); and the signal input/output port 102b of the first die 102 can be fanned out to the landing area 105b far away from the first die 102 by the interconnection structure formed by the first redistribution layer 105 and the first plug 106. In one embodiment, the first plug 106 has a vertical Z-axis and a cross-sectional width of substantially 2 microns.

Subsequently, a first capping layer 108 is formed to conformally cover the first redistribution layer 105 and contact the exposed first dielectric layer 104 (as shown in fig. 1E). In some embodiments of the present disclosure, the material and the manufacturing method of the first capping layer 108 may be the same as or different from those of the first dielectric layer 104.

Next, at least one second die 109 is attached to the first cap layer 108. In some embodiments of the present description, the second die 109 is also a good die after verification testing; and the thickness of the second die 109 is substantially less than 50 microns. In the present embodiment, the thickness of the second crystal grain 109 is substantially between 25 microns and 30 microns. The second die 109 may be attached in the same manner as the first die 102, such that the backside 109a of the second die 109 is attached to the first cap layer 108 in a downward direction, and the i/o terminals 109b at the front end of the second die 109 are exposed (as shown in fig. 1F).

Forming a second dielectric layer 110 conformally covering the second die 109 and contacting the first cap layer 108; forming a second redistribution layer 111 on the second dielectric layer 110, and forming a second plug 112 penetrating through the second dielectric layer 110 to electrically connect the input/output terminal 109b of the second die 109 and the second redistribution layer 111; a second capping layer 113 is formed to conformally cover the second redistribution layer 111 and contact the second dielectric layer 110. The signal input/output port 109b of the second die 109 can be fanned out of the vertical X-Z plane to a landing area 111b (not shown in fig. 1G) away from the second die 109 by the interconnection structure formed by the connection portion 111a and the connection line (not shown) of the second redistribution layer 111 and the second plug 112. Since the materials and methods for fabricating the second dielectric layer 110, the second redistribution layer 111, the second plug 112 and the second capping layer 113 are the same as those for fabricating the first dielectric layer 104, the first redistribution layer 105, the first plug 106 and the first capping layer 108, respectively, they are not repeated herein.

Subsequently, the above steps are repeated to attach the third die 114 on the second capping layer 113, and a third dielectric layer 115, a third redistribution layer 116 (including at least a connection portion 116a and a landing portion 116b), a third plug 117 and a third capping layer 118 are formed on the second capping layer 113. In some embodiments of the present description, the landing zone 105b of the first redistribution layer 105 does not overlap with the first die 102, the second die 109, the third die 114, the second redistribution layer 111, and the third redistribution layer 116; and the landing area 111b of the second redistribution layer 111 does not overlap with the third die 114 and the third redistribution layer 116.

It should be noted that the arrangement of the landing areas of the first redistribution layer 105, the second redistribution layer 111 and the third redistribution layer 116 is not limited thereto. In some embodiments of the present description, first, second, and third redistribution layers 105, 111, 116 may also include other landing zones; and a portion of the landing zone may overlap the overlying wire redistribution layer. For example, in the present embodiment, the first redistribution layer 105 may further include

landing zones

105c, 105d, and 105 e; the second redistribution layer 111 may further include

landing zones

111c and 111 d; the third redistribution layer 116 may also include

landing zones

116c and 116 d. The landing zone 105e of the first redistribution layer 105 may overlap with the landing zone 116c of the third redistribution layer 116 (as shown in fig. 1H).

Subsequently, a patterned conductive layer 119 is formed on the third cover layer 118, and the first redistribution layer 105, the second redistribution layer 111 and the third redistribution layer 116 are respectively connected to the patterned conductive layer 119 through an interlayer connection structure 120. In some embodiments of the present description, the formation of the patterned conductive layer 119 and the interlayer connection structure 120 includes the steps of:

first, the third capping layer 118 is patterned by an etching process to form a plurality of openings 121a-121f in the third capping layer 118, extending from the upper surface of the third capping layer 118 into the third capping layer 118. Then, at least one through hole 122a-122j is formed in each of the openings 121a-121f by at least one etching process, and passes through the corresponding third cap layer 118, third redistribution layer 116, third dielectric layer 115, second cap layer 113, second redistribution layer 111, second dielectric layer 110 and first cap layer 108, thereby exposing the

landing areas

105b, 105c and 105d of the first redistribution layer 105, the

landing areas

111b, 111c and 111b of the second redistribution layer 111 and the

landing areas

116b, 116c and 116d of the third redistribution layer 116 to the outside.

In the present embodiment, the through hole 122a is formed in the opening 121a for exposing the landing area 105b of the first redistribution layer 105; a through hole 122b formed in the opening 121b for exposing the landing area 111b of the second redistribution layer 111; the through hole 122c is formed in the opening 121c for exposing the landing area 116b of the third redistribution layer 116; through

holes

122d and 122e are formed in the opening 121d for exposing the

landing areas

105c and 105f of the first redistribution layer 105, respectively; through

holes

122f and 122g formed in the opening 121e respectively expose the

landing areas

116c and 111c of the third redistribution layer 116 and the second redistribution layer 111; and through

holes

122h, 122I and 122j formed in the opening 121f respectively expose the landing zone 105d of the first redistribution layer 105, the landing zone 111d of the second redistribution layer 111 and the landing zone 116d of the third redistribution layer 116 (as shown in fig. 1I).

In some embodiments of the present disclosure, through holes having the same depth, such as through

holes

122a, 122d, and 122e, may be formed through the same etching process. For example, in one embodiment, the through

holes

122d and 122e having the same depth may be formed in the opening 121d by a single etching process; the through hole 122a is formed in the opening 121a by the same etching process. In another embodiment, the through

holes

122d and 122e may be formed in the same opening 121d by different etching processes. In addition, through holes with different depths, such as through

holes

122h, 122i, and 122j, can be formed in the same opening 121f by the same etching process. However, in another embodiment, the through

holes

122h, 122i and 122j may be formed in the same opening 121f by different etching processes.

The third cap layer 118 is then covered with a conductive material, such as copper, aluminum, tungsten, or a combination thereof, and fills the openings 121a-121f and the through holes 122a-122 g. Subsequently, a planarization process, such as Chemical-Mechanical Polishing (CMP), is performed using the third capping layer 118 as a stop layer to remove a portion of the conductive material, thereby forming the patterned conductive layer 119 and the interlayer connection structure 120; after a series of post-processes (not shown), the release film 103 is modified by uv irradiation or heat treatment to remove the carrier substrate 10, thereby completing the fabrication of the non-pad fan-out die stack 100 as shown in fig. 1J.

In the present embodiment, the patterned conductive layer 119 may include a plurality of conductive portions 119a-119f formed in the openings 121a-121f, respectively. The interlayer connection structure 120 may include a plurality of interlayer contacts 120a to 120j formed in the through holes 122a to 122j, respectively. Wherein, the interlayer contact 120a electrically connects the landing area 105b of the first redistribution layer 105 and the conductive portion 119a of the patterned conductive layer 119; the interlayer contact 120b electrically connects the landing area 111b of the second redistribution layer 111 and the conductive portion 119b of the patterned conductive layer 119; the interlayer contact 120c electrically connects the landing area 116b of the third redistribution layer 116 and the conductive portion 119c of the patterned conductive layer 119; the interlayer contact 120d electrically connects the landing area 105f of the first redistribution layer 105 and the conductive portion 119d of the patterned conductive layer 119; the interlayer contact 120e electrically connects the landing area 105c of the first redistribution layer 105 and the conductive portion 119d of the patterned conductive layer 119; the interlayer contact 120f electrically connects the landing area 116c of the third redistribution layer 116 and the conductive portion 119e of the patterned conductive layer 119; the interlayer contact 120g electrically connects the landing area 111c of the second redistribution layer 111 and the conductive portion 119e of the patterned conductive layer 119; the interlayer contact 120h electrically connects the landing area 116d of the third redistribution layer 116 and the conductive portion 119f of the patterned conductive layer 119; the interlayer contact 120i electrically connects the landing area 111d of the second redistribution layer 111 and the conductive portion 119f of the patterned conductive layer 119; and the interlayer contact 120j electrically connects the landing area 105d of the first redistribution layer 105 and the conductive portion 119f of the patterned conductive layer 119.

However, the connection design of the patterned conductive layer 119 and the interlayer connection structure 120 is not limited thereto. In other embodiments of the present disclosure, different landing areas of the first redistribution layer 105, the second redistribution layer 111, and the third redistribution layer 116 may be combined with different conductive portions 119a to 119f and interlayer contacts 120a to 120j to generate different interconnection structures, so as to provide different routing manners for the first die 102, the second die 109, and the third die 114.

Because the no-pad fan-die stack 100 is prepared, the first die 102, the second die 109, and the third die 114 can be vertically stacked to form a three-dimensional die stack without using an additional substrate to pre-package a good die. In addition, the patterned conductive layer 119 and the interlayer connection structure 120 are used to replace the conventional wire bonding or flip chip technology to form an interconnection structure among the first die 102, the second die 109 and the third die 114, so that the space reserved for wire bonding or bonding pads in the conventional technology can be saved to accommodate more dies, thereby greatly increasing the packaging density. Also, because the bumpless fan-die stack 100 does not use solder bumps to form the interconnect structure of the first die 102, the second die 109, and the third die 114, the thermal budget of the process can be reduced, and the problem of system failure due to solder bump overflow caused by thermal stress can be prevented.

In accordance with the above embodiments, the present disclosure provides a bumpless fan-out die stack structure and a method for fabricating the same. At least one good bare die is bonded and fixed on a substrate; and covering the good bare crystal with a dielectric layer in a conformal manner; forming a circuit redistribution layer on the dielectric layer, electrically connecting the signal input/output end of the good bare chip with the circuit redistribution layer through the plug, and fanning out the pin position of the signal input/output to a landing area far away from the good bare chip through a connecting wire of the circuit redistribution layer; the circuit redistribution layer is conformally covered by the dielectric covering layer to form an interconnection structure consisting of at least one good die and the circuit redistribution layer. Then, using the dielectric covering layer as a substrate, and repeating the above steps, a plurality of interconnection structures including at least one good die and a circuit redistribution layer are vertically stacked on the dielectric covering layer. And then, forming a patterned conductive layer on the structure of the grain lamination, and respectively connecting the falling area of each circuit redistribution layer to the patterned conductive layer through an interlayer connection structure penetrating through the grain lamination structure so as to be connected with an external circuit.

Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A padless fan-die laminate structure, comprising:

a substrate;

a first crystal grain on the substrate;

a first dielectric layer conformally covering the first crystal grain and contacting the substrate;

a first redistribution layer on the first dielectric layer;

a first plug passing through the first dielectric layer to electrically connect the first die and the first redistribution layer;

a first covering layer conformally covering the first redistribution layer and contacting the first dielectric layer;

the second crystal grain is attached to the first covering layer, and the front surface of the first crystal grain faces to the bottom surface of the second crystal grain;

a second dielectric layer conformally covering the second crystal grain and contacting with the first covering layer;

a second redistribution layer on the second dielectric layer;

a second plug passing through the second dielectric layer to electrically connect the second die and the second redistribution layer;

a second covering layer conformally covering the second redistribution layer and contacting the second dielectric layer;

a patterned conductive layer on the second cover layer and including multiple conductive parts; and

an interlayer connection structure including a plurality of interlayer contacts, wherein the interlayer connection structure is connected with the patterned conductive layer through different landing areas of the first redistribution layer and the second redistribution layer, and different combinations of conductive parts and the interlayer contacts are matched to generate a plurality of different interconnection structures so as to provide different wiring modes for the first crystal grain and the second crystal grain;

wherein a first landing zone of the first redistribution layer is not overlapped with a second landing zone of the second grain and the second redistribution layer, and the conductive part of the patterned conductive layer is electrically contacted with the first redistribution layer and the second redistribution layer through the interlayer connection structure.

2. The padless fan-die laminate structure of claim 1, wherein the interlayer connection structure comprises:

a first interlayer contact passing through the second cover layer, the second dielectric layer and the first cover layer to electrically connect a first conductive part of the patterned conductive layer with the first landing area of the first circuit redistribution layer; and

a second interlayer contact passing through the second cover layer to electrically connect a second conductive part of the patterned conductive layer with the second landing area of the second redistribution layer.

3. The padless fan-die laminate structure of claim 2, wherein the interlayer connection structure further comprises:

a third interlayer contact passing through the second cover layer, the second dielectric layer and the first cover layer to electrically connect a third conductive part of the patterned conductive layer with a third landing area of the first circuit redistribution layer; and

a fourth interlayer contact, passing through the second cover layer, the second dielectric layer and the first cover layer, electrically connecting the third conductive part with a fourth landing area of the first redistribution layer; and the first landing zone, the third landing zone and the fourth landing zone are isolated from each other.

4. The padless fan-die laminate structure of claim 2, wherein the interlayer connection structure further comprises:

a fourth interlayer contact, passing through the second cover layer, electrically connecting the third conductive part with a fourth landing zone of the second redistribution layer.

5. A method for manufacturing a pad-free outer fan crystal grain laminated structure comprises the following steps:

providing a base material;

fixing at least one first crystal grain on the substrate;

forming a first dielectric layer conformally covering the first crystal grain and contacting with the substrate;

forming a first redistribution layer on the first dielectric layer;

forming at least one first plug through the first dielectric layer to electrically connect the first die and the first redistribution layer;

forming a first covering layer conformally covering the first redistribution layer and contacting the first dielectric layer;

attaching at least one second crystal grain to the first covering layer, wherein the front surface of the first crystal grain faces to the bottom surface of the second crystal grain;

forming a second dielectric layer conformally covering the second crystal grain and contacting with the first covering layer;

forming a second redistribution layer on the second dielectric layer;

forming at least one second plug through the second dielectric layer to electrically connect the second die and the second redistribution layer;

forming a second covering layer conformally covering the second redistribution layer and contacting the second dielectric layer;

forming a patterned conductive layer on the second cover layer, wherein the patterned conductive layer comprises a plurality of conductive parts; and

forming an interlayer connection structure, wherein the interlayer connection structure comprises a plurality of interlayer contacts, and the interlayer connection structure is connected with the patterned conductive layer through different landing areas of the first circuit redistribution layer and the second circuit redistribution layer, and different combinations of conductive parts and the interlayer contacts are matched to generate different interconnection structures so as to provide different wiring modes for the first crystal grain and the second crystal grain;

6. The method of claim 5, wherein the step of providing the substrate comprises:

forming a release film on a carrier substrate; and

forming a dielectric film on the release film.

7. The method of claim 5, wherein the step of forming the patterned conductive layer and the interlayer connection structure comprises:

patterning the second covering layer to form at least a first opening and a second opening in the second covering layer;

forming a first through hole in the first opening, penetrating through the second cover layer, the second dielectric layer and the first cover layer, and exposing a first landing area of the first redistribution layer;

forming a second through hole in the second opening, penetrating the second cover layer, and exposing a second landing area of the second redistribution layer; and

filling the first opening, the second opening, the first through hole and the second through hole with a conductive material.

8. The method of claim 7, wherein the second patterned cover layer further comprises a third opening, and the step of forming the patterned conductive layer and the interlayer connection structure further comprises:

forming a third through hole and a fourth through hole in the third opening, wherein the third through hole passes through the second cover layer, the second dielectric layer and the first cover layer to expose a third landing area of the first redistribution layer, and the fourth through hole passes through the second cover layer, the second dielectric layer and the first cover layer to expose a fourth landing area of the first redistribution layer; and

and filling the third opening, the third through hole and the fourth through hole with the conductive material.

9. The method of claim 7, wherein the second patterned cover layer further comprises a third opening, and the step of forming the patterned conductive layer and the interlayer connection structure further comprises:

forming a third through hole and a fourth through hole in the third opening, the third through hole passing through the second cover layer, the second dielectric layer and the first cover layer to expose a third landing area of the first redistribution layer, the fourth through hole passing through the second cover layer to expose a fourth landing area of the second redistribution layer; and

10. The method of claim 7, wherein the second patterned cover layer further comprises a third opening, and the step of forming the patterned conductive layer and the interlayer connection structure further comprises:

forming a third through hole in the third opening, penetrating through the second cover layer, the second dielectric layer and the first cover layer, and exposing a third landing area of the first redistribution layer; and

forming a fourth through hole in the third opening, penetrating the second cover layer, and exposing a fourth landing area of the second redistribution layer; and