CN110571273A - GaN HEMT device and method for synchronously preparing source, drain and grid - Google Patents
GaN HEMT device and method for synchronously preparing source, drain and grid Download PDFInfo
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- CN110571273A CN110571273A CN201910657362.0A CN201910657362A CN110571273A CN 110571273 A CN110571273 A CN 110571273A CN 201910657362 A CN201910657362 A CN 201910657362A CN 110571273 A CN110571273 A CN 110571273A
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 68
- 229910052751 metal Inorganic materials 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 64
- 239000011888 foil Substances 0.000 claims description 40
- 229910002704 AlGaN Inorganic materials 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 29
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- 238000001704 evaporation Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 238000009616 inductively coupled plasma Methods 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 10
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- 229910052719 titanium Inorganic materials 0.000 claims description 10
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 9
- 238000012546 transfer Methods 0.000 claims description 8
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- 239000000523 sample Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
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- 238000005566 electron beam evaporation Methods 0.000 claims description 2
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- 238000004549 pulsed laser deposition Methods 0.000 claims description 2
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Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
the invention discloses a GaN HEMT device and a method for synchronously preparing a source electrode, a drain electrode and a grid electrode, wherein the device comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially distributed from bottom to top, two ends of the upper surface of the barrier layer are connected with the source electrode and the drain electrode, an insulating layer is distributed on the upper surface of the barrier layer between the source electrode and the drain electrode, the upper surface of the insulating layer is connected with the grid electrode, the source electrode and the drain electrode are respectively in ohmic contact with the channel layer, and the height of the source electrode and the height of the drain electrode are equal and. The preparation method provided by the invention overcomes the defect that the existing preparation process needs to prepare the source, the drain and the grid in two steps, does not have the light diffraction effect of the traditional photoetching technology, and can quickly manufacture the micro-nano pattern with high dimensional precision. In addition, the method does not need alignment and secondary photoetching steps, can realize very accurate size control, has the line width of the device as low as 50nm, has simple operation steps and is suitable for industrial production.
Description
Technical Field
the invention belongs to the technical field of semiconductors, and particularly relates to a GaN HEMT device and a method for synchronously preparing a source electrode, a drain electrode and a grid electrode.
background
In recent years, wide bandgap semiconductors represented by group III nitrides such as GaN have been receiving much attention and have been vigorously developed. GaN High Electron Mobility Transistors (HEMTs) based on AlGaN/GaN heterojunctions exhibit incomparable great advantages in the aspects of high temperature resistance, radiation resistance, high voltage, high power, high frequency and the like, have already obtained practical application in the fields of power electronics and microwave radio frequency, and have a wide future development space.
in the GaN HEMT device, a source electrode and a drain electrode must form low-resistance ohmic contact with a channel layer to reduce on-resistance, and a thin insulating layer composed of silicon dioxide, aluminum oxide and the like is usually added between the grid electrode and a barrier layer to isolate so as to reduce leakage current.
Disclosure of Invention
in order to overcome the defects and shortcomings of the prior art, the invention aims to provide a GaN HEMT device and a method for synchronously preparing a source electrode, a drain electrode and a grid electrode.
The object of the invention is achieved by at least one of the following solutions.
the invention provides a GaN HEMT device synchronously prepared from a source electrode, a drain electrode and a grid electrode, which comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially distributed from bottom to top, wherein two ends of the upper surface of the barrier layer are connected with the source electrode and the drain electrode, an insulating layer is distributed on the upper surface of the barrier layer between the source electrode and the drain electrode, the upper surface of the insulating layer is connected with the grid electrode, the source electrode and the drain electrode are respectively in ohmic contact with the channel layer, and the height of the source electrode and the height of the drain electrode are equal.
preferably, the source electrode, the drain electrode and the grid electrode are all cuboids, the source electrode is the same as the drain electrode in size, the height is 400 ~ 1600nm, the length is 1 ~ 10 micrometers, the width is 1 ~ 10 micrometers, the grid electrode is 200 ~ 1400 nm in height, the width is the same as the source electrode, and the length is 50 ~ 2000 nm.
preferably, the height of the source electrode is 150 ~ 300 nm higher than that of the gate electrode, the distance between the gate electrode and the source electrode is 100 ~ 4000 nm, and the distance between the gate electrode and the drain electrode is 1 ~ 4 times of the distance between the gate electrode and the source electrode.
preferably, the source electrode, the drain electrode and the grid electrode are metal layers, the metal layers comprise a titanium metal layer, an aluminum metal layer, a nickel metal layer and a gold metal layer which are sequentially arranged from bottom to top, the thickness of the titanium metal layer is 10 ~ 30 nm, the thickness of the aluminum metal layer is 50 ~ 200nm, the thickness of the nickel metal layer is 50 ~ 100nm, and the thickness of the gold metal layer is 50 ~ 100 nm.
preferably, the insulating layer is made of one of silicon dioxide, silicon nitride and aluminum oxide, the thickness of the insulating layer is 5 ~ 60 nm, the substrate is one of silicon, silicon carbide and sapphire, and the thickness of the substrate is 0.3 ~ 1 mm;
the buffer layer is an AlGaN graded layer or an AlN/GaN superlattice layer, and the thickness of the buffer layer is 1.5 ~ 3 mu m;
the channel layer is a GaN channel layer, the thickness of the channel layer is 1 ~ 3 mu m, the barrier layer is an AlGaN barrier layer, and the thickness of the barrier layer is 20 ~ 25 nm.
preferably, the device further comprises a foil connected with the grid electrode, the foil is used for leading the grid electrode out of the device so as to be convenient for a probe station to test, the foil is located on the upper surface of the insulating layer, the shape of the foil is cuboid, the height of the foil is the same as that of the grid electrode, the length of the foil is 1 ~ 10 microns, and the width of the foil is 1 ~ 10 microns.
the invention also provides a method for synchronously preparing the source, the drain and the grid of the GaN HEMT device, which comprises the following steps:
(1) taking a wafer, wherein the wafer comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, and depositing an insulating layer on the barrier layer;
(2) Coating a layer of negative photoresist on the insulating layer;
(3) simultaneously imprinting patterns of a source electrode, a drain electrode and a grid electrode on the upper surface of the negative photoresist by a nano imprinting technology, and curing the negative photoresist by ultraviolet irradiation of 254 ~ 365 nm;
(4) Removing the negative photoresist and the insulating layer below the bottom of the source electrode and drain electrode pattern by an etching process to expose the barrier layer, thereby realizing the transfer of the source electrode and drain electrode pattern from the negative photoresist to the wafer;
(5) removing the negative photoresist under the bottom of the pattern of the grid electrode by an etching process to expose the insulating layer and realize the transfer of the grid electrode pattern from the negative photoresist to the wafer;
(6) evaporating a metal layer on the negative photoresist, the barrier layer exposed in the step (4) and the upper surface of the insulating layer exposed in the step (5), removing the negative photoresist and the metal layer on the upper surface of the negative photoresist in a photoresist removing solution after evaporation, and forming a source electrode and a drain electrode on the metal layer on the upper surface of the barrier layer exposed in the step (4) correspondingly; forming a grid electrode on the exposed metal layer on the upper surface of the insulating layer in the step (5);
(7) The source and drain electrodes are brought into ohmic contact with the channel layer by thermal annealing.
preferably, the deposition method of the insulating layer in the step (1) is one of metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition, pulsed laser deposition, atomic layer deposition and molecular beam epitaxy;
the thickness of the negative photoresist in the step (2) is 400 ~ 1600 nm;
the ultraviolet curing time in the step (3) is 30 ~ 60 seconds, and is related to the thickness of the negative photoresist.
preferably, the etching process in steps (4) and (5) adopts Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP); use of O in etching negative photoresist2the method comprises the following steps of selecting/Ar as etching gas, and selecting carbon tetrafluoride/trifluoromethane/Ar, carbon tetrafluoride/trifluoromethane/Ar and chlorine/boron trichloride/Ar as etching gas when an insulating layer is etched;
The evaporation method of the metal electrode in the step (6) is electron beam evaporation or magnetron sputtering;
the thermal annealing temperature in the step (7) is 700 ~ 900 ℃, and the time is 30 ~ 60 seconds.
preferably, in the step (3), a foil pattern is printed while the source electrode, the drain electrode and the gate electrode pattern are printed on the upper surface of the negative photoresist by a nano-imprinting technique, the foil pattern is connected with the gate electrode pattern, the bottom surface of the foil pattern is the upper surface of the insulating layer, and the depth of the foil pattern is the same as that of the gate electrode pattern.
Compared with the prior art, the invention has the following beneficial effects and advantages:
(1) The source electrode, the grid electrode and the drain electrode are synchronously prepared by utilizing the nano-imprinting technology, and the defect that the source electrode, the drain electrode and the grid electrode need to be prepared in two steps in the conventional preparation process of the GaN HEMT device is overcome;
(2) the nano-imprinting technology is a novel micro-nano processing technology based on a mechanical transfer means, does not have the light diffraction effect of the traditional photoetching technology, and can quickly manufacture micrometer and nanometer level patterns with high dimensional precision;
(3) The method for preparing the GaN HEMT device electrode does not need an alignment step and a secondary photoetching step, so that very accurate size control can be realized, the line width of the device can be as low as 50nm, the operation steps are simple, and the method is suitable for industrial production.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings are provided for brief description. It is to be noted, however, that the following drawings are only for the purpose of illustrating the present invention and are not to be construed as limiting the present invention. In the drawings:
Fig. 1 is a schematic structural view of a nanoimprint mold used in an embodiment, in which (a) is a front view and (b) is a top view;
fig. 2 is a schematic structural diagram of a GaN HEMT device fabricated with source, drain and gate electrodes simultaneously provided by the embodiment;
In the figure: 1-a source electrode; 2-a drain electrode; 3-a grid; 4-a foil; 5-an insulating layer; a 6-AlGaN barrier layer; 7-a GaN channel layer; 8-a buffer layer; 9-substrate.
Detailed Description
The present invention is further illustrated by the following examples, which are intended to be purely exemplary of the invention and are not intended to limit the scope of the invention. Further, it will be understood that various insubstantial changes and modifications can be made by those skilled in the art without inventive faculty after reading the present disclosure, and equivalents thereof can be made within the scope of the invention as defined in the claims appended hereto.
example 1
the embodiment provides a GaN HEMT device with synchronously prepared source, drain and gate, as shown in fig. 2, the device comprises a substrate 9, a buffer layer 8, a GaN channel layer 7 and an AlGaN barrier layer 6 which are sequentially distributed from bottom to top, wherein two ends of the upper surface of the AlGaN barrier layer 6 are connected with a source electrode 1 and a drain electrode 2, an insulating layer 5 is distributed on the upper surface of the AlGaN barrier layer 6 between the source electrode 1 and the drain electrode 2, the upper surface of the insulating layer 5 is connected with a gate electrode 3, the source electrode 1 and the drain electrode 2 are in ohmic contact with the GaN channel layer 7 respectively, and the source electrode 1 and the drain electrode 2 are equal in height and higher than the gate electrode 3.
The source electrode 1, the drain electrode 2 and the grid electrode 3 are all cuboids; the size of the source electrode 1 is the same as that of the drain electrode 2, the height is 750 nm, the length is 5 mu m, and the width is 5 mu m; the gate 3 has a height of 350 nm, a width equal to that of the source 1, and a length of 100 nm.
the distance between the grid 3 and the source 1 is 200 nm; the distance between the gate 3 and the drain 2 is 500 nm.
the source electrode 1, the drain electrode 2 and the grid electrode 3 are metal layers, the metal layers comprise a titanium metal layer, an aluminum metal layer, a nickel metal layer and a gold metal layer which are sequentially arranged from bottom to top, the thickness of the titanium metal layer is 10 nm, the thickness of the aluminum metal layer is 60 nm, the thickness of the nickel metal layer is 65 nm, and the thickness of the gold metal layer is 80 nm.
The insulating layer 5 is a silicon dioxide layer with a thickness of 10 nm.
the device also comprises a foil 4 connected with the grid electrode, wherein the foil 4 is used for leading out the grid electrode 3 to the outside of the device so as to facilitate the test of a probe station; the foil 4 is positioned on the upper surface of the insulating layer 5, and is in the shape of a cuboid, the height of the cuboid is the same as that of the grid, the length of the cuboid is 5 microns, and the width of the cuboid is 5 microns.
the substrate 9 is silicon, and the thickness of the substrate 9 is 700 μm; the buffer layer 8 is an AlN/GaN superlattice layer, and the thickness of the buffer layer 8 is 1.8 mu m;
The thickness of the GaN channel layer 7 is 2.2 μm;
The AlGaN barrier layer 6 has a thickness of 20 nm.
The embodiment also provides a method for synchronously preparing the source electrode 1, the drain electrode 2 and the grid electrode 3 of the GaN HEMT device, which comprises the following steps:
(1) Taking a 4-inch wafer, wherein the wafer comprises a substrate 9, a buffer layer 8, a GaN channel layer 7 and an AlGaN barrier layer 6 which are sequentially arranged from bottom to top, and depositing an insulating layer 5 on the AlGaN barrier layer 6 by utilizing an atomic layer deposition technology;
(2) Coating a layer of negative photoresist with the thickness of 800nm on the insulating layer 5;
(3) Imprinting patterns of a source electrode, a drain electrode, a grid electrode and a foil piece on the upper surface of the negative photoresist by using a nano imprinting mould shown in (a) and (b) of figure 1 through a nano imprinting technology, and curing the negative photoresist by irradiating 365 nm ultraviolet light for 33 seconds so as to shape the patterns;
(4) by ICP etching process with O2the/Ar is etching gas, the negative photoresist under the bottom of the source electrode pattern and the drain electrode pattern is removed, the negative photoresist with the thickness of about 400 nm still remains due to the shallow depth of the grid electrode pattern, and CF is used for the negative photoresist4/CHF3the/Ar is etching gas to remove the silicon dioxide insulating layer under the bottom of the source electrode and the drain electrode pattern and expose AThe lGaN barrier layer 6 is used for realizing the transfer of the source electrode pattern and the drain electrode pattern from the negative photoresist to the wafer, and the insulating layer 5 below the bottom of the grid electrode pattern is not influenced due to the protection of the negative photoresist;
(5) By ICP etching process with O2the/Ar is etching gas to remove the negative photoresist below the bottom of the pattern of the grid to expose the insulating layer, so that the grid pattern is transferred from the photoresist to the wafer;
(6) Evaporating a metal layer on the negative photoresist, the AlGaN barrier layer 6 exposed in the step (4) and the upper surface of the insulating layer 5 exposed in the step (5) by using an electron beam evaporator, removing the negative photoresist and the metal layer on the upper surface of the negative photoresist in a photoresist removing solution after evaporation, and forming a source electrode 1 and a drain electrode 2 by using the metal layer on the upper surface of the AlGaN barrier layer 6 exposed in the step (4); forming a grid electrode 3 on the metal layer exposed out of the step (5) on the upper surface of the insulating layer 5;
(7) and annealing at 750 ℃ for 35 seconds to enable the source electrode 1 and the drain electrode 2 to form ohmic contact with the GaN channel layer 7, so that the source electrode 1, the drain electrode 2 and the grid electrode 3 are synchronously prepared.
example 2
the embodiment provides a GaN HEMT device with synchronously prepared source, drain and gate, as shown in fig. 2, the device comprises a substrate 9, a buffer layer 8, a GaN channel layer 7 and an AlGaN barrier layer 6 which are sequentially distributed from bottom to top, wherein two ends of the upper surface of the AlGaN barrier layer 6 are connected with a source electrode 1 and a drain electrode 2, an insulating layer 5 is distributed on the upper surface of the AlGaN barrier layer 6 between the source electrode 1 and the drain electrode 2, the upper surface of the insulating layer 5 is connected with a gate electrode 3, the source electrode 1 and the drain electrode 2 are in ohmic contact with the GaN channel layer 7 respectively, and the source electrode 1 and the drain electrode 2 are equal in height and higher than the gate electrode 3.
The source electrode 1, the drain electrode 2 and the grid electrode 3 are all cuboids; the size of the source electrode 1 is the same as that of the drain electrode 2, the height is 1200nm, the length is 8 mu m, and the width is 8 mu m; the height of the grid 3 is 600nm, the width is the same as the source electrode, and the length is 200 nm.
the distance between the grid 3 and the source 1 is 200 nm; the distance between the gate 3 and the drain 2 is 400 nm.
The source electrode 1, the drain electrode 2 and the grid electrode 3 are metal layers, the metal layers comprise a titanium metal layer, an aluminum metal layer, a nickel metal layer and a gold metal layer which are sequentially arranged from bottom to top, the thickness of the titanium metal layer is 20 nm, the thickness of the aluminum metal layer is 100nm, the thickness of the nickel metal layer is 75 nm, and the thickness of the gold metal layer is 90 nm.
The insulating layer 5 is an alumina layer with a thickness of 15 nm.
The device also comprises a foil 4 connected with the grid 3, wherein the foil 4 is used for leading the grid 1 out of the device so as to facilitate the test of a probe station; the foil 4 is positioned on the upper surface of the insulating layer 5, and the foil 4 is in the shape of a rectangular parallelepiped with a height equal to that of the gate 3, a length of 8 μm, and a width of 8 μm.
the substrate 9 is sapphire, and the thickness of the substrate 9 is 420 μm;
the buffer layer 8 is an AlGaN gradient layer, and the thickness of the buffer layer 8 is 20 micrometers;
The thickness of the GaN channel layer 7 is 1.8 μm;
The AlGaN barrier layer 6 has a thickness of 25 nm.
The embodiment also provides a method for synchronously preparing the source electrode, the drain electrode and the grid electrode of the GaN HEMT device, which comprises the following steps:
(1) taking a 6-inch wafer, wherein the wafer comprises a substrate 9, a buffer layer 8, a GaN channel layer 7 and an AlGaN barrier layer 6 which are sequentially arranged from bottom to top, and depositing an aluminum oxide insulating layer on the AlGaN barrier layer 6 by utilizing an atomic layer deposition technology;
(2) Coating a layer of negative photoresist with the thickness of 1200nm on the insulating layer 5;
(3) Imprinting patterns of a source electrode, a drain electrode, a grid electrode and a foil piece on the upper surface of the negative photoresist by using a nano imprinting mould shown in (a) and (b) of figure 1 through a nano imprinting technology, and curing the negative photoresist by irradiating the negative photoresist for 45 seconds through 254 nm ultraviolet light so as to shape the patterns;
(4) by ICP etching process with O2the/Ar is etching gas, the negative photoresist under the bottom of the source electrode and the drain electrode is removed, and the negative photoresist with the thickness of about 600nm still remains due to the shallow depth of the grid electrode pattern, and Cl is used for removing the negative photoresist2/BCl3patterning the bottom of the source and drain electrodes for etching gasremoving the insulating layer 5 below the gate pattern, exposing the AlGaN barrier layer, realizing the transfer of the source and drain patterns from the negative photoresist to the wafer, and not influencing the insulating layer 5 below the bottom of the gate pattern due to the protection of the negative photoresist;
(5) By ICP etching process with O2the/Ar is etching gas to remove the negative photoresist below the bottom of the pattern of the grid to expose the insulating layer 5, so that the grid pattern is transferred from the photoresist to the wafer;
(6) evaporating a metal layer on the negative photoresist, the AlGaN barrier layer 6 exposed in the step (4) and the upper surface of the insulating layer 5 exposed in the step (5) by using a magnetron sputtering film plating machine, removing the negative photoresist and the metal layer on the upper surface of the negative photoresist in a photoresist removing solution after evaporation is finished, and forming a source electrode 1 and a drain electrode 2 on the metal layer on the upper surface of the AlGaN barrier layer 6 exposed in the step (4); forming a grid electrode 3 on the metal layer exposed out of the step (5) on the upper surface of the insulating layer 5;
(7) and annealing at the high temperature of 800 ℃ for 30 seconds to enable the source electrode 1 and the drain electrode 2 to form ohmic contact with the GaN channel layer 7, so that the source electrode, the drain electrode and the grid electrode are synchronously prepared.
Example 3
the embodiment provides a GaN HEMT device with synchronously prepared source, drain and gate, as shown in fig. 2, the device comprises a substrate 9, a buffer layer 8, a GaN channel layer 7 and an AlGaN barrier layer 6 which are sequentially distributed from bottom to top, wherein two ends of the upper surface of the AlGaN barrier layer 6 are connected with a source electrode 1 and a drain electrode 2, an insulating layer 5 is distributed on the upper surface of the AlGaN barrier layer 6 between the source electrode 1 and the drain electrode 2, the upper surface of the insulating layer 5 is connected with a gate electrode 3, the source electrode 1 and the drain electrode 2 are in ohmic contact with the GaN channel layer 7 respectively, and the source electrode 1 and the drain electrode 2 are equal in height and higher than the gate electrode 3.
The source electrode 1, the drain electrode 2 and the grid electrode 3 are all cuboids; the size of the source electrode 1 is the same as that of the drain electrode 2, the height is 1500 nm, the length is 10 mu m, and the width is 10 mu m; the gate 3 has a height of 1000 nm, a width equal to that of the source 1, and a length of 800 nm.
the distance between the grid 3 and the source 1 is 1 μm; the distance between the gate 3 and the drain 2 is 1.8 μm.
the source electrode 1, the drain electrode 2 and the grid electrode 3 are metal layers, the metal layers comprise a titanium metal layer, an aluminum metal layer, a nickel metal layer and a gold metal layer which are sequentially arranged from bottom to top, the thickness of the titanium metal layer is 25 nm, the thickness of the aluminum metal layer is 150nm, the thickness of the nickel metal layer is 80 nm, and the thickness of the gold metal layer is 100 nm.
The insulating layer is a silicon nitride layer with a thickness of 20 nm.
The device also comprises a foil 4 connected with the grid 3, wherein the foil 4 is used for leading the grid 3 out of the device so as to facilitate the test of a probe station; the foil 4 is positioned on the upper surface of the insulating layer 5, the shape of the foil 4 is a cuboid, the height of the foil is the same as that of the grid 3, the length of the foil is 10 micrometers, and the width of the foil is 10 micrometers;
The substrate 9 is silicon carbide, and the thickness of the substrate 9 is 500 micrometers;
the buffer layer 8 is an AlN/GaN superlattice layer, and the thickness of the buffer layer 8 is 3 micrometers;
The thickness of the GaN channel layer 7 is 2.8 μm;
The AlGaN barrier layer 6 has a thickness of 25 nm.
The embodiment also provides a method for synchronously preparing the source electrode, the drain electrode and the grid electrode of the GaN HEMT device, which comprises the following steps:
(1) Taking a 6-inch wafer, wherein the wafer comprises a substrate 9, a buffer layer 8, a GaN channel layer 7 and an AlGaN barrier layer 6 which are sequentially arranged from bottom to top, and depositing an insulating layer 5 on the AlGaN barrier layer 6 by utilizing an atomic layer deposition technology;
(2) Coating a layer of negative photoresist with the thickness of 1600nm on the insulating layer 5;
(3) Imprinting patterns of a source electrode, a drain electrode, a grid electrode and a foil piece on the upper surface of the negative photoresist by using a nano imprinting mould shown in (a) and (b) of figure 1 through a nano imprinting technology, and curing the negative photoresist by irradiating 365 nm ultraviolet light for 50 seconds so as to shape the patterns;
(4) by ICP etching process with O2the/Ar is etching gas, the negative photoresist under the bottom of the source electrode and the drain electrode pattern is removed, the negative photoresist with the thickness of about 700 nm still remains due to the shallow depth of the grid electrode pattern, and CF is used for removing the negative photoresist4/CHF3/ArThe insulating layer 5 below the bottom of the source electrode pattern and the drain electrode pattern is removed by etching gas, the AlGaN barrier layer 6 is exposed, the transfer of the source electrode pattern and the drain electrode pattern from the negative photoresist to the wafer is realized, and the insulating layer 5 below the bottom of the grid electrode pattern is not influenced due to the protection of the negative photoresist;
(5) By ICP etching process with O2the/Ar is etching gas to remove the negative photoresist below the bottom of the pattern of the grid to expose the insulating layer 5, so that the grid pattern is transferred from the photoresist to the wafer;
(6) Evaporating a metal layer on the negative photoresist, the AlGaN barrier layer 6 exposed in the step (4) and the upper surface of the insulating layer 5 exposed in the step (5) by using a magnetron sputtering film plating machine, removing the negative photoresist and the metal layer on the upper surface of the negative photoresist in a photoresist removing solution after evaporation is finished, and forming a source electrode 1 and a drain electrode 2 on the metal layer on the upper surface of the AlGaN barrier layer 6 exposed in the step (4); forming a grid electrode 3 on the metal layer exposed out of the step (5) on the upper surface of the insulating layer 5;
(7) And (3) annealing at the high temperature of 700 ℃ for 60 seconds to enable the source electrode 3 and the drain electrode 2 to form ohmic contact with the GaN channel layer 7, so that the synchronous preparation of the source electrode, the drain electrode and the grid electrode is completed.
the above examples are preferred embodiments of the present invention. The present invention should not be limited to the embodiments described, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents and are intended to be included in the scope of the present invention.
Claims (10)
1. The GaN HEMT device with the source electrode, the drain electrode and the grid electrode synchronously prepared is characterized by comprising a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially distributed from bottom to top, wherein two ends of the upper surface of the barrier layer are connected with the source electrode and the drain electrode, an insulating layer is distributed on the upper surface of the barrier layer between the source electrode and the drain electrode, the upper surface of the insulating layer is connected with the grid electrode, the source electrode and the drain electrode are respectively in ohmic contact with the channel layer, and the height of the source electrode and the height of the drain electrode are equal and.
2. the GaN HEMT device synchronously prepared by the source electrode, the drain electrode and the grid electrode according to claim 1 is characterized in that the source electrode, the drain electrode and the grid electrode are all cuboids, the source electrode is the same as the drain electrode in size, the height is 400 ~ 1600nm, the length is 1 ~ 10 micrometers, the width is 1 ~ 10 micrometers, the height of the grid electrode is 200 ~ 1400 nm, the width is the same as the source electrode, and the length is 50 ~ 2000 nm.
3. the GaN HEMT device prepared synchronously with the source, the drain and the grid according to claim 1, wherein the height of the source is 150 ~ 300 nm higher than that of the grid, the distance between the grid and the source is 100 ~ 4000 nm, and the distance between the grid and the drain is 1 ~ 4 times that between the grid and the source.
4. the GaN HEMT device with the source electrode, the drain electrode and the grid electrode synchronously prepared according to claim 1, wherein the source electrode, the drain electrode and the grid electrode are metal layers, the metal layers comprise a titanium metal layer, an aluminum metal layer, a nickel metal layer and a gold metal layer which are sequentially arranged from bottom to top, the thickness of the titanium metal layer is 10 ~ 30 nm, the thickness of the aluminum metal layer is 50 ~ 200nm, the thickness of the nickel metal layer is 50 ~ 100nm, and the thickness of the gold metal layer is 50 ~ 100 nm.
5. the GaN HEMT device synchronously prepared by the source, the drain and the grid according to claim 1 is characterized in that the insulating layer is made of one of silicon dioxide, silicon nitride and aluminum oxide, the thickness of the insulating layer is 5 ~ 60 nm, the substrate is one of silicon, silicon carbide and sapphire, and the thickness of the substrate is 0.3 ~ 1 mm;
the buffer layer is an AlGaN graded layer or an AlN/GaN superlattice layer, and the thickness of the buffer layer is 1.5 ~ 3 mu m;
the channel layer is a GaN channel layer, the thickness of the channel layer is 1 ~ 3 mu m, the barrier layer is an AlGaN barrier layer, and the thickness of the barrier layer is 20 ~ 25 nm.
6. the GaN HEMT device synchronously prepared by the source, the drain and the grid according to claim 1 is characterized by further comprising a foil connected with the grid, wherein the foil is used for leading the grid out of the device so as to be convenient for a probe station to test, the foil is positioned on the upper surface of the insulating layer, the foil is cuboid, the height of the foil is the same as that of the grid, the length of the foil is 1 ~ 10 microns, and the width of the foil is 1 ~ 10 microns.
7. A method for synchronously preparing a source electrode, a drain electrode and a grid electrode of the GaN HEMT device as claimed in any one of claims 1 to 6, which is characterized by comprising the following steps:
(1) Taking a wafer, wherein the wafer comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, and depositing an insulating layer on the barrier layer;
(2) Coating a layer of negative photoresist on the insulating layer;
(3) simultaneously imprinting patterns of a source electrode, a drain electrode and a grid electrode on the upper surface of the negative photoresist by a nano imprinting technology, and curing the negative photoresist by ultraviolet irradiation of 254 ~ 365 nm;
(4) removing the negative photoresist and the insulating layer below the bottom of the source electrode and drain electrode pattern by an etching process to expose the barrier layer, thereby realizing the transfer of the source electrode and drain electrode pattern from the negative photoresist to the wafer;
(5) Removing the negative photoresist under the bottom of the pattern of the grid electrode by an etching process to expose the insulating layer and realize the transfer of the grid electrode pattern from the negative photoresist to the wafer;
(6) evaporating a metal layer on the negative photoresist, the barrier layer exposed in the step (4) and the upper surface of the insulating layer exposed in the step (5), removing the negative photoresist and the metal layer on the upper surface of the negative photoresist in a photoresist removing solution after evaporation, and forming a source electrode and a drain electrode on the metal layer on the upper surface of the barrier layer exposed in the step (4) correspondingly; forming a grid electrode on the exposed metal layer on the upper surface of the insulating layer in the step (5);
(7) the source and drain electrodes are brought into ohmic contact with the channel layer by thermal annealing.
8. the method for synchronously manufacturing a source, a drain and a gate of a GaN HEMT device according to claim 7, wherein the deposition method of the insulating layer in the step (1) is one of metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition, pulsed laser deposition, atomic layer deposition and molecular beam epitaxy;
the thickness of the negative photoresist in the step (2) is 400 ~ 1600 nm;
the ultraviolet curing time in the step (3) is 30 ~ 60 seconds, and is related to the thickness of the negative photoresist.
9. the method for synchronously preparing the source, the drain and the gate of the GaN HEMT device according to claim 7, wherein the etching process in the steps (4) and (5) adopts Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP); use of O in etching negative photoresist2The method comprises the following steps of selecting/Ar as etching gas, and selecting carbon tetrafluoride/trifluoromethane/Ar, carbon tetrafluoride/trifluoromethane/Ar and chlorine/boron trichloride/Ar as etching gas when an insulating layer is etched;
The evaporation method of the metal electrode in the step (6) is electron beam evaporation or magnetron sputtering;
the thermal annealing temperature in the step (7) is 700 ~ 900 ℃, and the time is 30 ~ 60 seconds.
10. the method for synchronously manufacturing a source, a drain and a gate of a GaN HEMT device according to claim 7, wherein in the step (3), a foil pattern is printed on the upper surface of the negative photoresist by a nano-imprinting technique, the foil pattern is connected with the gate pattern, the bottom surface of the foil pattern is the upper surface of the insulating layer, and the depth of the foil pattern is the same as that of the gate pattern.
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