CN110535789B

CN110535789B - SRIO-ETH protocol conversion chip verification device and method

Info

Publication number: CN110535789B
Application number: CN201910628138.9A
Authority: CN
Inventors: 沈剑良; 郭中孚; 吕平; 汪欣; 陈艇; 李沛杰; 高彦钊; 张霞; 刘冬培; 于洪
Original assignee: Information Engineering University of PLA Strategic Support Force
Current assignee: Information Engineering University of PLA Strategic Support Force
Priority date: 2019-07-12
Filing date: 2019-07-12
Publication date: 2021-07-23
Anticipated expiration: 2039-07-12
Also published as: CN110535789A

Abstract

The invention provides a device and a method for verifying an SRIO-ETH protocol conversion chip, which comprises a TX end, an RX end and a packet counting conversion rule calculation module, wherein the packet counting conversion rule calculation module comprises a packet counting submodule and a macro definition submodule; the TX terminal is used for sending a source protocol packet to a protocol conversion chip, the protocol conversion chip analyzes and extracts payload of the source protocol packet and forms a target protocol packet to be routed to the RX terminal, the RX terminal analyzes the target protocol packet to obtain the payload, the target protocol corresponds to an ETH protocol when the source protocol is an SRIO protocol, the ETH protocol corresponds to the SRIO protocol when the source protocol is the ETH protocol, the macro definition submodule is used for configuring counting check information for the RX terminal and the TX terminal, and the packet counting submodule extracts the counting check information and then counts packets. The invention improves the testing capability of the protocol conversion chip with different fragmentation rules, and ensures that the whole device has wider application range and higher flexibility.

Description

SRIO-ETH protocol conversion chip verification device and method

Technical Field

The invention belongs to the technical field of chip verification, and particularly relates to a verification device for an SRIO-ETH conversion chip.

Background

With the gradual popularization of 5G and the Internet of things, everything can be interconnected, the shackles of communication among all protocols are finely and silently broken, and a protocol conversion chip is needed to erect an interconnection bridge. The ETH (Ethernet) protocol is a widely used protocol because it supports multi-layer encapsulation, is suitable for down to the physical layer and up to the application layer, and has a wide application range and high flexibility. While the high-performance distributed embedded processing system mostly adopts Serial Rapid Io (SRIO) as an interface standard, SRIO signal routing is less, signal interference is effectively reduced, pin resources can be saved, high-accuracy transmission is provided, and the distributed embedded processing system is widely used for routing connection of embedded interconnection and a back plate. Therefore, a large number of protocol conversion chips for realizing ETH to SRIO appear in the current market, and a cross-architecture data transmission channel is provided for a hardware acceleration system.

The ETH-SRIO bridging device is designed, the protocol of each high-speed serial data interface can be defined into any one of the two protocols through software, and the non-blocking, low-delay and high-reliability interconnection and intercommunication between the two heterogeneous protocols can be realized. The bridge device of ETH and SRIO has wide application scene and powerful functions, and can bring great convenience in many fields by successful development.

In the development stage of the chip, how to verify that the conversion chip has the protocol conversion function is an important topic. At present, no proper scheme is available for completing the function test of the protocol conversion chip, and the function verification test scheme aiming at the single protocol forwarding chip is to compare the packet counts of a sending end and a receiving end by statistics to check whether the function of the forwarding chip is normal.

The protocol conversion chip can be verified through UVM logic simulation, but the simulation speed of the method is slow, when the scale of a digital circuit is large, the logic simulation speed becomes slower, the verification period of the whole project becomes long, and the lead period of the whole project is limited; generally, the function verification based on the FPGA is performed by performing statistics on packet counts at the transmitting end and the receiving end and comparing the statistics on the packet counts, and when the function of the protocol conversion chip is verified, it is impossible to directly compare whether the packet counts are equal to determine whether the protocol conversion function is normal. Or the correctness of the protocol conversion cannot be determined by checking the CRC check bits alone, since there may be cases where the entire packet is lost. Or a single protocol forwarding function verification scheme such as a scheme of performing cumulative counting by packet counting at a sending end is not suitable for function verification of the protocol conversion chip. In the test, the PAYLOAD of the sending end and the receiving end can be considered to be checked, manual comparison is carried out, time and labor are consumed, and the test of line rate is not supported.

Considering that in the process of protocol conversion, the length of data packets supported by different protocols is different due to protocol conversion in the transmission process of the data packets, and at this time, the number of the data packets may change, and it is desired to compare whether the number of the data packets at the receiving end and the sending end conforms to the protocol conversion rule, and it is only possible to calculate the change of the number of the packets before and after the protocol conversion by analyzing the conversion rule between different protocols by a tester, and further compare whether the number of the data packets is correct, so a large amount of human resources are consumed, and considering that the number of the packets sent in a test scene is large, and the real-time verification of the line rate cannot be performed.

Meanwhile, most protocols can adopt a self-defined packet cutting rule, when a receiving port is changed, the packet cutting rule can be completely changed, and meanwhile, considering that the slicing rules between ports are not understood to be possibly different, if the packet counting and checking rules are reconfigured one by one, the speed of the whole test can be influenced.

Disclosure of Invention

In view of the above, the present invention is directed to a device and a method for verifying an SRIO-ETH protocol conversion chip, so as to solve the above problems.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

the SRIO-ETH protocol conversion chip verification device comprises a TX end, an RX end and a packet counting conversion rule calculation module, wherein the packet counting conversion rule calculation module comprises a packet counting submodule and a macro definition submodule;

the TX terminal is used for sending a source protocol packet to a protocol conversion chip, the protocol conversion chip analyzes and extracts an effective load payload of the source protocol packet and forms a target protocol packet to be routed to the RX terminal, the RX terminal analyzes the target protocol packet to obtain the effective load payload, the target protocol corresponds to an ETH protocol when the source protocol is an SRIO protocol, the ETH protocol corresponds to an SRIO protocol when the source protocol is the ETH protocol, the macro definition submodule is used for configuring counting check information for the RX terminal and the TX terminal, and the packet counting submodule extracts the counting check information and then counts packets.

Further, the TX end includes a PAYLOAD _ GEN module, a PKT _ GEN module, a TX _ PKT _ CNT module, and a TX _ Port module, which are connected in sequence, where the PAYLOAD _ GEN module is configured to generate a PAYLOAD in the source protocol packet, the PKT _ GEN module is configured to encapsulate the PAYLOAD into a source protocol packet, the TX _ PKT _ CNT module is configured to calculate the number of the source protocol packets, and the TX _ Port module is the TX end Port.

Further, the RX end includes an RX _ Port module, an RX _ PKT _ CNT module, a PKT _ GET module, and a PAYLOAD _ GET module, which are connected in sequence, where the RX _ Port module is the RX end Port, the RX _ PKT _ CNT module is used to calculate the number of the target protocol packets, the PKT _ GET module is used to parse the target protocol packets, and the PAYLOAD _ GET module is used to obtain PAYLOAD of the target protocol packets.

Further, the Macro definition sub-module includes an SDI interface unit configured to configure the TX _ Port module and the RX _ Port module, and a Macro _ Define unit configured to configure count check information for the TX _ PKT _ CNT module and the RX _ PKT _ CNT module.

Further, the packet counting sub-module includes a GET _ CNT unit for extracting count verification information of the TX end and the RX end, and a PKT _ CNT _ call unit for packet counting.

Further, the TX _ PKT _ CNT module and the RX _ PKT _ CNT module further include a packet type counting unit for completing packet type counting by extracting FTYPE fields of different packet types.

A SRIO-ETH protocol conversion chip verification method applying the verification device is characterized by comprising the following steps:

step 1: the TX end generates an effective load payload, encapsulates the effective load payload into a source protocol packet and sends the source protocol packet to a protocol conversion chip;

step 2: the protocol conversion chip receives the source protocol packet, analyzes and packages the source protocol packet to generate a target protocol packet;

and step 3: the RX end receives the target protocol packet and analyzes the target protocol packet to generate payload;

and 4, step 4: configuring the TX terminal and the RX terminal through the macro definition submodule;

and 5: counting the packets by the packet counting submodule and outputting a packet counting result;

further, the step 1 further includes calculating the number of the source protocol packets by the TX _ PKT _ CNT module, and the step 3 further includes calculating the number of the target protocol packets by the RX _ PKT _ CNT module.

Further, the step 4 comprises: configuring the TX _ Port module and the RX _ Port module through the SDI interface unit, and configuring count check information for the TX _ PKT _ CNT module and the RX _ PKT _ CNT module through the Macro _ Define unit.

Further, the step 5 comprises:

step 51: initializing the maximum packet length RX _ MAX _ L and the packet counting result Pre _ C _ Cnt received by a TX end sending packet length TX _ P _ L, RX end;

step 52: extracting the counting verification information through a GET _ CNT unit and starting verification;

step 53: counting packets by the PKT _ CNT _ CALCULATITE unit: comparing the length TX _ P _ L of a source protocol packet with the maximum packet length RX _ MAX _ L of a receiving end;

step 54: when TX _ P _ L > RX _ MAX _ L, the packet count result Pre _ C _ Cnt is (TX _ P _ L/RX _ MAX _ L) + X, X ≧ 1, and when TX _ P _ L is ≦ RX _ MAX _ L, the packet count result Pre _ C _ Cnt is GEN _ Cnt, where GEN _ Cnt is the TX-side packet count.

Compared with the prior art, the device and the method for verifying the SRIO-ETH protocol conversion chip have the following advantages that:

(1) the verification device provided by the invention is provided with the packet counting submodule and the macro definition submodule, so that the test capability of protocol conversion chips with different fragmentation rules is greatly improved, and the whole device has wider application range and higher flexibility.

(2) The invention supports the bidirectional simultaneous data packet sending and verification.

(3) The package type counting unit is arranged, and data acquisition of later debugging work is facilitated.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic structural diagram of a verification apparatus when a TX end is an ETH protocol device and an RX end is an SRIO protocol device according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart illustrating a verification method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a verification apparatus when an SRIO end is a protocol device and an RX end is an ETH protocol device according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a verification apparatus for simultaneously verifying that an ETH protocol is converted into an SRIO protocol and that the SRIO protocol is converted into the ETH protocol according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

the TX terminal is used for sending a source protocol packet to a protocol conversion chip, the protocol conversion chip analyzes and extracts payload of the source protocol packet and forms a target protocol packet to be routed to the RX terminal, the RX terminal analyzes the target protocol packet to obtain the payload, the target protocol corresponds to an ETH protocol when the source protocol is an SRIO protocol, the ETH protocol corresponds to the SRIO protocol when the source protocol is an ETH protocol, the macro definition submodule is used for configuring counting check information for the RX terminal and the TX terminal, and the packet counting submodule extracts the counting check information and then counts packets.

The TX end comprises a PAYLLOAD _ GEN module, a PKT _ GEN module, a TX _ PKT _ CNT module and a TX _ Port module which are connected in sequence, wherein the PAYLLOAD _ GEN module is used for generating PAYLOAD in the source protocol packet, the PKT _ GEN module is used for packaging the PAYLOAD into the source protocol packet, the TX _ PKT _ CNT module is used for calculating the number of the source protocol packet, and the TX _ Port module is the TX end Port.

The RX end includes an RX _ Port module, an RX _ PKT _ CNT module, a PKT _ GET module, and a PAYLOAD _ GET module, which are connected in sequence, where the RX _ Port module is the RX end Port, the RX _ PKT _ CNT module is used to calculate the number of the target protocol packets, the PKT _ GET module is used to parse the target protocol packets, and the PAYLOAD _ GET module is used to obtain PAYLOAD of the target protocol packets.

The Macro definition submodule comprises an SDI interface unit and a Macro _ Define unit, wherein the SDI interface unit is used for configuring the TX _ Port module and the RX _ Port module, and the Macro _ Define unit is used for configuring counting checking information for the TX _ PKT _ CNT module and the RX _ PKT _ CNT module.

The packet counting submodule comprises a GET _ CNT unit for extracting counting verification information of the TX end and the RX end, and a PKT _ CNT _ calibration unit for performing packet counting.

The TX _ PKT _ CNT module and the RX _ PKT _ CNT module further include a packet type counting unit, which completes packet type counting by extracting FTYPE fields of different packet types, for example, an SRIO protocol packet includes the following 6 types: NREAD, NWRITE, NWRITE _ R, DOORBELL, MESSAGE, RESPONS, generate different queues for counting for different types of packet formats, because packets of different transaction types are different in FTYPE, counting can be completed by extracting the FTYPE field:

the invention also provides a method for verifying the SRIO-ETH protocol conversion chip by applying the verification device, which comprises the following steps as shown in FIG. 2:

step 1: at the TX end, the PAYLOAD _ GEN module generates an effective load PAYLOAD in a source protocol packet, and the effective load PAYLOAD is packaged by the PKT _ GEN module and then sent to a protocol conversion chip;

and step 3: at the RX end, the PKT _ GET module analyzes a target protocol packet, and the PAYLLOAD _ GET module obtains an effective load PAYLOAD in the target protocol packet, receives the target protocol packet and analyzes the effective load PAYLOAD to generate the effective load PAYLOAD;

preferably, the step 1 further includes calculating the number of the source protocol packets by the TX _ PKT _ CNT module, the step 3 further includes calculating the number of the target protocol packets by the RX _ PKT _ CNT module, and the step 4 includes: configuring the TX _ Port module and the RX _ Port module through the SDI interface unit, and configuring count check information for the TX _ PKT _ CNT module and the RX _ PKT _ CNT module through the Macro _ Define unit.

Preferably, the step 5 comprises:

step 54: when TX _ P _ L > RX _ MAX _ L, the packet count result Pre _ C _ Cnt is (TX _ P _ L/RX _ MAX _ L) + X, X ≧ 1, and when TX _ P _ L is ≦ RX _ MAX _ L, the packet count result Pre _ C _ Cnt is GEN _ Cnt, where GEN _ Cnt is the TX-side packet count. Generally, the part exceeding the maximum packet length received by the RX end is directly encapsulated into 1 packet, and the value of X is 1 at this time, but considering that the unpacking rule of the ratio remainder part may split the surface user universality into the length of 2 raised to the power of an integer, or an unpacking rule applicable to a specific scenario is adopted, and X is greater than or equal to 1 at this time.

As shown in fig. 1, in a case that a TX end, that is, a transmitting end is an ETH protocol device, and an RX end, that is, a receiving end is an SRIO protocol device, a DUT module, that is, a protocol conversion chip in the drawing converts a packet in an ETH protocol format into an SRIO protocol packet recognizable by the RX end, and at the TX end, a PKT _ GEN module packages PAYLOAD data into a packet in an ETH protocol, where the DUT module includes a Parser unit, a DE-Parser unit, a PKT _ Segment unit, and a Head _ kernel unit, the DUT module receives the ETH protocol packet and parses through the Parser unit, extracts PAYLOAD in the received protocol packet and judges whether the packet needs to be segmented by the PKT _ Segment unit, the Head _ kernel unit reads a target protocol encapsulation rule and encapsulates the packet by the DE-Parser unit to generate and route the SRIO protocol packet to the RX end, and the RX end obtains an effective PAYLOAD in the SRIO protocol packet by the pad _ GET module, the PAYLOAD _ CHECK module records the PAYLOAD length of each packet, CALCULATEs the number of packets of the SRIO protocol through the PKT _ CNT _ CALCULATE unit, compares the packet count result with the packet count result at the RX end, and if the packet count result is the same with the packet count result, the protocol conversion chip is proved to meet the performance requirement.

Considering that the SRIO protocols corresponding to different ports have different fragmentation rules, firstly, Macro definition instruction information is input to the TX _ Port and the RX _ Port through the SDI interface unit, and count check information is configured to the TX _ PKT _ CNT module and the TX _ PKT _ CNT module through the Macro _ Define unit, where the count check information includes protocol information and transceiver status of each Port, and a protocol information format for each Port is: (Port _ Num, protocol type, packet specification), GET _ CNT unit extracts count check information, and counts packets through the PKT _ CNT _ calculation unit, for example, in a fragmentation manner, an integer power of 2, and if the received ETH packet length is 255, 7 SRIO packets are generated, and the packet lengths are 128, 64, 32, 16, 8, 4, 2, and 1, respectively. The value of X is then 7.

For example, as shown in fig. 3, in the case where the TX end is an SRIO protocol device and the RX end is an ETH protocol device, because the SRIO protocol PAYLOAD length can be directly encapsulated into a single packet in the ETH format, the packet in the ETH format is not converted into a split packet in the SRIO format, but the packet count may not be in a one-to-one correspondence relationship in some special scenarios, so that the packet number calculation module is still reserved.

As shown in fig. 4, for bi-directionally and simultaneously sending and verifying the data packet, the SRIO protocol may be simultaneously verified to be converted into the ETH protocol and the ETH protocol to be converted into the SRIO protocol, and the TX end and the RX end are combined together, in which case the two endpoint devices need to simultaneously take on the functions of the sending device and the verifying device.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

The SRIO-ETH protocol conversion chip verification device is characterized in that: the system comprises a TX end, an RX end and a packet counting conversion rule calculation module, wherein the packet counting conversion rule calculation module comprises a packet counting submodule and a macro definition submodule;

the TX terminal is used for sending a source protocol packet to a protocol conversion chip, the protocol conversion chip analyzes and extracts an effective load payload of the source protocol packet and forms a target protocol packet to be routed to the RX terminal, the RX terminal analyzes the target protocol packet to obtain the effective load payload, the target protocol corresponds to an ETH protocol when the source protocol is an SRIO protocol, the target protocol corresponds to an SRIO protocol when the source protocol is the ETH protocol, the macro definition submodule is used for configuring counting check information for the RX terminal and the TX terminal, and the packet counting submodule extracts the counting check information and then counts packets; the packet counting submodule comprises a PKT _ CNT _ call unit, and is used for packet counting, and specifically used for: comparing the length TX _ P _ L of a source protocol packet with the maximum packet length RX _ MAX _ L of a receiving end; when TX _ P _ L > RX _ MAX _ L, a packet counting result Pre _ C _ Cnt = (TX _ P _ L/RX _ MAX _ L) + X, X is more than or equal to 1, when TX _ P _ L is less than or equal to RX _ MAX _ L, the packet counting result Pre _ C _ Cnt = GEN _ Cnt, wherein GEN _ Cnt is the TX-end packet count; and comparing the result with the packet counting result at the RX end, and if the result is the same, indicating that the protocol conversion chip meets the performance requirement.
2. The SRIO-ETH protocol conversion chip authentication device of claim 1, wherein: the TX end comprises a PAYLLOAD _ GEN module, a PKT _ GEN module, a TX _ PKT _ CNT module and a TX _ Port module which are connected in sequence, wherein the PAYLLOAD _ GEN module is used for generating PAYLOAD in the source protocol packet, the PKT _ GEN module is used for packaging the PAYLOAD into the source protocol packet, the TX _ PKT _ CNT module is used for calculating the number of the source protocol packet, and the TX _ Port module is the TX end Port.
3. The SRIO-ETH protocol conversion chip authentication device of claim 2, wherein: the RX end includes an RX _ Port module, an RX _ PKT _ CNT module, a PKT _ GET module, and a PAYLOAD _ GET module, which are connected in sequence, where the RX _ Port module is the RX end Port, the RX _ PKT _ CNT module is used to calculate the number of the target protocol packets, the PKT _ GET module is used to parse the target protocol packets, and the PAYLOAD _ GET module is used to obtain PAYLOAD of the target protocol packets.
4. The SRIO-ETH protocol conversion chip authentication device of claim 3, wherein: the Macro definition submodule comprises an SDI interface unit and a Macro _ Define unit, wherein the SDI interface unit is used for configuring the TX _ Port module and the RX _ Port module, and the Macro _ Define unit is used for configuring counting checking information for the TX _ PKT _ CNT module and the RX _ PKT _ CNT module.
5. The SRIO-ETH protocol conversion chip authentication device of claim 3, wherein: the packet counting submodule comprises a GET _ CNT unit for extracting counting verification information of the TX end and the RX end, and a PKT _ CNT _ calibration unit for counting packets.
6. The SRIO-ETH protocol conversion chip authentication device of claim 3, wherein: the TX _ PKT _ CNT module and the RX _ PKT _ CNT module further include a packet type counting unit that completes packet type counting by extracting FTYPE fields of different packet types.
7. The SRIO-ETH protocol conversion chip authentication method applied to the authentication apparatus according to claim 1, comprising the steps of:

step 1: the TX end generates an effective load payload, encapsulates the effective load payload into a source protocol packet and sends the source protocol packet to a protocol conversion chip;

step 2: the protocol conversion chip receives the source protocol packet, analyzes and encapsulates the source protocol packet to generate a target protocol packet, and routes the target protocol packet to an RX end;

and step 3: the RX end receives the target protocol packet and analyzes the target protocol packet to generate payload;

and 4, step 4: configuring counting check information for the TX terminal and the RX terminal through the macro definition submodule;

and 5: and counting the packets by the packet counting submodule and outputting a packet counting result.
8. The SRIO-ETH protocol conversion chip verification method according to claim 7, wherein: the TX end comprises a TX _ PKT _ CNT module, and correspondingly, the step 1 further comprises calculating the number of the source protocol packets by the TX _ PKT _ CNT module; the RX end comprises an RX _ PKT _ CNT module; correspondingly, the step 3 further includes calculating, by the RX _ PKT _ CNT module, the number of the target protocol packets.
9. The SRIO-ETH protocol conversion chip verification method according to claim 8, wherein: the Macro definition submodule comprises an SDI interface unit and a Macro _ Define unit; correspondingly, the step 4 comprises the following steps: configuring a TX _ Port module and an RX _ Port module through the SDI interface unit, and configuring count check information for the TX _ PKT _ CNT module and the RX _ PKT _ CNT module through the Macro _ Define unit; wherein the TX _ Port module is the TX Port, and the RX _ Port module is the RX Port.
10. The SRIO-ETH protocol conversion chip verification method according to claim 7, wherein: the packet counting submodule comprises a GET _ CNT unit; correspondingly, the step 5 comprises the following steps:

step 51: initializing the maximum packet length RX _ MAX _ L and the packet counting result Pre _ C _ Cnt received by a TX end sending packet length TX _ P _ L, RX end;

step 52: extracting the counting verification information through a GET _ CNT unit and starting verification;

step 53: counting packets by the PKT _ CNT _ CALCULATITE unit: comparing the length TX _ P _ L of a source protocol packet with the maximum packet length RX _ MAX _ L of a receiving end;

step 54: when TX _ P _ L > RX _ MAX _ L, the packet count result Pre _ C _ Cnt = (TX _ P _ L/RX _ MAX _ L) + X, X ≧ 1, and when TX _ P _ L is ≦ RX _ MAX _ L, the packet count result Pre _ C _ Cnt = GEN _ Cnt, where GEN _ Cnt is the TX-side packet count.