CN110502210B - Low frequency integration circuit and method - Google Patents
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Abstract
The invention provides a low-frequency integrating circuit and a method, comprising the following steps: a subtracter for subtracting the current sampling value from the reference signal; a first switch for sampling an output signal of the low frequency integration circuit; the adder is used for adding the last integral output value and the output signal of the subtracter; a second switch sampling an output signal of the adder; a first capacitor for sample and hold and a second capacitor; wherein the polarity of the control signals of the first switch and the second switch is opposite. And feeding back the last integral output value to a first addition input end of the adder, inputting a value obtained by subtracting the current sampling value from the reference signal to a second addition input end of the adder, and outputting the current integral output value after addition operation is carried out through the adder. The invention can realize the low-frequency filtering function without an external capacitor, a digital circuit and a singlechip, is convenient to integrate and has low cost.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a low-frequency integrating circuit and a method.
Background
The integrating circuit is mainly used for waveform conversion, elimination of offset voltage of an amplifying circuit, integral compensation in feedback control and the like. In general, a power factor correction circuit needs to perform loop control by integrating a low-frequency periodic signal such as a power frequency current to obtain an average current. As shown in fig. 1, the integration of the low-frequency periodic signal can be realized by a simple operational amplifier circuit, which includes an operational amplifier 1, a resistor R and a capacitor C, wherein one end of the resistor R receives an input signal, the other end of the resistor R is connected to the inverting input terminal of the operational amplifier 1, one end of the capacitor C is connected to the inverting input terminal of the operational amplifier 11, the other end of the capacitor C is connected to the output terminal of the operational amplifier 1, and the non-inverting input terminal of the operational amplifier 11 is connected to a reference signal Vref. The output signal of the circuit satisfies the following relation:
wherein vin (t) is a voltage signal converted from the power frequency current, Vref is an internal reference voltage signal, and vo (t) is an obtained output control signal. In order to process a low-frequency periodic signal, the capacitor C is large and cannot be integrated into a chip generally, so that the capacitor in this way needs to be placed outside the chip and 2 pins are needed.
In order to reduce the number of pins, the output of one pin can be realized by using a transconductance operational amplifier, as shown in fig. 2, a non-inverting input terminal of a transconductance operational amplifier 2 receives a reference signal, an inverting input terminal of the transconductance operational amplifier receives an input signal, and one end of a capacitor C is connected to the output terminal of the transconductance operational amplifier, and the other end is grounded. The output signal of the circuit satisfies the following relation:
normalizing equation (1) and equation (2) to obtain equation (3):
wherein K is a normalized proportionality coefficient, and satisfies the following conditions:
the low-frequency signal is considered to be kept unchanged in the sampling time during the high-frequency sampling, so that the integration function can be realized by digitally calculating the periodic signal with the average value as the reference value, and a desired output control signal can be obtained. However, the low frequency integrator implemented by a digital circuit or a single chip microcomputer has a high cost, and cannot be used in a general analog circuit process.
Therefore, how to avoid using large capacitors in the integrator, reduce the cost, and adapt to the analog circuit process has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a low frequency integrator and a method thereof, which are used to solve the problems in the prior art that a large capacitor cannot be integrated, and a low frequency integrator implemented in a digital circuit or a single chip microcomputer has high cost and is not suitable for an analog circuit.
To achieve the above and other related objects, the present invention provides a low frequency integration circuit, comprising:
the circuit comprises a subtracter, an adder, a first switch, a second switch, a first capacitor and a second capacitor;
the adder input end of the subtracter receives a reference signal, and the subtractor input end of the subtracter receives a current sampling value and is used for carrying out the operation of subtracting the current sampling value from the reference signal;
the input end of the first switch is connected with the output end of the low-frequency integrating circuit, and the output end of the first switch is connected with the upper polar plate of the first capacitor and used for sampling the output signal of the low-frequency integrating circuit; the lower polar plate of the first capacitor is grounded;
a first adding input end of the adder is connected with a last integral output value output by the first switch, and a second adding input end of the adder is connected with an output end of the subtracter and is used for adding the last integral output value and an output signal of the subtracter;
the input end of the second switch is connected with the output end of the adder, and the output end of the second switch is used as the output end of the low-frequency integrating circuit and is used for sampling the output signal of the adder;
the upper polar plate of the second capacitor is connected with the output end of the second switch, and the lower polar plate is grounded;
wherein the polarity of the control signals of the first switch and the second switch is opposite.
Preferably, the subtractor comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier;
one end of the first resistor is used as a subtraction input end of the subtracter, and the other end of the first resistor is connected with an inverting input end of the first operational amplifier;
one end of the second resistor is connected with the inverting input end of the first operational amplifier, and the other end of the second resistor is connected with the output end of the first operational amplifier;
one end of the third resistor is used as an addition input end of the subtracter, and the other end of the third resistor is connected with a positive phase input end of the first operational amplifier;
one end of the fourth resistor is connected with the positive phase input end of the first operational amplifier, and the other end of the fourth resistor is grounded.
Preferably, the adder includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a second operational amplifier;
one end of the fifth resistor is used as a first addition input end of the adder, and the other end of the fifth resistor is connected with a non-inverting input end of the second operational amplifier;
one end of the sixth resistor is used as a second addition input end of the adder, and the other end of the sixth resistor is connected with a non-inverting input end of the second operational amplifier;
one end of the seventh resistor is connected with the inverting input end of the second operational amplifier, and the other end of the seventh resistor is grounded;
one end of the eighth resistor is connected with the inverting input end of the second operational amplifier, and the other end of the eighth resistor is connected with the output end of the second operational amplifier.
Preferably, the low frequency integration circuit further comprises a first follower connected between the current sample value and the subtraction input terminal of the subtractor, a second follower connected between the output terminal of the first switch and the first addition input terminal of the adder, and a third follower connected between the output terminal of the second switch and the output terminal of the low frequency integration circuit, each follower for isolating a signal.
Preferably, the low frequency integration circuit further comprises a switch control signal generation module; the switch control signal generating module comprises a high-frequency sampling unit and an inverter; the high-frequency sampling unit is used for generating square wave signals; the phase inverter is connected to the output end of the high-frequency sampling unit and used for generating an inverse signal of the output signal of the high-frequency sampling unit.
Preferably, the capacitance values of the first capacitor and the second capacitor are in the pF level.
Preferably, the low-frequency integrating circuit further includes a first scaling factor adjusting module and a second scaling factor adjusting module, the first scaling factor adjusting module is connected between the output end of the subtractor and the second adding input end of the adder, and the second scaling factor adjusting module is connected between the current sample value and the subtracting input end of the subtractor.
More preferably, the low frequency integration circuit further comprises a third switch having an output connected to the input of the low frequency integration circuit, and a third capacitor connected to the output of the third switch.
More preferably, the low-frequency integrating circuit further comprises a peak sampling module, and an output end of the peak sampling module is connected to a control end of the third switch, and is used for controlling the third switch to perform sampling; and the capacitance value of the third capacitor is in a pF level.
To achieve the above and other related objects, the present invention further provides a low frequency integration method of the above low frequency integration circuit, the low frequency integration method at least comprising:
and feeding back the last integral output value to a first addition input end of the adder, inputting a value obtained by subtracting the current sampling value from the reference signal to a second addition input end of the adder, and outputting the current integral output value after addition operation is carried out through the adder.
Preferably, the current integrated output value satisfies the following relation:
Vo(n)＝K1*(Vref-K2*Vin(n))+Vo(n-1)，
wherein, Vo(n) is the current integrated output value, K1 is the first scaling factor, K2 is the second scaling factor, Vin(n) is the current sample value, VoAnd (n-1) is the last integration output value.
More preferably, the first and second scaling factors are determined by adjusting the resistances of the inputs of the subtractor and the adder; or the first scaling factor and the second scaling factor are determined by a first scaling factor adjusting module arranged between the output end of the subtracter and the second adding input end of the adder and a second scaling factor adjusting module arranged between the current sampling value and the subtracting input end of the subtracter.
Preferably, the low frequency integration method further comprises: receiving the peak current of a switching tube in a power factor correction circuit, sampling the peak current of the switching tube based on peak sampling to obtain an envelope waveform of the peak current of the switching tube, and obtaining a direct current feedback loop control signal through integration to further remove a compensation capacitor in the power factor correction circuit.
As described above, the low frequency integration circuit and method of the present invention have the following advantages:
1. the low-frequency integration circuit and the method can realize the low-frequency integration function without an external capacitor, are convenient to integrate and have low cost.
2. The low-frequency integration circuit and the method can realize digital integration without a digital circuit or a singlechip, and the cost is greatly reduced.
3. The low-frequency integrating circuit and the method can obtain the integral value of the peak current envelope waveform of the switching tube by matching with a peak sampling technology, thereby saving an integrating compensation capacitor such as a power factor correction circuit and the like which need to filter low-frequency ripples, further reducing the number of pins and reducing the cost.
Drawings
Fig. 1 shows a schematic diagram of an integrating circuit implemented by an operational amplifier circuit in the prior art.
Fig. 2 shows a schematic diagram of an integrating circuit implemented by a transconductance operational amplifier in the prior art.
Fig. 3 is a schematic diagram of a low frequency integration circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating the operation of the low frequency integration circuit of the present invention.
Fig. 5 is a schematic diagram of another embodiment of the low frequency integration circuit of the present invention.
Fig. 6 is a schematic diagram of a low frequency integration circuit according to another embodiment of the present invention.
Fig. 7 is a schematic diagram of a low frequency integration circuit according to still another embodiment of the present invention.
Fig. 8 is a schematic diagram of a power factor correction circuit in the prior art.
Fig. 9 is a schematic diagram of the low frequency integrator circuit of the present invention applied to a power factor correction circuit.
Description of the element reference numerals
1 operational amplifier
2 transconductance operational amplifier
3 low frequency integrating circuit
31 subtracter
311 first operational amplifier
32 adder
321 second operational amplifier
33 switch control signal generating module
331 high frequency sampling unit
332 inverter
341 to 343 first to third followers
35 first scale factor adjusting module
36 second proportionality coefficient adjusting module
37 peak value sampling module
4 power factor correction circuit
41 compensation module
42 comparison module
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
To achieve the above and other related objects, the present invention provides a low frequency integration circuit 3, wherein the low frequency integration circuit 3 includes:
the circuit comprises a subtracter 31, an adder 32, a first switch S1, a second switch S2, a first capacitor C1, a second capacitor C2 and a switch control signal generation module 33.
As shown in fig. 3, the subtractor 31 has an adding input receiving the reference signal Vref and a subtracting input receiving the current sample value Vin(n) for subtracting the current sample value V from the reference signal VrefinAnd (n) calculating.
Specifically, in the present embodiment, the subtractor 31 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first operational amplifier 311. One end of the first resistor R1 is used as the subtraction input end of the subtractor 31, and the other end is connected to the inverting input end of the first operational amplifier 311; one end of the second resistor R2 is connected to the inverting input terminal of the first operational amplifier 311, and the other end is connected to the output terminal of the first operational amplifier 311; one end of the third resistor R3 is used as an adding input end of the subtractor 31, and the other end is connected to a non-inverting input end of the first operational amplifier 311; one end of the fourth resistor R4 is connected to the non-inverting input terminal of the first operational amplifier 311, and the other end is grounded. Optionally, said reference signal Vref minus said current sample value VinThe circuit structure of (n) is applicable to the embodiment, and is not limited to the embodiment.
As shown in fig. 3, an input terminal of the first switch S1 is connected to an output terminal of the low frequency integration circuit 3, and an output terminal of the first switch S1 is connected to an upper plate of the first capacitor C1 for sampling an output signal of the low frequency integration circuit 3.
Specifically, the first switch S1 is used as a sampling switch, and the sampling frequency can be set according to the sampling requirement by the control signal frequency of the first switch S1, but not necessarily set here. In this embodiment, the first switch S1 performs high frequency sampling.
As shown in fig. 3, the upper plate of the first capacitor C1 is connected to the output terminal of the first switch S1, and the lower plate of the first capacitor C1 is grounded. The first capacitor C1 is used as a sample-and-hold capacitor for holding the sampled output signal of the low frequency integration circuit 3 on the first capacitor C1.
Specifically, the capacitance value of the first capacitor C1 is pF level, and can be integrated in a chip.
As shown in fig. 3, the first adding input terminal of the adder 32 is connected to the last integral output value V outputted by the first switch S1O(n-1), a second adding input terminal of the adder 32 is connected to the output terminal of the subtracter 31, and is used for outputting the last integration output value VO(n-1) and the output signal of the subtractor 31.
Specifically, in the present embodiment, the adder 32 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a second operational amplifier 321. One end of the fifth resistor R5 is used as the first adding input end of the adder 32, and the other end is connected to the non-inverting input end of the second operational amplifier 321; one end of the sixth resistor R6 is used as the second adding input end of the adder 32, and the other end is connected to the non-inverting input end of the second operational amplifier 321; one end of the seventh resistor R7 is connected to the inverting input terminal of the second operational amplifier 321, and the other end is grounded; one end of the eighth resistor R8 is connected to the inverting input terminal of the second operational amplifier 321, and the other end is connected to the output terminal of the second operational amplifier 321. The last integral output value V can be arbitrarily realizedO(n-1) added to the output signal of the subtractor 31The circuit structure is suitable for this embodiment, and is not limited to this embodiment.
As shown in fig. 3, an input terminal of the second switch S2 is connected to the output terminal of the adder 32, and an output terminal of the second switch S2 is used as an output terminal of the low frequency integration circuit 3, for sampling the output signal of the adder 32.
Specifically, the second switch S2 is used as a sampling switch, and the sampling frequency can be set according to the sampling requirement by the control signal frequency of the second switch S2, but not necessarily set here. In this embodiment, the second switch S2 performs high frequency sampling.
As shown in fig. 3, the upper plate of the second capacitor C2 is connected to the output terminal of the second switch S2, and the lower plate of the second capacitor C2 is grounded. The second capacitor C2 is used as a sample-and-hold capacitor for holding the sampled output signal of the adder 32 on the second capacitor C2.
Specifically, the capacitance of the second capacitor C2 is of the pF level, and can be integrated in a chip.
As shown in fig. 3, the switch control signal generating module 33 is connected to the control ends of the first switch S1 and the second switch S2, and is configured to control the first switch S1 and the second switch S2 to be turned on and off, so as to implement sampling.
Specifically, the switch control signal generating module 33 includes a high-frequency sampling unit 331 and an inverter 332, where the high-frequency sampling unit 331 is configured to generate a square wave signal as a switch control signal; the inverter 332 is connected to the output end of the high frequency sampling unit 331, and is configured to generate an inverse signal of the output signal of the high frequency sampling unit 331.
It should be noted that, in this embodiment, the output terminal of the high-frequency sampling unit 331 is connected to the control terminal of the first switch S1, and the output terminal of the inverter 332 is connected to the control terminal of the second switch S2. In practical applications, the connection relationship between the output signal of the switch control signal generating module 22 and the first switch S1 and the second switch S2 can be set as required, and the control signal of the first switch S1 and the control signal of the second switch S2 have opposite polarities, which is not limited to this embodiment.
As shown in fig. 3 and 4, the operation principle of the low frequency integration circuit of the present embodiment is as follows:
current sample value Vin(n) enters the subtractor 31 through a subtraction input terminal of the subtractor 31, the reference signal Vref enters the subtractor 31 through an addition input terminal of the subtractor 31, and the subtraction is performed by the subtractor 31. In this embodiment, the reference signal Vref is a mean value of the current sample value.
The switch control signal generation module 33 controls the first switch S1 to be turned on and the second switch S2 to be turned off, at which time the current integrated output value Vo(n) is sampled and converted into the last integral output value Vo(n-1) and is held on said first capacitance C1.
Last integral output value Vo(n-1) enters the adder 32 through a first addition input terminal of the adder 32, and the output signal of the subtractor 31 enters the adder 32 through a second input terminal of the adder 32, and the two are added and output.
The switch control signal generating module 33 controls the second switch S2 to be opened and the first switch S1 to be closed, at which time the output signal of the adder 32 is used as the current integrated output value V of a new roundo(n) is sampled and held on the second capacitor C2 as the output signal of the low frequency integration circuit 3.
The low frequency integration circuit 3 integrates the current sampling value according to the sampling period t set by the high frequency sampling unit 331, and the current integration output value Vo(n) satisfies the following relation:
Vo(n)＝K1*(Vref-K2*Vin(n))+Vo(n-1)，
wherein, Vo(n) is the current integrated output value, K1 is the first scaling factor, K2 is the second scaling factor, Vin(n) is the current sample value, VoAnd (n-1) is the last integration output value. The adjustment amount of each sampling period is K1 Vref-K1K 2Vin(n) by adjusting the time of samplingThe time t, the first proportionality coefficient K1 and the second proportionality coefficient K2 can adjust the gain and bandwidth of the integrating circuit, so as to obtain a proper control voltage value as a feedback compensation signal of the system.
In this embodiment, the first scaling factor K1 and the second scaling factor K2 are determined by adjusting the resistances of the input terminals of the subtracter 31 and the adder 32, and satisfy the following relations:
wherein, R1 is a resistance value of the first resistor, R2 is a resistance value of the second resistor, R3 is a resistance value of the third resistor, R4 is a resistance value of the fourth resistor, R5 is a resistance value of the fifth resistor, R6 is a resistance value of the sixth resistor, R7 is a resistance value of the seventh resistor, and R8 is a resistance value of the eighth resistor.
Example two
As shown in fig. 5, the present embodiment provides a low frequency integration circuit 3, where the difference between the low frequency integration circuit 3 and the first embodiment is that the present embodiment further includes a low frequency integration circuit connected to the current sample value VinA first follower 341 between (n) and the subtracting input terminal of the subtractor 31, a second follower 342 connected between the output terminal of the first switch S1 and the first adding input terminal of the adder 32, and a third follower 343 connected between the output terminal of the second switch S2 and the output terminal of the low frequency integrating circuit 3. The first follower 341, the second follower 342, and the third follower 343 play an isolation role, which can greatly improve the stability of the low frequency integration circuit 3.
In particular, the current sampleValue Vin(n) the input impedance can be effectively increased and the output impedance can be effectively reduced by transmitting the first follower 341 to the subtraction input end of the subtracter 31, so that the isolation of the input and output signals at the two ends of the first follower 341 is ensured.
In particular, the last integrated output value Vo(n-1) is transmitted to the first adding input end of the adder 32 through the second follower 342, which can effectively increase the input impedance, decrease the output impedance, and ensure the isolation of the input and output signals at both ends of the second follower 342.
In particular, the pre-integration output value Vo(n) is transmitted to the output end of the low-frequency integrating circuit 3 through the third follower 343, so that the input impedance can be effectively increased, the output impedance can be effectively reduced, and the isolation of input and output signals at two ends of the third follower 343 can be ensured.
In this embodiment, the first follower 341, the second follower 342, and the third follower 343 are implemented by operational amplifiers. The positive phase input end of the operational amplifier is used as the input end of the follower; the inverting input end of the operational amplifier is connected with the output end of the operational amplifier and is used as the output end of the follower. In practical application, any circuit structure capable of realizing voltage following output and having an isolation effect is suitable for the follower of this embodiment, and is not limited to this embodiment.
The working principle of the low frequency integration circuit of this embodiment is the same as that of the first embodiment, and is not described herein.
EXAMPLE III
As shown in fig. 6, the present embodiment provides a low frequency integrator circuit 3, and the difference between the low frequency integrator circuit 3 and the first embodiment is that a scaling factor is set by a first scaling factor adjusting module 35 and a second scaling factor adjusting module 36.
Specifically, the first scaling factor adjusting module 35 is connected between the output terminal of the subtractor 31 and the second adding input terminal of the adder 32, and the second scaling factor adjusting module 36 is connected to the current sample value Vin(n) to the subtracting input of said subtractor 31.
The subtracter 31 and the adder 32 have no influence on the first scaling factor K1 and the second scaling factor K2, and the first scaling factor K1 and the second scaling factor K2 are generated by the first scaling factor adjustment module 35 and the second scaling factor adjustment module 36, so as to realize the same output signal expression as in the first embodiment.
Example four
As shown in fig. 7, this embodiment provides a low frequency integration circuit 3, which is different from the second embodiment in that the low frequency integration circuit 3 further includes a third switch S3 whose output terminal is connected to the input terminal of the low frequency integration circuit 3, and a third capacitor C3 connected to the output terminal of the third switch.
Specifically, the input terminal of the third switch S3 receives the sampled value according to actual needs, and the output terminal is connected to the input terminal of the first follower 341, so as to sample the input signal of the third switch S3. The third switch S3 is used as a sampling switch, and the sampling frequency can be set according to the sampling requirement by the control signal frequency of the third switch S3, but not necessarily set here.
Specifically, the upper plate of the third capacitor C3 is connected to the output terminal of the third switch S3, and the lower plate is grounded, so as to serve as a sample-and-hold capacitor for holding the sampled input signal on the third capacitor C3. The third capacitor C3 has a capacitance of pF level and can be integrated in a chip.
As shown in fig. 8, taking a Boost structure as an example, in the prior art, the power factor correction circuit 4 includes an LED load or a main circuit, an inductor L, a freewheeling diode D, an output capacitor C, a switching tube M, a sampling resistor Rcs, a compensation module 41, a compensation capacitor Ccomp, and a comparison module 42, and a peak current of the switching tube M needs to be integrated by the compensation capacitor Ccomp to obtain a control value of a feedback loop, so as to control the switching tube M to be turned on or off. The compensation capacitor Ccomp is a capacitor with a large capacitance value and cannot be integrated into a chip, so that the port COMP needs to be externally arranged outside the chip. As shown in fig. 9, in this embodiment, the low-frequency integrating circuit 3 is applied to a power factor correction circuit 4, an input end of the low-frequency integrating circuit 3 is connected to a source end of the switching tube M, and an output end of the low-frequency integrating circuit is connected to the compensation module 41, so as to obtain an integrated value of a peak current envelope waveform of the switching tube, the low-frequency integrating circuit 3 outputs a feedback loop control signal of the power factor correction circuit, and the feedback loop control signal is a direct current value and can be used as a feedback signal that can be directly processed by a chip on which the power factor correction circuit 4 is located, so that a compensation capacitor Ccomp outside a system can be removed and the number of chip pins can be reduced, thereby reducing the cost of the system.
Specifically, the input terminal of the third switch S3 receives the switching tube peak current signal CS _ pk, and the control signal of the third switch S3 is generated by the peak sampling module 37.
It should be noted that the power factor correction circuit 6 may be any circuit capable of realizing power factor correction, and is not limited to this embodiment, which is only an example.
It should be noted that other circuits having an integral compensation capacitor for filtering out low-frequency ripples are also applicable to the present invention, and are not limited to the power factor correction circuit illustrated in this embodiment.
The operation principle of the low frequency integration circuit 3 of the present embodiment is as follows:
the switching tube peak current signal CS _ pk is input into the low-frequency integrating circuit 3, the peak sampling module 37 outputs a control signal to drive the third switch S3 to sample the switching tube peak current signal CS _ pk, the switching tube peak current signal CS _ pk is a plurality of sawtooth pulses, and an end point of each peak in the switching tube peak current signal CS _ pk is obtained through sampling, so as to obtain an envelope waveform of the switching tube peak current, and the envelope waveform is held on the third capacitor C3.
Then, the subtractor 31, the adder 32, the first switch S1, the second switch S2, the first capacitor C1, the second capacitor C2, the switch control signal generation module 33, the first follower 341, the second follower 342, and the third follower 343 perform digital integration to obtain a feedback loop control signal of the power factor correction circuit, where the feedback loop control signal is an average value of the peak current envelope of the switching tube. The integration method is the same as the first embodiment, and is not described in detail here.
The low-frequency integrating circuit and the method can realize the function of digital integration in a common analog circuit, and have high universality and low cost.
In summary, the present invention provides a low frequency integration circuit and method, including: the subtracter is used for receiving a reference signal and a current sampling value and is used for carrying out the operation of subtracting the current sampling value from the reference signal; the first switch is connected between the output end of the low-frequency integrating circuit and the upper polar plate of the first capacitor and is used for sampling an output signal of the low-frequency integrating circuit; the lower polar plate of the first capacitor is grounded; the first addition input end is connected with the first switch output end, the second addition input end is connected with the output end of the subtracter, and the adder is used for adding the last integral output value and the output signal of the subtracter; the second switch is connected between the output end of the adder and the output end of the low-frequency integrating circuit and is used for sampling the output signal of the adder; the upper polar plate of the second capacitor is connected with the output end of the second switch, and the lower polar plate is grounded; wherein the polarity of the control signals of the first switch and the second switch is opposite. And feeding back the last integral output value to a first addition input end of the adder, inputting a value obtained by subtracting the current sampling value from the reference signal to a second addition input end of the adder, and outputting the current integral output value after addition operation is carried out through the adder. The low-frequency integrating circuit and the method can realize the low-frequency filtering function without an external capacitor, a digital circuit and a singlechip, are convenient to integrate and have low cost; the filtering value of the peak current envelope waveform of the switching tube can be obtained by matching with a peak sampling technology, so that integral compensation capacitors such as a power factor correction circuit and the like which need to filter low-frequency ripples are saved, the number of pins is reduced, and the cost is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A low frequency integration circuit, characterized in that the low frequency integration circuit comprises at least:
the circuit comprises a subtracter, an adder, a first switch, a second switch, a first capacitor and a second capacitor;
the adder input end of the subtracter receives a reference signal, and the subtractor input end of the subtracter receives a current sampling value and is used for carrying out the operation of subtracting the current sampling value from the reference signal;
the input end of the first switch is connected with the output end of the low-frequency integrating circuit, and the output end of the first switch is connected with the upper polar plate of the first capacitor and used for sampling the output signal of the low-frequency integrating circuit; the lower polar plate of the first capacitor is grounded;
a first adding input end of the adder is connected with a last integral output value output by the first switch, and a second adding input end of the adder is connected with an output end of the subtracter and is used for adding the last integral output value and an output signal of the subtracter;
the input end of the second switch is connected with the output end of the adder, and the output end of the second switch is used as the output end of the low-frequency integrating circuit and is used for sampling the output signal of the adder;
the upper polar plate of the second capacitor is connected with the output end of the second switch, and the lower polar plate is grounded;
wherein the polarity of the control signals of the first switch and the second switch is opposite.
2. The low frequency integration circuit of claim 1, wherein: the subtracter comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier;
one end of the first resistor is used as a subtraction input end of the subtracter, and the other end of the first resistor is connected with an inverting input end of the first operational amplifier;
one end of the second resistor is connected with the inverting input end of the first operational amplifier, and the other end of the second resistor is connected with the output end of the first operational amplifier;
one end of the third resistor is used as an addition input end of the subtracter, and the other end of the third resistor is connected with a positive phase input end of the first operational amplifier;
one end of the fourth resistor is connected with the positive phase input end of the first operational amplifier, and the other end of the fourth resistor is grounded.
3. The low frequency integration circuit of claim 1, wherein: the adder comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second operational amplifier;
one end of the fifth resistor is used as a first addition input end of the adder, and the other end of the fifth resistor is connected with a non-inverting input end of the second operational amplifier;
one end of the sixth resistor is used as a second addition input end of the adder, and the other end of the sixth resistor is connected with a non-inverting input end of the second operational amplifier;
one end of the seventh resistor is connected with the inverting input end of the second operational amplifier, and the other end of the seventh resistor is grounded;
one end of the eighth resistor is connected with the inverting input end of the second operational amplifier, and the other end of the eighth resistor is connected with the output end of the second operational amplifier.
4. The low frequency integration circuit of claim 1, wherein: the low-frequency integration circuit further comprises a first follower connected between the current sampling value and the subtraction input end of the subtracter, a second follower connected between the output end of the first switch and the first addition input end of the adder, and a third follower connected between the output end of the second switch and the output end of the low-frequency integration circuit, wherein each follower is used for isolating signals.
5. The low frequency integration circuit of claim 1, wherein: the low-frequency integrating circuit also comprises a switch control signal generating module; the switch control signal generating module comprises a high-frequency sampling unit and an inverter; the high-frequency sampling unit is used for generating square wave signals; the phase inverter is connected to the output end of the high-frequency sampling unit and used for generating an inverse signal of the output signal of the high-frequency sampling unit.
6. The low frequency integration circuit of claim 1, wherein: the capacitance value of the first capacitor and the capacitance value of the second capacitor are pF level.
7. The low frequency integration circuit of claim 1, wherein: the low-frequency integrating circuit further comprises a first proportional coefficient adjusting module and a second proportional coefficient adjusting module, wherein the first proportional coefficient adjusting module is connected between the output end of the subtracter and the second adding input end of the adder, and the second proportional coefficient adjusting module is connected between the current sampling value and the subtracting input end of the subtracter.
8. The low frequency integration circuit according to any one of claims 1 to 7, wherein: the low-frequency integration circuit further comprises a third switch and a third capacitor, wherein the output end of the third switch is connected to the input end of the low-frequency integration circuit, and the third capacitor is connected to the output end of the third switch.
9. The low frequency integration circuit of claim 8, wherein: the low-frequency integrating circuit further comprises a peak value sampling module, wherein the output end of the peak value sampling module is connected with the control end of the third switch and is used for controlling the third switch to sample; and the capacitance value of the third capacitor is in a pF level.
10. A low frequency integration method of a low frequency integration circuit according to any one of claims 1 to 9, wherein the low frequency integration method at least comprises:
and feeding back the last integral output value to a first addition input end of the adder, inputting a value obtained by subtracting the current sampling value from the reference signal to a second addition input end of the adder, and outputting the current integral output value after addition operation is carried out through the adder.
11. A low frequency integration method as claimed in claim 10, wherein: the current integral output value satisfies the following relation:
Vo(n)＝K1*(Vref-K2*Vin(n))+Vo(n-1)，
wherein, Vo(n) is the current integrated output value, K1 is the first scaling factor, Vref is the reference signal, K2 is the second scaling factor, Vin(n) is the current sample value, VoAnd (n-1) is the last integration output value.
12. A low frequency integration method as claimed in claim 11, wherein: determining the first scaling factor and the second scaling factor by adjusting the resistances of the input ends of the subtracter and the adder; or the first scaling factor and the second scaling factor are determined by a first scaling factor adjusting module arranged between the output end of the subtracter and the second adding input end of the adder and a second scaling factor adjusting module arranged between the current sampling value and the subtracting input end of the subtracter.
13. A low frequency integration method as claimed in claim 10, wherein: the low frequency integration method further comprises: receiving the peak current of a switching tube in a power factor correction circuit, sampling the peak current of the switching tube based on peak sampling to obtain an envelope waveform of the peak current of the switching tube, and obtaining a direct current feedback loop control signal through integration to further remove a compensation capacitor in the power factor correction circuit.
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