CN102231100A - Analog adder and current-type boosting transformer - Google Patents

Abstract

The application discloses an analog adder and a current-type boosting transformer. The analog adder comprises an operational transconductance amplifier, an offset current source, a compensation oblique wave current source, a first output resistor and a second output resistor, wherein the offset current source is connected with the grid electrode of an MOS (metal oxide semiconductor) transistor at the output stage of the operational transconductance amplifier; the current of the offset current source is reflected on a fifth MOS transistor at the output stage of the operational transconductance amplifier; when the sensing voltage VSN is 0, the MOS transistor at the output stage is ensured to operate in a saturated region, so that all the MOS transistors in the analog adder operate in the saturated region; and when the input sensing voltage VSN is about 0, output signals of the analog adder change along with the change of the input sensing voltage, so that the response speed of the analog adder is improved, thus the analog adder provided by the invention is applicable to current-type boosting transformers with frequently switched current load and current-type boosting transformers which operate in a CCM (continuous conduction mode), a critical operating mode or a DCM (discontinuous conduction mode).

Description

A kind of analog adder and current mode step-up transformer

Technical field

The application relates to the analog adder technical field, particularly relates to a kind of analog adder and current mode step-up transformer.

Background technology

Be applied to the analog adder in the current mode step-up transformer, be used for offset voltage, compensation ramp voltage, sensing voltage are added up, see also Fig. 1, show the circuit theory diagrams of traditional analog adder, as shown in the figure, P manages 107-110, N manages 112-114, and bias current sources 104, resistance 115 and 116 operational transconductance amplifier that constitute, an end of resistance 115 is as the inverting input of operational transconductance amplifier, and this reverse inter-input-ing ending grounding; One end of resistance 116 is as the in-phase input end of this operational transconductance amplifier, and this in-phase input end input sensing voltage VSN, electric current on the P pipe 110 is the output current of operational transconductance amplifier, and electric current is the electric current of the output of operational transconductance amplifier on the P pipe 111, and this electric current is VSN/R115; P pipe 111 and N pipe 114 are the backfeed loop of this operational transconductance amplifier, the output current of this operational transconductance amplifier are fed back to the inverting input of operational transconductance amplifier through resistance R 115;

Current source 105 is minimum offset current, and offset voltage is I105 * R118; Current source I106 is compensation oblique wave electric current, and the compensation ramp voltage is that I106 * (R117+R118), the voltage VADD of this analog adder output is specially:

VADD=(VSN/R115) * R118+I105 * R118+I106 * (R117+R118) (formula 1)

The time of supposing one-period is T, and dutycycle is D, in the time of 0≤t≤DT, and sensing voltage VSN (t)={ I _{L, min}* R _SN+ (VIN/L) * R _SN* t} * u (t), wherein, I _{L, min}Refer to the minimum value of peak inductive current.

When the current mode step-up transformer is operated in CCM (Continuous Conduction Mode, continuously conducting state) mode of operation following time, I _{L, min}It is value greater than 0; When the current mode step-up transformer is operated in DCM (Discontinuous Conduction Mode, discontinuous conducting state) mode of operation following time, I _{L, min}Equal 0; When the current mode step-up transformer was operated in critical mode of operation or DCM mode of operation, sensing voltage VSN can be reduced to: VSN (t)=(VIN/L) * RSN*t*u (t), and 0≤t≤DT, when t=0, VSN (0)=0.

For analog adder shown in Figure 1, P manages 108 and 109 symmetries, and N manages 112 and 113 symmetries, resistance R 115 and 116 equates that when the sensing voltage VSN of input was 0, the electric current that flows through on the N pipe 114 was 0, be that N pipe 114 is in cut-off region, when VSN increased, N managed 114 and carries out the transition to sub-threshold region from cut-off region, Zhongdao saturation region, owing to managing 114 from when the district carries out the transition to sub-threshold region as N, the electric current that flows through on 114 is very little, and mutual conductance is also very little, be one near or be slightly larger than 0 value, its open-loop gain A _{DC, open}≈ 0 bandwidth ≈ 0, promptly when the sensing voltage VSN that imports is very little, the output current of this analog adder can not be followed input signal well and be changed, in other words, the response speed of traditional analog adder is slow, matching is poor, can not be advantageously applied in the current mode step-up transformer of the frequent switch of current loading, can not be advantageously applied in the current mode step-up transformer that is operated under CCM, critical mode of operation or three kinds of mode of operations of DCM.

Summary of the invention

For solving the problems of the technologies described above, the embodiment of the present application provides a kind of analog adder and current mode step-up transformer, under the prerequisite that is implemented in the matching properties that does not change analog adder, improves response speed, and technical scheme is as follows:

A kind of analog adder comprises: operational transconductance amplifier, offset current source, compensation oblique wave current source, first output resistance and second output resistance, wherein:

The reverse inter-input-ing ending grounding of operational transconductance amplifier, in-phase input end are the input end of this analog adder, and output terminal is connected to the hot end of described second output resistance, the other end ground connection of described second output resistance through first metal-oxide-semiconductor;

The grid of the 5th metal-oxide-semiconductor in the output stage of offset current source and described operational transconductance amplifier links to each other;

Compensation oblique wave current source links to each other with the described second output resistance hot end by first output resistance, and the hot end of described first output resistance is the output terminal of this analog adder.

Preferably, described operational transconductance amplifier comprises: the first cascade bias unit, the input stage that is connected with described output stage, and backfeed loop, wherein:

The described first cascade bias unit links to each other with the metal-oxide-semiconductor of described input stage, is used to the metal-oxide-semiconductor of described input stage that bias current is provided;

Described input stage comprises: second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, be connected the feedback resistance of the described second metal-oxide-semiconductor source electrode, and second input resistance that is connected described the 3rd metal-oxide-semiconductor source electrode, the mirror current source of formation;

Described output stage also comprises: the 4th metal-oxide-semiconductor that is connected in series with described the 5th metal-oxide-semiconductor, wherein, the drain electrode of described the 5th metal-oxide-semiconductor connects the 4th metal-oxide-semiconductor, and the grid of described the 5th metal-oxide-semiconductor links to each other with the drain electrode of described the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor connects described offset current source;

Described backfeed loop comprises: described first metal-oxide-semiconductor and the 5th metal-oxide-semiconductor, and the grid of described first metal-oxide-semiconductor connects the drain electrode of described the 5th metal-oxide-semiconductor, and the source electrode of described the 5th metal-oxide-semiconductor is connected to the hot end of described feedback resistance.

Preferably, the described first cascade bias unit comprises: bias current sources, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, wherein:

The source electrode of described the 6th metal-oxide-semiconductor connects dc positive power, and drain electrode connects the negative output terminal of described bias current sources, the positive output end ground connection of described bias current sources;

The grid of described the 7th metal-oxide-semiconductor connects the grid of described the 6th metal-oxide-semiconductor, and the source electrode of described the 7th metal-oxide-semiconductor connects described dc positive power, and the drain electrode of described the 7th metal-oxide-semiconductor connects the drain electrode of described second metal-oxide-semiconductor;

The grid of described the 8th metal-oxide-semiconductor connects the grid of described the 6th metal-oxide-semiconductor, and the source electrode of described the 8th metal-oxide-semiconductor connects described dc positive power, and the drain electrode of described the 8th metal-oxide-semiconductor connects the drain electrode of described the 3rd metal-oxide-semiconductor.

Preferably, the source electrode of the 4th metal-oxide-semiconductor in the described output stage connects dc positive power, the grid of described the 4th metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, the drain electrode of the 4th metal-oxide-semiconductor connects the drain electrode of described the 5th metal-oxide-semiconductor, the source electrode of described the 5th metal-oxide-semiconductor connects the hot end of described feedback resistance, the grid of described the 5th metal-oxide-semiconductor connects the drain electrode of described the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor links to each other with described offset current source.

Preferably, the grid of described first metal-oxide-semiconductor connects the grid of described the 4th metal-oxide-semiconductor, and the source electrode of described first metal-oxide-semiconductor connects dc positive power, and the drain electrode of described first metal-oxide-semiconductor connects the hot end of described second output resistance.

Preferably, above-mentioned analog adder also comprises:

Be connected the second cascade bias unit between described first cascade bias unit and the described input stage, wherein:

The described second cascade bias unit comprises: the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor, and second bias current sources, wherein:

The grid of described the 9th metal-oxide-semiconductor is connected with drain electrode, and should drain electrode connect described second bias supply;

Described the tenth metal-oxide-semiconductor is serially connected between described the 7th metal-oxide-semiconductor and second metal-oxide-semiconductor, and the grid of described the tenth metal-oxide-semiconductor is connected with the grid of described the 9th metal-oxide-semiconductor;

Described the 11 metal-oxide-semiconductor is connected in series between described the 8th metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, and the grid of described the 11 metal-oxide-semiconductor is connected with the grid of described the 9th metal-oxide-semiconductor.

Preferably, described second metal-oxide-semiconductor, described the 3rd metal-oxide-semiconductor and described the 5th metal-oxide-semiconductor are the NMOS pipe;

Preferably, described first metal-oxide-semiconductor, described the 4th metal-oxide-semiconductor, described the 6th metal-oxide-semiconductor, described the 7th metal-oxide-semiconductor, described the 8th metal-oxide-semiconductor, described the 9th metal-oxide-semiconductor, described the tenth metal-oxide-semiconductor and described the 11 metal-oxide-semiconductor are the PMOS pipe.

When the embodiment of the present application also provides a kind of current mode step-up transformer to be operated in the critical mode of operation of CCM or three kinds of mode of operations of DCM, reduce the aberration optimizing performance, technical scheme is as follows:

A kind of current mode step-up transformer, comprise: error amplifier, pulse width modulation (PWM) comparer, pwm control circuit and switching tube, it is characterized in that, also comprise: each described analog adder of claim 1-6, the sensing voltage input end of this analog adder is connected to the source electrode of described switching tube, and the output terminal of this analog adder is connected to the in-phase input end of described PWM comparer.

The technical scheme that is provided by above the embodiment of the present application as seen, this analog adder is connected the offset current source between the input stage and output stage of operational transconductance amplifier, because the characteristic of two metal-oxide-semiconductors in input stage coupling, the electric current that flows through this two pipe is identical, again because described offset current source and course is crossed a metal-oxide-semiconductor of described two metal-oxide-semiconductors, electric current on the metal-oxide-semiconductor of output stage flows through the another metal-oxide-semiconductor as feedback current, and the bias current of two metal-oxide-semiconductors of input stage equates, then electric current equates on the 5th metal-oxide-semiconductor in the electric current in offset current source and the output stage, be that current signal on the offset current source is reflected on the 5th metal-oxide-semiconductor of described output stage, therefore, when sensing voltage VSN is input as 0, the electric current that flows through output stage is the electric current of the output in offset current source, thereby can make the metal-oxide-semiconductor of output stage be operated in the saturation region, and then make the metal-oxide-semiconductor in the analog adder all be operated in the saturation region, when the sensing voltage VSN that imports is near 0, make the output signal of this analog adder can be good at following the sensing voltage variation of input and changing, promptly improved the response speed of this analog adder, be particularly useful in the current mode step-up transformer of the frequent switch of current loading, and might be operated in CCM, in the current mode step-up transformer under three kinds of patterns of critical mode of operation or DCM.

Description of drawings

In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, the accompanying drawing that describes below only is some embodiment that put down in writing among the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is the circuit theory synoptic diagram of traditional analog adder;

Fig. 2 is the schematic block circuit diagram of a kind of analog adder of the embodiment of the present application;

Fig. 3 is the electrical block diagram of a kind of analog adder of the embodiment of the present application;

Fig. 4 is the input and output waveform synoptic diagram of the embodiment of the present application analog adder;

Fig. 5 is the circuit theory diagrams of a kind of current mode step-up transformer of the embodiment of the present application.

Embodiment

In order to make those skilled in the art person understand technical scheme among the application better, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all should belong to the scope of the application's protection.

See also Fig. 2, show the circuit theory synoptic diagram of a kind of analog adder of the embodiment of the present application, this analog adder mainly comprises: operational transconductance amplifier 100, offset current source 121, compensation oblique wave current source 122, the first metal-oxide-semiconductor M1, the first output resistance R1, the second output resistance R2, wherein:

Operational transconductance amplifier 100 comprises input stage and output stage, concrete, the in-phase input end of input stage is as the input end of this analog adder, input has described sensing voltage VSN, reverse inter-input-ing ending grounding, wherein, the effect of resistance R 103 and resistance R 104 is current limlitings, prevents that the electric current of input of operational transconductance amplifier 100 is excessive.

Metal-oxide-semiconductor 105 and metal-oxide-semiconductor 106 are the output stage of this operational transconductance amplifier 100, and the grid of metal-oxide-semiconductor 106 is connected to the grid of the first metal-oxide-semiconductor M1, and the output current of this operational transconductance amplifier 100 is passed to the first metal-oxide-semiconductor M1 through metal-oxide-semiconductor 105 and metal-oxide-semiconductor 106.The source electrode of metal-oxide-semiconductor 106 is connected to the inverting input of this operational transconductance amplifier simultaneously, forms backfeed loop, thereby guarantees operational transconductance amplifier 100 operate as normal.

The drain electrode of the first metal-oxide-semiconductor M1 is by the second output resistance R2 ground connection, and the source electrode of the first metal-oxide-semiconductor M1 connects dc positive power VDD.Compensation oblique wave current source 122 is connected to the hot end of the described second output resistance R2 by the first output resistance R1, and the hot end of the first output resistance R1 is the output terminal of this analog adder.

Between the input stage and output stage of offset current source 121 and operational transconductance amplifier, concrete, be connected the grid of the metal-oxide-semiconductor 106 of described output stage, at this moment, the electric current that flows through on the metal-oxide-semiconductor of the output stage of operational transconductance amplifier 100 equals the electric current on the offset current source.

The analog adder that present embodiment provides, the offset current source is connected between the input stage and output stage of operational transconductance amplifier, because the characteristic of two metal-oxide-semiconductors in input stage coupling, the electric current that flows through this two metal-oxide-semiconductor is identical, again because described offset current source and course is crossed a metal-oxide-semiconductor of described two metal-oxide-semiconductors, electric current on the metal-oxide-semiconductor of output stage flows through the another metal-oxide-semiconductor as feedback current, and the bias current of two metal-oxide-semiconductors of input stage equates, then electric current equates on the metal-oxide-semiconductor of the electric current in offset current source and output stage, be that current signal on the offset current source is reflected on the metal-oxide-semiconductor of described output stage, therefore, when sensing voltage VSN is input as 0, the electric current that flows through output stage is the electric current of the output in offset current source, thereby, can make the metal-oxide-semiconductor of output stage be operated in the saturation region, and then make the metal-oxide-semiconductor in the analog adder all be operated in the saturation region, when the sensing voltage VSN that imports is near 0, make the output signal of this analog adder can be good at following the sensing voltage variation of input and changing, promptly improved the response speed of this analog adder, be particularly useful in the current mode step-up transformer of the frequent switch of current loading, and might be operated in CCM, in the current mode step-up transformer under three kinds of patterns of critical mode of operation or DCM.

See also Fig. 3, show the physical circuit synoptic diagram of the analog adder that the embodiment of the present application provides, it is a kind of concrete embodiment of the corresponding embodiment of Fig. 2, this analog adder comprises: operational transconductance amplifier 100, offset current source 121, compensation oblique wave current source 122, the first output resistance R1 and the second output resistance R2, the first metal-oxide-semiconductor M1, wherein, described compensation oblique wave current source 122 is to rise since 0 with certain slope, control signal up to pwm control circuit output is a low level, switching tube M1 ends, the electric current descending slope on described certain slope and the inductance L, and the cycles of OSC clock signal etc. are relevant; Then, compensation oblique wave current source 122 reduces to 0.

The effect of operational transconductance amplifier 100 is that the voltage signal that in-phase input end is imported is sensing voltage VSN, be converted to current signal output, described operational transconductance amplifier 100 comprises: input stage, output stage, backfeed loop and the first cascade bias unit 110.

The voltage that the electric current of operational transconductance amplifier output and described offset current source 121 and compensation oblique wave current source 122 produce on the second output resistance R2 superposes, thereby obtains the output signal of this analog adder.

The described first cascade bias unit 110 comprises first bias current sources, 111, the six metal-oxide-semiconductors 112, the 7th metal-oxide-semiconductor 113 and the 8th metal-oxide-semiconductor 114, wherein:

Described first bias current sources 111 provides bias current by the 7th metal-oxide-semiconductor 113 for second metal-oxide-semiconductor 101, simultaneously, first bias current sources 111 provides bias current by the 8th metal-oxide-semiconductor 114 for the 3rd metal-oxide-semiconductor 102, thereby guarantees the saturation region that is operated in of second metal-oxide-semiconductor 101 and the 3rd metal-oxide-semiconductor 102.

Concrete, first bias current sources, 111 1 end ground connection, the other end is connected to the drain electrode of described the 6th metal-oxide-semiconductor 112, simultaneously, the drain electrode of the 6th metal-oxide-semiconductor 112 is connected to the grid of the 6th metal-oxide-semiconductor 112, the grid of the 6th metal-oxide-semiconductor 112 is connected to the grid of described the 7th metal-oxide-semiconductor 113, and the drain electrode of the 7th metal-oxide-semiconductor 113 connects the drain electrode of described second metal-oxide-semiconductor 101, and the source electrode of the 7th metal-oxide-semiconductor 113 connects dc positive power VDD; The grid of the 8th metal-oxide-semiconductor 114 connects the grid of the 6th metal-oxide-semiconductor 112, and the source electrode of the 8th metal-oxide-semiconductor 114 connects dc positive power VDD, and the drain electrode of the 8th metal-oxide-semiconductor 114 connects the drain electrode of described the 3rd metal-oxide-semiconductor 102.

Described input stage comprises: second metal-oxide-semiconductor 101, the 3rd metal-oxide-semiconductor 102, feedback resistance R103, the second input resistance R104.

Concrete, the drain electrode of second metal-oxide-semiconductor 101 links to each other with grid, and simultaneously, the drain electrode of second metal-oxide-semiconductor 101 links to each other with the drain electrode of the 7th metal-oxide-semiconductor 113, and the source electrode of second metal-oxide-semiconductor 101 is as the inverting input of this operational transconductance amplifier, by feedback resistance R103 ground connection;

The drain electrode of the 3rd metal-oxide-semiconductor 102 links to each other with grid, the drain electrode of the 3rd metal-oxide-semiconductor 102 simultaneously links to each other with the drain electrode of the 8th metal-oxide-semiconductor 114, the source electrode of the 3rd metal-oxide-semiconductor 102 has described sensing voltage VSN as the in-phase input end of this operational transconductance amplifier by second input resistance R104 input.

Described output stage comprises: the 4th metal-oxide-semiconductor 105 that is connected in series and the 5th metal-oxide-semiconductor 106, concrete, the grid of the 4th metal-oxide-semiconductor 105 connects the drain electrode of the 4th metal-oxide-semiconductor 105, the source electrode of the 4th metal-oxide-semiconductor 105 connects dc positive power VDD, the drain electrode of the 4th metal-oxide-semiconductor 105 connects the drain electrode of described the 5th metal-oxide-semiconductor 106, the source electrode of described the 5th metal-oxide-semiconductor 106 connects the common port of described second metal-oxide-semiconductor 101 and feedback resistance R103, the grid of the 5th metal-oxide-semiconductor 106 connects the drain electrode of described the 3rd metal-oxide-semiconductor 102, described offset current source 121 is connected to the grid of the 5th metal-oxide-semiconductor 106 simultaneously, the electric current that flows through on the 4th metal-oxide-semiconductor 105 and the 5th metal-oxide-semiconductor 106 equates, and be the output current of this operational transconductance amplifier, electric current on the 4th metal-oxide-semiconductor 105 feeds back to the inverting input of this operational transconductance amplifier by resistance R 103, forms a closed-loop system.

When sensing voltage VSN was 0, the electric current that flows through the 5th metal-oxide-semiconductor 106 was the electric current in offset current source 121; When sensing voltage VSN is during greater than 0 voltage signal, the electric current that the operational transconductance amplifier output current promptly flows through on the 5th metal-oxide-semiconductor 106 is I _{D, 106}=I ₁₂₁+ VSN/R ₁₀₄

At sensing voltage VSN is 0 o'clock, and first bias current sources 111 rationally is set, and the 5th metal-oxide-semiconductor 106 is chosen suitable breadth length ratio, can guarantee that so all metal-oxide-semiconductors in the operational transconductance amplifier all are operated in the saturation region.

The output terminal of operational transconductance amplifier is connected to the grid of the first metal-oxide-semiconductor M1, the source electrode of this first metal-oxide-semiconductor M1 connects dc positive power VDD, drain electrode connects the hot end of the second output resistance R2, the other end ground connection of the second output resistance R2, compensation oblique wave current source 122 is connected to the hot end of the second output resistance R2 by the first output resistance R1, and then compensating ramp voltage is 122 * (R1+R2).

The hot end of the first output resistance R1 i.e. the output terminal VADD of this analog adder, suppose that the 4th MOS105 pipe and the breadth length ratio of the first metal-oxide-semiconductor M1 are 1: 1, in the current mode step-up transformer of the frequent switch of current loading, compensation oblique wave current source 122 increases progressively since 0, so hypothesis compensation oblique wave current source 122 is 0, then the voltage of this analog adder output is:

VADD＝(VSN/R ₁₀₄+I ₁₂₁)×R2+I ₁₂₂×(R1+R2)＝(VSN/R ₁₀₄+I ₁₂₁)×R2。

See also the input and output waveform synoptic diagram of present embodiment corresponding simulating totalizer shown in Figure 4, the VSN among the figure is the waveform of input signal VSN correspondence, and VADD is the waveform of output signal VADD correspondence.

When the current mode step-up transformer is operated in critical mode of operation, compensation oblique wave current source 122 is 0, and offset current source 121 equates that with first bias current sources 111 resistance of feedback resistance R103, the second input resistance R104 and the second output resistance R2 is all equal, i.e. R103=R104=R2.The input signal VSN of analog adder rises to 50mV from 0mV in 500ns, at t=0 constantly, and VADD=I ₁₂₁* R ₂, hence one can see that, and the output signal VADD of analog adder can be good at following input signal VSN to be changed.And, sensing voltage VSN initial value in input is in 0 the step response, the response speed of the analog adder that present embodiment provides is obviously faster than the step response speed of existing analog adder, because, at the sensing voltage VSN initial value annex of input, the bandwidth that the analog machine that present embodiment provides is initiated is far longer than the bandwidth of analog adder in the prior art.

Need to prove that described first metal-oxide-semiconductor in the foregoing description, described the 4th metal-oxide-semiconductor, described the 6th metal-oxide-semiconductor, described the 7th metal-oxide-semiconductor and described the 8th metal-oxide-semiconductor are the PMOS pipe.

In summary, the analog adder that present embodiment provides, by the offset current source being connected the inside of operational transconductance amplifier, all metal-oxide-semiconductors all are operated in the saturation region in the operational transconductance amplifier thereby can make, thereby the response speed that has improved this analog adder is fast, make this analog adder can be applicable in the current mode step-up transformer of the frequent switch of current loading, and might be operated in the current mode step-up transformer under CCM, critical mode of operation or three kinds of patterns of DCM.

Preferably, referring to Fig. 3, the analog adder that the embodiment of the present application provides also comprises: the second cascade bias unit 130, effect is the output impedance that improves the mirror current source of mainly being made up of second metal-oxide-semiconductor 101 and the 3rd metal-oxide-semiconductor 102 in the operational transconductance amplifier, so that the performance of this analog adder of following adopted formula computational analysis.

This unit mainly comprises: the 9th metal-oxide-semiconductor 131, the tenth metal-oxide-semiconductor the 132, the 11 metal-oxide-semiconductor 133, and second bias current sources 134, wherein:

The grid of described the 9th metal-oxide-semiconductor 131 is connected with drain electrode, and should drain electrode connect described second bias supply 134, and source electrode connects dc positive power VDD.

Described the tenth metal-oxide-semiconductor 132 is serially connected between described the 7th metal-oxide-semiconductor 113 and second metal-oxide-semiconductor 101, the source electrode of the tenth metal-oxide-semiconductor 132 connects the drain electrode of described the 7th metal-oxide-semiconductor 113, the drain electrode of the tenth metal-oxide-semiconductor 132 connects the drain electrode of described second metal-oxide-semiconductor 101, and the grid of the tenth metal-oxide-semiconductor 132 is connected with the grid of described the 9th metal-oxide-semiconductor 131;

Between described the 11 metal-oxide-semiconductor 133 described the 8th metal-oxide-semiconductors of serial connection and the 3rd metal-oxide-semiconductor, the source electrode of the 11 metal-oxide-semiconductor 133 connects the drain electrode of described the 8th metal-oxide-semiconductor 114, the drain electrode of the 11 metal-oxide-semiconductor 133 connects the drain electrode of described the 3rd metal-oxide-semiconductor 102, and the grid of the 11 metal-oxide-semiconductor 133 is connected with the grid of described the 9th metal-oxide-semiconductor 131.

The summation of the stray capacitance that electric capacity 135 expression a are ordered, its value is C _Par

The output of operational transconductance amplifier 100 is the current signals on the 4th metal-oxide-semiconductor 105, and the inverting input by feedback resistance R103 feeds back to operational transconductance amplifier 100 forms a voltage input, the closed-loop system of electric current output.

Convenient for computing, the input signal of described closed-loop system is regarded as output current flows through the magnitude of voltage on the feedback resistance R103, be exactly a voltage input like this, the system of voltage output.For the system of voltage input voltage output, the dominant pole invariant position, open-loop gain equals the open loop output mutual conductance of operational transconductance amplifier 100 and the product of feedback resistance R103.

The output impedance of supposing the described first cascade bias unit and the second cascade unit is far longer than the impedance of seeing into from the drain terminal of the 3rd metal-oxide-semiconductor 102 pipes, the i.e. impedance of seeing into from a point, and described output impedance is in parallel with the described impedance of seeing into from a point, then can ignore the influence of described output impedance during from output impedance that an a sees in computational analysis.

The open-loop gain of this operational transconductance amplifier is:

$A_{\mathrm{DC},\mathrm{open}}=[({\mathrm{<figure-callout\; id="102"\; label="gm"\; filenames="HDA0000072898670000031.png"\; state="\{\{state\}\}">gm</figure-callout>}}_{102}+{\mathrm{gmb}}_{102})\&times;r_{o,102}+1]\&times;\frac{{\mathrm{<figure-callout\; id="106"\; label="gm"\; filenames="HDA0000072898670000012.png"\; state="\{\{state\}\}">gm</figure-callout>}}_{106}\&times;{\mathrm{<figure-callout\; id="102"\; label="R"\; filenames="HDA0000072898670000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{102}}{1+({\mathrm{<figure-callout\; id="106"\; label="gm"\; filenames="HDA0000072898670000012.png"\; state="\{\{state\}\}">gm</figure-callout>}}_{106}+{\mathrm{gmb}}_{106})\&times;R_{102}}$ (formula 2)

In the formula 2, gm ₁₀₂Be the mutual conductance of the 3rd metal-oxide-semiconductor 102, gm ₁₀₆Be the mutual conductance of the 5th metal-oxide-semiconductor 106, gmb ₁₀₂Be the back of the body grid mutual conductance of the 3rd metal-oxide-semiconductor 102, ro, 102 is the output impedance of metal-oxide-semiconductor 102

Dominant pole is ${\mathrm{\&omega;}}_{p1}=\frac{1}{2\&times;\mathrm{\&pi;}\&times;C_{\mathrm{par}}\&times;[r_{o,102}+({\mathrm{<figure-callout\; id="102"\; label="gm"\; filenames="HDA0000072898670000031.png"\; state="\{\{state\}\}">gm</figure-callout>}}_{102}+{\mathrm{gmb}}_{102})\&times;r_{o,102}\&times;R_{102}}$ (formula 3)

All the other nodes all can be regarded the low-resistance limit as, so this operational transconductance amplifier is a first order pole operational amplifier.The pull-type conversion of its open loop can be write as

$A_{\mathrm{open}}\left(s\right)=\frac{A_{\mathrm{DC},\mathrm{open}}}{1+\frac{S}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_{p1}}}$ (formula 4)

The output current of operational transconductance amplifier feeds back to the inverting input of this operational transconductance amplifier by the 5th metal-oxide-semiconductor 106 and feedback resistance R103, and this reverse inter-input-ing ending grounding forms closed-loop system, and the pull-type of the closed loop gain of closed-loop system is transformed to:

$A_{\mathrm{close}}\left(s\right)\&ap;\frac{1}{1+\frac{S}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_{P1}\&times;A_{\mathrm{DC},\mathrm{open}}}}$ (formula 5)

Closed-loop bandwidth can be expressed as:

ω _u=ω _P1* A _{DC, open}(formula 6)

Then the pull-type conversion of closed loop gain can be write as:

$A_{\mathrm{close}}\left(s\right)\&ap;\frac{1}{1+\frac{S}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_u}}$ (formula 7)

So, when input signal be $\mathrm{VSN}\left(S\right)=\frac{I_{L,\min }\&times;R_{\mathrm{SN}}}{S}+\frac{\mathrm{VIN}\&times;R_{\mathrm{SN}}}{L\&times;S^2}$ The time,

The response of this closed-loop system is:

$A_{\mathrm{close}}\left(s\right)\&times;V_{\mathrm{SN}}\left(S\right)=\frac{1}{1+\frac{s}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_u}}\&times;(\frac{I_{L,\min }\&times;R_{\mathrm{SN}}}{S}+\frac{\mathrm{VIN}\&times;R_{\mathrm{SN}}}{L\&times;S^2})$ (formula 8)

The result of corresponding anti-pull-type conversion, just the result of the time domain response of this closed-loop system is:

$V_{\mathrm{OUT}}\left(t\right)=I_{121}\&times;{\mathrm{<figure-callout\; id="103"\; label="R"\; filenames="HDA0000072898670000031.png"\; state="\{\{state\}\}">R</figure-callout>}}_{103}+I_{L,\min }\&times;R_{\mathrm{SN}}\&times;(1-\exp (-2\&CenterDot;\mathrm{\&pi;}\&CenterDot;{\mathrm{\&omega;}}_u\&CenterDot;t)\&times;u\left(t\right)$

(formula 9)

$+\frac{\mathrm{VIN}\&times;R_{\mathrm{SN}}}{L}\&times;\{t+\frac{1}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_u}[-1+\exp (-2\&CenterDot;\mathrm{\&pi;}\&CenterDot;{\mathrm{\&omega;}}_u\&CenterDot;t)\left]\right\}\&times;u\left(t\right)$

Error term V _ERROR(t) promptly:

V _OUT(t)-V _SN(t)-I ₁₂₁* R ₁₀₃(formula 10)

Also promptly:

$V_{\mathrm{ERROR}}\left(t\right)=u\left(t\right)\&times;$

$\{-I_{L,\min }\&times;R_{\mathrm{SN}}\&times;\exp (-2\&CenterDot;\mathrm{\&pi;}\&CenterDot;{\mathrm{\&omega;}}_u\&CenterDot;t)+\frac{\mathrm{VIN}\&times;R_{\mathrm{SN}}}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_u\&times;L}\&times;[-1+\exp (-2\&CenterDot;\mathrm{\&pi;}\&CenterDot;{\mathrm{\&omega;}}_u\&CenterDot;t)\left]\right\}$

(formula 11)

First error in the error shown in the formula 11 is:

V _ERROR1(t)=-I _{L, min}* R _SN* exp (2 π ω _uT) (formula 12)

First error V _ERROR1(t) extreme value occurs in t=0 constantly, when step response takes place in input signal VSN, and V _ERROR1(0)=-I _{L, minn}* R _SN, V _ERROR1(t) along with the increase of time t, be index decreased, improve bandwidth omega _u, can effectively reduce V _ERROR1

In the error term shown in the formula 11, second error is:

$V_{\mathrm{ERROR}2}\left(t\right)=\frac{\mathrm{VIN}\&times;R_{\mathrm{SN}}}{2\&times;\mathrm{\&pi;}\&times;{\mathrm{\&omega;}}_u\&times;L}\&times;[-1+\exp (-2\&CenterDot;\mathrm{\&pi;}\&CenterDot;{\mathrm{\&omega;}}_u\&CenterDot;t)$ (formula 13)

V _ERROR2(t) extreme value occurs in t=∞ constantly,

Second error V _ERROR2(t) increasing to along with time t

R in the formula _SNSampling resistor R for the current mode step-up transformer _SNResistance.

By foregoing as seen, when input signal comprised step signal and ramp signal, the error that the step input is produced was exponential damping, and the error that the slope input is produced, but along with the time is exponential increase.Yet, in the current mode step-up transformer, the frequency of analog adder work is the frequency that is subjected to the clock signal OSC of oscillator, and the restriction of dutycycle D, thereby the error that can make analog adder is a very little value all the time, therefore, when the analog adder that the embodiment of the present application provides was applied in the current mode step-up transformer, the error of generation can be controlled near the very little value.

To sum up, the embodiment of the present application provides is applicable to analog adder in the current mode step-up transformer, the response speed that at the input signal initial value is 0 step response is far away faster than existing analog adder, and output error can be controlled near the very little value.

The embodiment of the present application also provides a kind of current mode step-up transformer, use the analog adder that the foregoing description provides, concrete, see also Fig. 5, this current mode step-up transformer mainly comprises: totalizer 100, error amplifier 101, PWM (Pulse Width Modulation, pulse-length modulation) comparer 102, pwm control circuit 103, and switching tube M1, wherein:

When pwm control circuit 103 output high level, switching tube M1 conducting, electric current flows to coil L from input power supply VIN, through switching tube M1, and sampling resistor R _SNBack inflow place end, this moment coil L storage power, output capacitance C _OUTProvide energy for load LOAD separately, when totalizer 100 output voltages when detecting voltage, pwm control circuit 103 output low levels, switching tube M1 turn-offs, electric current exports load LOAD to behind input power supply VIN flowing through coil L, diode D, at this moment, store the coil L of energy and import power supply VIN, thereby realize boosting jointly for load provides energy.

Concrete circuit structure is as follows:

The input signal of described totalizer 100 comprises: offset voltage, compensation ramp signal, and sensing voltage, the signal of output terminal output is as the input signal of the in-phase input end of PWM comparer.Wherein:

Offset voltage is for fear of the interference owing to ground, and perhaps the output signal of the totalizer 100 that the earth potential difference causes between inner each module of circuit incurs loss in transmission;

The compensation ramp signal is and the cycle synchronisation of the clock signal OSC of oscillator, and jagged compensation oblique wave electric current takes place, and is used for sensing voltage is revised, and makes dutycycle greater than 50% o'clock, subharmonic oscillation can not take place;

Electric current and the sampling resistor R of flowing through coil L when sensing voltage VSN is pwm control circuit 103 output high-level control signal _SNProduct, flow through the electric current of coil L by detection, can detect and the corresponding current variation of load.

Error amplifier 101, its inverting input input signal is a resistance R _FBOutput voltage, i.e. output current I _LOADIn resistance R _FBOn pressure drop, the in-phase input end input reference voltage source V REF of error amplifier 101, after error amplifier 101 amplifies the voltage of signals difference of two input end inputs, by output terminal output, and this output signal inputs to the inverting input of PWM comparer 102 as the detection voltage of PWM comparer 102.

The in-phase input end of PWM comparer 102 connects the output terminal of totalizer 100, and output terminal is connected to the input end of pwm control circuit 103, when the voltage signal of totalizer output surpasses described detectable voltage signals, and PWM comparer 102 output high level signals.

Pwm control circuit 103 is SR latchs, its reset terminal R connects the output terminal of PWM comparer, set end S input has the clock signal of oscillator, output terminal is connected to the control end of switching tube M1, when M1 when negative edge appears in clock signal OSC begins conducting, when the PWM comparator output signal was high level, M1 turn-offed.

Capacitor C among Fig. 2 _INBe used for stablizing input signal VIN, capacitor C _OUTWhen the conducting of M1 pipe, provide energy, R to output load _ESRIt is capacitor C _OUTSeries connection ESR resistance, load I _LOADExpression is a current loading.

Need to prove, in this article, relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or in proper order between these entities or the operation.

The above only is the application's a embodiment; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the application's protection domain.

Claims (9)

1. an analog adder is characterized in that, comprising: operational transconductance amplifier, offset current source, compensation oblique wave current source, first output resistance and second output resistance, wherein:

The reverse inter-input-ing ending grounding of operational transconductance amplifier, in-phase input end are the input end of this analog adder, and output terminal is connected to the hot end of described second output resistance, the other end ground connection of described second output resistance through first metal-oxide-semiconductor;

The grid of the 5th metal-oxide-semiconductor in the output stage of offset current source and described operational transconductance amplifier links to each other;

Compensation oblique wave current source links to each other with the described second output resistance hot end by first output resistance, and the hot end of described first output resistance is the output terminal of this analog adder.

2. analog adder according to claim 1 is characterized in that, described operational transconductance amplifier comprises: the first cascade bias unit, the input stage that is connected with described output stage, and backfeed loop, wherein:

The described first cascade bias unit links to each other with the metal-oxide-semiconductor of described input stage, is used to the metal-oxide-semiconductor of described input stage that bias current is provided;

Described input stage comprises: second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, be connected the feedback resistance of the described second metal-oxide-semiconductor source electrode, and second input resistance that is connected described the 3rd metal-oxide-semiconductor source electrode, the mirror current source of formation;

Described output stage also comprises: the 4th metal-oxide-semiconductor that is connected in series with described the 5th metal-oxide-semiconductor, wherein, the drain electrode of described the 5th metal-oxide-semiconductor connects the 4th metal-oxide-semiconductor, and the grid of described the 5th metal-oxide-semiconductor links to each other with the drain electrode of described the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor connects described offset current source;

Described backfeed loop comprises: described first metal-oxide-semiconductor and the 5th metal-oxide-semiconductor, and the grid of described first metal-oxide-semiconductor connects the drain electrode of described the 5th metal-oxide-semiconductor, and the source electrode of described the 5th metal-oxide-semiconductor is connected to the hot end of described feedback resistance.

3. analog adder according to claim 2 is characterized in that, the described first cascade bias unit comprises: bias current sources, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, wherein:

The source electrode of described the 6th metal-oxide-semiconductor connects dc positive power, and drain electrode connects the negative output terminal of described bias current sources, the positive output end ground connection of described bias current sources;

The grid of described the 7th metal-oxide-semiconductor connects the grid of described the 6th metal-oxide-semiconductor, and the source electrode of described the 7th metal-oxide-semiconductor connects described dc positive power, and the drain electrode of described the 7th metal-oxide-semiconductor connects the drain electrode of described second metal-oxide-semiconductor;

The grid of described the 8th metal-oxide-semiconductor connects the grid of described the 6th metal-oxide-semiconductor, and the source electrode of described the 8th metal-oxide-semiconductor connects described dc positive power, and the drain electrode of described the 8th metal-oxide-semiconductor connects the drain electrode of described the 3rd metal-oxide-semiconductor.

4. analog adder according to claim 3 is characterized in that:

The source electrode of the 4th metal-oxide-semiconductor in the described output stage connects dc positive power, the grid of described the 4th metal-oxide-semiconductor connects the drain electrode of the 4th metal-oxide-semiconductor, the drain electrode of the 4th metal-oxide-semiconductor connects the drain electrode of described the 5th metal-oxide-semiconductor, the source electrode of described the 5th metal-oxide-semiconductor connects the hot end of described feedback resistance, the grid of described the 5th metal-oxide-semiconductor connects the drain electrode of described the 3rd metal-oxide-semiconductor, and the grid of the 5th metal-oxide-semiconductor links to each other with described offset current source.

5. analog adder according to claim 4, it is characterized in that, the grid of described first metal-oxide-semiconductor connects the grid of described the 4th metal-oxide-semiconductor, and the source electrode of described first metal-oxide-semiconductor connects dc positive power, and the drain electrode of described first metal-oxide-semiconductor connects the hot end of described second output resistance.

6. analog adder according to claim 5 is characterized in that, also comprises:

Be connected the second cascade bias unit between described first cascade bias unit and the described input stage, wherein:

The described second cascade bias unit comprises: the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor, and second bias current sources, wherein:

The grid of described the 9th metal-oxide-semiconductor is connected with drain electrode, and should drain electrode connect described second bias supply;

Described the tenth metal-oxide-semiconductor is serially connected between described the 7th metal-oxide-semiconductor and second metal-oxide-semiconductor, and the grid of described the tenth metal-oxide-semiconductor is connected with the grid of described the 9th metal-oxide-semiconductor;

Described the 11 metal-oxide-semiconductor is connected in series between described the 8th metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, and the grid of described the 11 metal-oxide-semiconductor is connected with the grid of described the 9th metal-oxide-semiconductor.

7. analog adder according to claim 6 is characterized in that, described second metal-oxide-semiconductor, described the 3rd metal-oxide-semiconductor and described the 5th metal-oxide-semiconductor are the NMOS pipe.

8. analog adder according to claim 6, it is characterized in that described first metal-oxide-semiconductor, described the 4th metal-oxide-semiconductor, described the 6th metal-oxide-semiconductor, described the 7th metal-oxide-semiconductor, described the 8th metal-oxide-semiconductor, described the 9th metal-oxide-semiconductor, described the tenth metal-oxide-semiconductor and described the 11 metal-oxide-semiconductor are the PMOS pipe.

9. current mode step-up transformer, comprise: error amplifier, pulse width modulation (PWM) comparer, pwm control circuit and switching tube, it is characterized in that, also comprise: each described analog adder of claim 1-8, the sensing voltage input end of this analog adder is connected to the source electrode of described switching tube, and the output terminal of this analog adder is connected to the in-phase input end of described PWM comparer.

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