CN110472420B - Binding identification method, system, terminal equipment and storage medium - Google Patents
Binding identification method, system, terminal equipment and storage medium Download PDFInfo
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- CN110472420B CN110472420B CN201910656269.8A CN201910656269A CN110472420B CN 110472420 B CN110472420 B CN 110472420B CN 201910656269 A CN201910656269 A CN 201910656269A CN 110472420 B CN110472420 B CN 110472420B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/81—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
Abstract
The invention is suitable for the technical field of computers, and provides a binding identification method, a system, a terminal device and a storage medium. According to the embodiment of the invention, the specific basic input/output system chip is bound with the specific mainboard, when the specific basic input/output system chip is connected with the mainboard which is not bound, the mainboard cannot be normally started, and when the specific basic input/output system chip is connected with the mainboard which is not bound, the mainboard can be directly shut down, so that the private information of a user is effectively protected, and the safety of the basic input/output system chip and the mainboard is ensured.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a binding identification method, a binding identification system, terminal equipment and a storage medium.
Background
At present, in order to ensure the universality of a main board and a basic input and output system, the main board and the basic input and output system of the same type can be arbitrarily interchanged and started, namely, a chip of the basic input and output system can be randomly applied to other main boards of the same type and started, so that although the application range of the main board and the basic input and output system is expanded, the defects of insufficient confidentiality and safety are overcome, private information of a user cannot be effectively protected, once a security hole appears, the same security hole can possibly appear on the chip of the basic input and output system of the same type and the main board of the same type, and therefore, economic and security damages are brought to the user.
Disclosure of Invention
In view of this, embodiments of the present invention provide a binding identification method, system, terminal device and storage medium, so as to solve the problem of insufficient security and safety between a basic input/output system chip and a motherboard in the prior art.
A first aspect of an embodiment of the present invention provides a binding identification method, which is implemented by a basic input/output system and a motherboard, where the motherboard is in communication connection with the basic input/output system through a first input/output line and a second input/output line, and the binding identification method includes the following operations performed by the motherboard:
when the power-on operation is executed, the level states of the first input-output line and the second input-output line are set to be a first level state;
detecting the level states of the first input-output line and the second input-output line in real time;
the basic input and output system is used for switching the level state of the first input and output line to a second level state after initialization;
when the first input/output line is detected to be in a second level state, controlling the second input/output line to be switched to the second level state;
judging whether the level states of the first input-output line and the second input-output line are the second level state;
if the level states of the first input-output line and the second input-output line are both the second level states, determining that the mainboard is bound with the basic input-output system, and continuing to execute the starting operation;
and if the level states of the first input/output line or the second input/output line are both the first level states, judging that the mainboard and the basic input/output system are not bound, and entering a program of a loop locking machine.
In one embodiment, the bios is configured to transmit data unidirectionally to the motherboard via the first i/o line, and the motherboard is configured to communicate bidirectionally with the bios via the second i/o line.
In one embodiment, the determining whether the level states of the first input-output line and the second input-output line are both the second level state includes:
acquiring the level states of a first input-output line and a second input-output line;
judging whether the first input/output line is in a second level state;
if the first input/output line is in the second level state, determining whether the second input/output line is in the second level state.
In one embodiment, at power-on, after setting the level states of the first input-output line and the second input-output line to the first level state, the method further includes:
starting a timing program;
after the timing program is started for preset time, acquiring the level state of the first input and output line;
and if the first input/output line is in a second level state, the basic input/output system chip is a non-binding basic input/output system chip and executes shutdown operation.
In one embodiment, the starting the timer procedure comprises:
a watchdog program is started for a preset time.
In one embodiment, the predetermined time is 40-80 seconds.
In one embodiment, the first level is a high level and the second level is a low level.
A second aspect of an embodiment of the present invention provides a binding identification system, including:
the first control module is used for setting the level states of the first input-output line and the second input-output line to be a first level state when the power-on execution starting-up operation is carried out;
the detection module is used for detecting the level states of the first input and output line and the second input and output line in real time;
the second control module is used for switching the level state of the first input and output line to a second level state after the basic input and output system is initialized;
the third control module is used for controlling the second input/output line to be switched to a second level state when the first input/output line is detected to be in the second level state;
and the judging module is used for judging whether the levels of the first input output line and the second input output line are both in the second level state.
As an embodiment of the second aspect of the present invention, the bios is configured to transmit data unidirectionally to the motherboard via the first input/output line, and the motherboard is configured to communicate bidirectionally with the bios via the second input/output line.
A third aspect of an embodiment of the present invention provides a terminal device, including:
the computer system comprises a memory, a mainboard and a computer program which is stored in the memory and can run on the mainboard, wherein the mainboard realizes the steps of any embodiment of the first aspect of the embodiment of the invention when executing the computer program.
A fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a motherboard, implements the steps as in any one of the embodiments of the first aspect of the embodiments of the present invention.
The embodiment of the invention provides a binding identification method, a binding identification system, terminal equipment and a storage medium, wherein a specific basic input/output system chip is bound with a specific mainboard, when the specific basic input/output system chip is connected with the mainboard which is not bound, the mainboard cannot be normally started, and when the specific basic input/output system chip is connected with the mainboard which is not bound, the mainboard can be directly shut down, so that the private information of a user is effectively protected, and the safety of the basic input/output system chip and the mainboard is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is an interaction diagram of a basic input/output system and a motherboard according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating an implementation process of a binding identification method according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating an implementation process of a binding identification method timing program according to an embodiment of the present invention;
FIG. 4 is a diagram of a binding identification system provided by an embodiment of the invention;
fig. 5 is a schematic diagram of a terminal device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood by those skilled in the art, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
Example one
The embodiment provides a binding identification method, which is implemented based on a Basic Input Output System (BIOS) and a main board, where the main board is in communication connection with the BIOS through a first Input Output line and a second Input Output line.
In application, the basic input/output system and the motherboard may be devices in a computing device with computing and control functions, such as a personal computer, a notebook computer, a tablet computer, a server, a mobile phone, a palmtop computer, and the like, and the binding identification method provided in this embodiment may be specifically executed by a processor of the motherboard.
In Application, the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable Logic device (CPLD), a discrete Gate or transistor Logic device, a discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
As shown in fig. 1, a schematic diagram of a connection structure of a motherboard 2 and a basic input/output system 1 is exemplarily shown; the basic input and output system 1 is configured to transmit data to the motherboard unidirectionally through the first input and output line GPIO1, and the motherboard 2 is configured to communicate with the basic input and output system 1 bidirectionally through the second input and output line GPIO 2.
In an application, the first input-output line and the second input-output line may be General-purpose input/output (GPIO) data lines.
As shown in fig. 2, the binding identification method provided in this embodiment includes the following operations performed by the processor of the motherboard:
and S201, when the power-on operation is executed in the power-on state, setting the level states of the first input-output line and the second input-output line to be a first level state.
In application, the binding check of the motherboard and the basic input/output system includes that firstly, a basic input/output system chip is inserted into the motherboard, security check is performed, after no problem is confirmed, the motherboard is powered on and started, control signals of a first input/output line and a second input/output line are initially defaulted to be first level signals, and after the motherboard is powered on, the first input/output line and the second input/output line are powered on and are in a first level state, wherein the first level represents a level state, and the first level can be a high level or a low level.
In one embodiment, step S201 is followed by:
s, 303: starting a timing program;
the timing program is a judgment program which is triggered once every a period of time, and after the timing program is triggered, if the basic input output system chip is a correct basic input output system chip, the level state of the first input output line is forced to return to an default initial level, namely a first level state.
S304: after the timing program is started for preset time, acquiring the level state of the first input and output line;
as described above, the timer procedure is a determination procedure that is triggered every certain period of time, and therefore, the acquired level state of the first input/output line is also the level of the first input/output line triggered after a preset time period elapses.
S306: and if the first input/output line is in a second level state, the basic input/output system chip is a non-binding basic input/output system chip and executes shutdown operation.
In one embodiment, the starting the timer procedure comprises:
a watchdog program is started for a preset time.
The watchdog, also called watchdog timer, is a timer circuit, generally has an input, called feeding dog, when the micro control unit normally works, it outputs a signal to the feeding dog end at intervals, and clears the WDT to zero, so that the watchdog program restarts timing, and by the above characteristics of the watchdog circuit, we can implement a timing program that is triggered at intervals.
In one embodiment, the predetermined time is 40-80 seconds.
S202: detecting the level states of the first input-output line and the second input-output line in real time; the basic input and output system is used for switching the level state of the first input and output line to a second level state after initialization.
In application, since the present embodiment determines whether the motherboard and the bios are bound according to the level states of the first input output line and the second input output line, it is necessary to detect the level states of the first input output line and the second input output line at any time to ensure that the change information can be transmitted to the corresponding components to make corresponding changes when the level states of the first input output line and the second input output line are changed, and the level of the first input output line and the level of the second input output line can be detected by disposing a dedicated level measurer.
After the mainboard is powered on and started, a basic input and output program is started and initialized, a control signal of the first input and output line is changed, and the level state of the first input and output line is changed into a second level state; wherein the second level is a level distinguished from the first level, and represents a level different from the first level.
S203: and when the first input/output line is detected to be in a second level state, controlling the second input/output line to be switched to the second level state.
In application, when the mainboard is a mainboard bound with a basic input and output system, the level state of the second input and output line can change along with the level state of the first input and output line, the level of the first input and output line is controlled by the basic input and output system, and when the level of the first input and output line changes, the bound mainboard can control the level of the second input and output line to change correspondingly; for example, the first input/output line and the second input/output line are initially at a high level, after the basic input/output program is started, the level of the first input/output line is changed to a low level, the binding main board detects the level change of the first input/output line, and the main board correspondingly controls the level of the second input/output line to be changed to the low level.
S204: and judging whether the level states of the first input-output line and the second input-output line are the second level state or not.
In application, the level states of the first input output line and the second input output line have several possibilities, firstly, a basic input output program is normally started, the first input output line is changed into the second level state, and meanwhile, the mainboard can detect the level change of the first input output line and control the level of the second input output line to be changed into the second level state; secondly, the basic input and output program is normally started, the first input and output line is changed into a second level state, the mainboard cannot detect the level change of the first input and output line or detect the level change of the second input and output line but does not change the level state of the second input and output line or detect the level change of the second input and output line but cannot control the level state of the second input and output line to change, and at this time, the level state of the second input and output line is the second level state; thirdly, if the basic input/output program cannot be started normally, the level state of the first input/output line is not changed, the level state of the second input/output line is not changed, and both the first input/output line and the second input/output line are in a high level state.
In one embodiment, step S204 is followed by:
acquiring the level states of a first input-output line and a second input-output line;
as described above, the level states of the first input/output line and the second input/output line can be detected in real time by the level measuring device, and therefore, the level states of the first input/output line and the second input/output line can be obtained at any time, but the level states of the first input/output line and the second input/output line to be obtained in this step are the level states after the level changes of the first input/output line and the second input/output line, and of course, the level states of the first input/output line or the second input/output line may not change, and the obtained level states are the level states after the flow time of the above-mentioned steps S201 to S203.
Judging whether the first input/output line is in a second level state;
when the first input/output line is in the first level state, the basic input/output system may be out of order, or the motherboard cannot support normal startup of the basic input/output system, and the motherboard cannot be normally started.
If the first input/output line is in the second level state, determining whether the second input/output line is in the second level state.
When the second mainboard is in the second level state, the startup detection is passed, the mainboard is normally started, when the second input output line is in the first level state, the mainboard sends the level information of the second input output line through the second input output line, the startup detection is not passed, and the mainboard enters the crash.
The first level and the second level are not used as the only standard for determining whether the basic input/output system chip and the main board are bound, but are only an optimal implementation manner, and other signals can be used as detection signals, such as on-off of a switch, when the basic input/output program is normally started, corresponding signals are output, the switch is judged to be closed, wherein an ammeter is connected in series with a circuit provided with the switch to detect whether the switch is closed, and two judgment switches are arranged to be used for determining whether the basic input/output system chip and the main board are bound; the detection signal may be an additional characteristic due to a change in a signal, for example, an element that generates a magnetic field in accordance with a change in a level is provided in each of the first input/output line and the second input/output line, and whether or not a change in a potential occurs in the first input/output line and the second input/output line is detected by detecting the magnetic field.
S205: and if the level states of the first input output line and the second input output line are both the second level states, determining that the mainboard is bound with the basic input output system, and continuing to execute the starting operation.
In application, the basic input and output program is normally started, the first input and output line is changed into the second level state, meanwhile, the mainboard can detect the level change of the first input and output line and control the level of the second input and output line to be changed into the second level state, at the moment, the mainboard can be judged to be bound with the basic input and output system, and then the starting operation is normally executed.
S206: and if the level states of the first input/output line or the second input/output line are both the first level states, judging that the mainboard and the basic input/output system are not bound, and entering a program of a loop locking machine.
In application, when the second and third possibilities of the level states of the first input-output line and the second input-output line appear, the main board is not bound with the basic input-output system, and the basic input-output program performs the dead-cycle control, so that the main board enters the dead-cycle shutdown program.
In one embodiment, the bios is configured to transmit data unidirectionally to the motherboard via the first i/o line, and the motherboard is configured to communicate bidirectionally with the bios via the second i/o line.
In one embodiment, step S204 is followed by:
acquiring the level states of a first input-output line and a second input-output line;
as described above, the level states of the first input/output line and the second input/output line can be detected in real time by the level measuring device, and therefore, the level states of the first input/output line and the second input/output line can be obtained at any time, but the level states of the first input/output line and the second input/output line to be obtained in this step are the level states after the level changes of the first input/output line and the second input/output line, and of course, the level states of the first input/output line or the second input/output line may not change, and the obtained level states are the level states after the flow time of the above-mentioned S201 to S204.
Judging whether the first input/output line is in a second level state;
when the first input/output line is in the first level state, the basic input/output system may be out of order, or the motherboard cannot support normal startup of the basic input/output system, and the motherboard cannot be normally started.
If the first input/output line is in the second level state, determining whether the second input/output line is in the second level state.
When the second mainboard is in the second level state, the startup detection is passed, the mainboard is normally started, when the second input output line is in the first level state, the mainboard sends the level information of the second input output line through the second input output line, the startup detection is not passed, and the mainboard enters the crash.
The first level and the second level are not used as the only standard for determining whether the basic input/output system chip and the main board are bound, but are only an optimal implementation manner, and other signals can be used as detection signals, such as on-off of a switch, when the basic input/output program is normally started, corresponding signals are output, the switch is judged to be closed, wherein an ammeter is connected in series with a circuit provided with the switch to detect whether the switch is closed, and two judgment switches are arranged to be used for determining whether the basic input/output system chip and the main board are bound; the detection signal may be an additional characteristic due to a change in a signal, for example, an element that generates a magnetic field in accordance with a change in a level is provided in each of the first input/output line and the second input/output line, and whether or not a change in a potential occurs in the first input/output line and the second input/output line is detected by detecting the magnetic field.
The embodiment of the invention provides a binding identification method, which binds a specific basic input/output system chip with a specific motherboard, when the specific basic input/output system chip is connected with the motherboard which is not bound, the motherboard cannot be normally started, and when the specific basic input/output system chip is connected with the motherboard which is not bound, the motherboard is directly shut down, so that private information of a user is effectively protected, and the security of the basic input/output system chip and the motherboard is ensured.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Example two:
referring to fig. 4, the present embodiment provides a binding identification system 4 for executing the method steps of the first embodiment, where the binding identification system 4 includes: a first control module 41, a second control module 43, a third control module 44, a detection module 42, and a determination module 45.
The first control module 41 is configured to set the level states of the first input/output line and the second input/output line to a first level state when the power-on operation is performed;
the detection module 42 is used for detecting the level states of the first input-output line and the second input-output line in real time;
a second control module 43, configured to switch the level state of the first input/output line to a second level state after the basic input/output system is initialized;
a third control module 44, configured to control the second input/output line to switch to a second level state when the first input/output line is detected to be in the second level state;
and the judging module 45 is configured to judge whether the levels of the first input/output line and the second input/output line are both in the second level state.
In one embodiment, the binding identification system further comprises:
and the acquisition module is used for acquiring the level states of the first input-output line and the second input-output line.
The sequence judging module is used for judging whether the first input and output line is in a second level state or not; and after the first input/output line is judged to be in the second level state, whether the second input/output line is in the second level state is judged.
In one embodiment, the binding identification system further comprises:
the timing module is used for starting a timing program; after the timing program is started for preset time, acquiring the level state of the first input/output line;
the judging module is further configured to judge a level state of a first input/output line after a timing program is triggered, and if the first input/output line is in a second level state, judge that the basic input/output system chip which is not bound to the motherboard and the basic input/output system is an unbound basic input/output system chip, and execute a shutdown operation
In application, each module in the binding identification system may be a software program module in a processor of the terminal device, may also be implemented by different processors, and may also be implemented by different logic circuit structures in one processor of the terminal device.
The embodiment binds the specific basic input/output system chip with the specific mainboard by providing a binding identification system, when the specific basic input/output system chip is connected with the basic input/output system chip and is not bound with the mainboard, the mainboard cannot be normally started, and when the specific basic input/output system chip is connected with the mainboard and is not bound with the mainboard, the mainboard can be directly shut down, so that the private information of a user is effectively protected, and the safety of the basic input/output system chip and the mainboard is ensured.
EXAMPLE III
As shown in fig. 5, the present embodiment provides a terminal device 5, which includes: a motherboard 2, a bios 1, a processor 50, a memory 51, and a computer program 52, such as a bios program, stored in the memory 51 and executable on the processor 50. In this example, the motherboard includes a processor 50, and when the processor 50 executes the computer program 52, the steps in the above-described embodiment of the binding identification method, for example, steps S201 to S206 in the first embodiment, are implemented. Alternatively, the processor 50, when executing the computer program 52, implements the functions of the modules/units in the above-mentioned device embodiments, such as the functions of the modules 41 to 45 shown in fig. 4.
Illustratively, the computer program 52 may be partitioned into one or more modules/units that are stored in the memory 51 and executed by the processor 50 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of the computer program 52 in the terminal device 5. For example, the computer program 52 may be divided into a first control module, a second control module, a third control module, a detection module, and a judgment module, and the specific functions of each module are as follows:
the first control module is used for setting the level states of the first input-output line and the second input-output line to be a first level state when the power-on execution starting-up operation is carried out;
the detection module is used for detecting the level states of the first input and output line and the second input and output line in real time;
the second control module is used for switching the level state of the first input and output line to a second level state after the basic input and output system is initialized;
the third control module is used for controlling the second input/output line to be switched to a second level state when the first input/output line is detected to be in the second level state;
and the judging module is used for judging whether the levels of the first input output line and the second input output line are both in the second level state.
The terminal device 5 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device may include, but is not limited to, a processor 50, a memory 51. It will be understood by those skilled in the art that fig. 5 is only an example of the terminal device 5, and does not constitute a limitation to the terminal device 5, and may include more or less components than those shown, or combine some components, or different components, for example, the terminal device 5 may further include an input-output device, a network access device, a bus, etc.
The processor 50 may be a Central Processing Unit (CPU), other general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5. The memory 51 may also be an external storage device of the terminal device 5, such as a plug-in hard disk provided on the terminal device 5, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card (FlashCard), and the like. Further, the memory 51 may also include both an internal storage unit and an external storage device of the terminal device 5. The memory 51 is used for storing the computer program and other programs and data required by the terminal device. The memory 51 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed binding identification method and system, terminal device, and storage medium may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the binding identification method according to the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium and can implement the steps of the above embodiments of the method when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer memory, Read-only memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A binding identification method is realized based on a basic input output system and a mainboard, the mainboard is in communication connection with the basic input output system through a first input output line and a second input output line, and the binding identification method comprises the following operations executed by the mainboard:
when the power-on operation is executed, the level states of the first input-output line and the second input-output line are set to be a first level state;
detecting the level states of the first input-output line and the second input-output line in real time; the basic input and output system is used for switching the level state of the first input and output line to a second level state after initialization;
when the first input/output line is detected to be in a second level state, controlling the second input/output line to be switched to the second level state;
judging whether the level states of the first input-output line and the second input-output line are the second level state;
if the level states of the first input-output line and the second input-output line are both the second level states, determining that the mainboard is bound with the basic input-output system, and continuing to execute the starting operation;
and if the level states of the first input/output line or the second input/output line are both the first level states, judging that the mainboard and the basic input/output system are not bound, and entering a program of a loop locking machine.
2. The binding recognition method of claim 1, wherein the bios is configured to transmit data unidirectionally to the motherboard via the first i/o line, and the motherboard is configured to communicate bidirectionally with the bios via the second i/o line.
3. The binding identification method according to claim 1, wherein said judging whether the level states of the first input-output line and the second input-output line are both the second level state comprises:
acquiring the level states of a first input-output line and a second input-output line;
judging whether the first input/output line is in a second level state;
if the first input/output line is in the second level state, determining whether the second input/output line is in the second level state.
4. The binding identification method according to any one of claims 1 to 3, wherein after setting the level states of the first input-output line and the second input-output line to the first level state at power-on, further comprising:
starting a timing program;
after the timing program is started for preset time, acquiring the level state of the first input and output line;
and if the first input/output line is in a second level state, judging that the mainboard and the basic input/output system are not bound, and executing shutdown operation.
5. The binding identification method according to claim 4, wherein the starting of the timer comprises:
a watchdog program is started for a preset time.
6. The binding recognition method of claim 4, wherein the predetermined time is 40-80 seconds.
7. The binding identification method according to any of claims 1 to 3, wherein the first level is a high level and the second level is a low level.
8. A binding identification system, comprising:
the first control module is used for setting the level states of the first input-output line and the second input-output line to be a first level state when the power-on execution starting-up operation is carried out;
the detection module is used for detecting the level states of the first input and output line and the second input and output line in real time;
the second control module is used for switching the level state of the first input and output line to a second level state after the basic input and output system is initialized;
the third control module is used for controlling the second input/output line to be switched to a second level state when the first input/output line is detected to be in the second level state;
the judging module is used for judging whether the levels of the first input output line and the second input output line are both in the second level state;
if the level states of the first input-output line and the second input-output line are both the second level state, determining that the mainboard is bound with the basic input-output system, and continuing to execute the starting operation;
and if the level states of the first input/output line or the second input/output line are both the first level states, judging that the mainboard and the basic input/output system are not bound, and entering a program of a loop locking machine.
9. A terminal device comprising a memory, a bios, a motherboard and a computer program stored in the memory and executable on the motherboard, wherein the steps of the method according to any of claims 1 to 7 are implemented by the motherboard when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when executed by a motherboard, implements the steps of the method according to any one of claims 1 to 7.
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008127431A2 (en) * | 2006-11-21 | 2008-10-23 | Verient, Inc. | Systems and methods for identification and authentication of a user |
| CN104753518A (en) * | 2013-12-27 | 2015-07-01 | 鸿富锦精密工业(武汉)有限公司 | Control circuit |
| CN104899055A (en) * | 2015-05-06 | 2015-09-09 | 深圳市国鑫恒宇科技有限公司 | BIOS control based ME updating system and updating method thereof |
| CN105354116A (en) * | 2015-10-23 | 2016-02-24 | 青岛海信移动通信技术股份有限公司 | Hot-plug detection method, apparatus, system and mobile terminal |
| CN105487896A (en) * | 2015-11-27 | 2016-04-13 | 南京熊猫电子股份有限公司 | Use method of embedded mainboard in different equipment |
| CN106250725A (en) * | 2016-08-02 | 2016-12-21 | 浪潮电子信息产业股份有限公司 | A kind of ARM platform prevents the method that UEFI program is illegally transplanted |
| US9607666B2 (en) * | 2015-06-16 | 2017-03-28 | SK Hynix Inc. | Input/output circuit and input/output device including the same |
| CN106598564A (en) * | 2016-10-24 | 2017-04-26 | 郑州云海信息技术有限公司 | Method for implementing BIOS capable of self-adapting to different main boards, BIOS, and main board |
| CN108256336A (en) * | 2018-02-09 | 2018-07-06 | 深圳市杰和科技发展有限公司 | The binding and recognition methods of operating system and mainboard |
| US20180253556A1 (en) * | 2017-03-02 | 2018-09-06 | Qualcomm Incorporated | Selective restoration and authentication of a secure image |
| CN109583214A (en) * | 2018-11-28 | 2019-04-05 | 北京可信华泰信息技术有限公司 | A kind of method of controlling security |
| CN109670349A (en) * | 2018-12-13 | 2019-04-23 | 英业达科技有限公司 | The hardware structure of trusted computer and the credible starting method of computer |
| US20190213339A1 (en) * | 2018-01-09 | 2019-07-11 | Booz Allen Hamilton Inc. | System and method for controlling the power states of a mobile computing device |
-
2019
- 2019-07-19 CN CN201910656269.8A patent/CN110472420B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008127431A2 (en) * | 2006-11-21 | 2008-10-23 | Verient, Inc. | Systems and methods for identification and authentication of a user |
| CN104753518A (en) * | 2013-12-27 | 2015-07-01 | 鸿富锦精密工业(武汉)有限公司 | Control circuit |
| CN104899055A (en) * | 2015-05-06 | 2015-09-09 | 深圳市国鑫恒宇科技有限公司 | BIOS control based ME updating system and updating method thereof |
| US9607666B2 (en) * | 2015-06-16 | 2017-03-28 | SK Hynix Inc. | Input/output circuit and input/output device including the same |
| CN105354116A (en) * | 2015-10-23 | 2016-02-24 | 青岛海信移动通信技术股份有限公司 | Hot-plug detection method, apparatus, system and mobile terminal |
| CN105487896A (en) * | 2015-11-27 | 2016-04-13 | 南京熊猫电子股份有限公司 | Use method of embedded mainboard in different equipment |
| CN106250725A (en) * | 2016-08-02 | 2016-12-21 | 浪潮电子信息产业股份有限公司 | A kind of ARM platform prevents the method that UEFI program is illegally transplanted |
| CN106598564A (en) * | 2016-10-24 | 2017-04-26 | 郑州云海信息技术有限公司 | Method for implementing BIOS capable of self-adapting to different main boards, BIOS, and main board |
| US20180253556A1 (en) * | 2017-03-02 | 2018-09-06 | Qualcomm Incorporated | Selective restoration and authentication of a secure image |
| US20190213339A1 (en) * | 2018-01-09 | 2019-07-11 | Booz Allen Hamilton Inc. | System and method for controlling the power states of a mobile computing device |
| CN108256336A (en) * | 2018-02-09 | 2018-07-06 | 深圳市杰和科技发展有限公司 | The binding and recognition methods of operating system and mainboard |
| CN109583214A (en) * | 2018-11-28 | 2019-04-05 | 北京可信华泰信息技术有限公司 | A kind of method of controlling security |
| CN109670349A (en) * | 2018-12-13 | 2019-04-23 | 英业达科技有限公司 | The hardware structure of trusted computer and the credible starting method of computer |
Non-Patent Citations (3)
| Title |
|---|
| 可信计算的安全防护机制及其在高可信网络中的应用;郝平;《中国电子科学研究院学报》;20080520;第3卷(第1期);第14-19页 * |
| 基于可信计算及 SGX 的软件保护方法;黄冬;《通信技术》;20171128;第50卷(第10期);第2340-2344页 * |
| 基于硬件的计算机安全策略;匡春光;《微处理机》;20110915;第32卷(第1期);第89-91页 * |
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