CN110263485B - Automatic drawing system and computer system for chip packaging diagram - Google Patents
Automatic drawing system and computer system for chip packaging diagram Download PDFInfo
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Abstract
The invention relates to an automatic drawing system and a computer system of a chip packaging diagram, which are characterized in that the automatic drawing system comprises a comprehensive information database of an integrated circuit bare chip, a packaging type acquisition module, a functional port information acquisition module and a packaging diagram drawing module; the comprehensive information database provides data support for other modules; the package type acquisition module acquires the package type of the chip in the comprehensive information database; the function port information acquisition module is used for acquiring the name of a function port correspondingly connected with each pin of the chip and all the use functions of the function port in the comprehensive information database; and the packaging diagram drawing module is used for automatically drawing the packaging diagram. The automatic drawing system effectively solves various defects caused by manual drawing, can effectively accelerate the development speed of the chip, ensures the accuracy rate of the packaging diagram and reduces the labor cost; and the application range is wide, and the method is suitable for chip development based on various integrated circuit bare chips.
Description
All as the field of technology
The invention relates to the technical field of drawing of chip packaging diagrams, in particular to an automatic drawing system of a chip packaging diagram and a computer system.
The background art
Chips, also known as microcircuits (microcircuits), microchips (microchips), and Integrated Circuits (ICs). Refers to a silicon chip containing integrated circuits, which is small in size and is often part of a computer or other electronic device.
The chip packaging is that an integrated circuit bare chip produced by Foundation is placed on a substrate with a bearing function, functional ports are led out, and then the integrated circuit bare chip is fixedly packaged into a whole to form a required chip, and the led-out functional ports are correspondingly connected to pins of the chip. In practical application, according to different needs of a user, all the functional ports of the integrated circuit die are not used, only a part of the functional ports are used, if the chip is led out of all the functional ports of the integrated circuit die, the chip occupies a large area, and miniaturization development of various electronic devices is not facilitated, so that in practical application, the required functional ports are led out, the unnecessary functional ports are not led out, and then the chip is packaged, so that the area occupied by the chip can be effectively reduced.
After the chip package design is completed, the package content needs to be checked, and a package diagram is drawn for a user to confirm, wherein the checking of the package content is mainly used for checking whether a function port with repeated lead-out exists, whether a function port with error lead-out exists, whether some function ports are missed or not, and the drawing of the package diagram comprises drawing of a chip arrangement mode of the chip package, names of the lead-out function ports and all functions of the function ports; due to the variety of the packaging types of the chip, such as SOP/LQFP/QFN/BGA/DIP, the pin arrangement of the chip is different in each packaging type, and the number of the chip pins is different, the chip can be divided into different packaging types in each packaging type, for example, SOP16/SOP24/SOP32 respectively represents that the packaging type is SOP, and the number of the chip pins (or the number of the extracted functional ports) is 16/24/32.
In the prior art, verification of chip packaging and drawing of a packaging diagram are mostly completed manually, and the above description shows that the packaging types have diversity, if the verification is completed manually, a large amount of workload is often needed, a large amount of time is consumed, and in addition, once errors occur, the whole chip can not be used; moreover, in the development process, the names of the functional ports of the integrated circuit bare chip and the functions of the functional ports may also be changed, or when the functions of the pins of the chip are changed, the package content is changed, and at this time, the package content of the chip needs to be checked again and a package diagram needs to be drawn again; the verification of the chip package and the drawing of the package diagram by manpower are low in working efficiency, low in accuracy, long in chip development time and high in labor cost.
All the contents of the invention
The invention aims to provide an automatic core drawing system for a chip packaging diagram, which has the advantages of high accuracy, high chip development speed and the like. The invention is realized by the following technical scheme:
an automatic drawing system of a chip packaging diagram is characterized by comprising a comprehensive information database of an integrated circuit bare chip, a packaging type acquisition module, a functional port information acquisition module and a packaging diagram drawing module;
the comprehensive information database comprises the name of each functional port of the integrated circuit bare chip, all the use functions corresponding to each functional port, and a plurality of packaging types based on the integrated circuit bare chip, wherein the packaging types comprise packaging modes and the pin number of the chip, and the comprehensive information database also comprises the connection relation between each functional port of the integrated circuit bare chip and the pin of the chip of each packaging type;
the package type acquisition module is used for acquiring the package type of the chip needing to be drawn in the package diagram from the comprehensive information database;
the function port information acquisition module comprises a name acquisition submodule of a function port and a function acquisition submodule, and the name acquisition submodule is used for acquiring the name of the function port correspondingly connected with each pin of the chip in the comprehensive information database; the function acquisition submodule is used for acquiring all use functions of the function port connected with each pin of the chip in the comprehensive information database;
and the package drawing module automatically draws the package according to the package type and the functional port name corresponding to each pin of the chip.
Preferably, the functional port information obtaining module further includes an automatic checking sub-module, configured to confirm accuracy of the name of the functional port corresponding to each pin of the chip.
Specifically, the confirming the accuracy of the functional port name includes confirming whether each pin of the chip has a missing functional port, and if the pin is missed, prompting;
or, the determining the accuracy of the functional port name includes determining whether the functional port corresponding to each pin of the chip has a duplicate name, and if the functional port has the duplicate name, prompting.
Preferably, the chip further comprises a package diagram file generating module, which generates a package diagram file according to the package type, the functional port name corresponding to each pin of the chip, and all the functions used by the functional ports; and the packaging diagram drawing module automatically draws a chip packaging diagram according to the packaging diagram file.
Preferably, the system further comprises a package diagram storage module for storing the drawn chip package diagram.
Specifically, the automatic drawing system is compiled by adopting an object-oriented programming language.
Specifically, the packaging manner is SOP, LQPF, QFN, BGA, or DIP, and may be any packaging manner known in the art, which is not listed here.
Further, the package type obtaining module is further configured to determine whether a correct package type exists.
Specifically, the package diagram includes a package type, a number of each pin of the chip, a name of a function port to which each pin of the chip is correspondingly connected, and all use functions corresponding to each function port.
The second object of the present invention is to provide a computer system, and the second object of the present invention is achieved by the following technical solutions:
a computer system comprising a memory storing a program for use by an automatic rendering system supporting the first object of the present invention, and a processor configured to execute the program stored in the memory.
The invention has the beneficial technical effects that: the automatic drawing method of the chip packaging diagram effectively solves various defects caused by manual drawing, can effectively accelerate the development speed of the chip, ensures the accuracy rate of the packaging diagram and reduces the labor cost; and the application range is wide, and the method is suitable for chip development based on various integrated circuit bare chips.
Description of the drawings
FIG. 1 is a block diagram of an automatic drawing system for a chip package diagram provided by the present invention;
FIG. 2 is a flow chart of a method for automatically rendering a package diagram according to an embodiment of the present invention;
FIG. 3 is a package diagram of an integrated circuit die based package type SOP28 according to an embodiment of the present invention;
FIG. 4 is a diagram of a package of the SOP20 type based on an integrated circuit die according to an embodiment of the present invention;
fig. 5 is a diagram of an integrated circuit die based package of the type LQFP32 provided by an embodiment of the present invention.
Embodiments (all) in this section
In order to clearly understand the technical solutions of the present invention, the present invention is further described with reference to the following embodiments, which are only used for the convenience of explaining the technical solutions of the present invention, and the present invention is not limited to the disclosure of the embodiments.
The invention discloses a chip packaging diagram automatic drawing system, which is used for drawing a chip packaging diagram after the chip design is finished, needing to verify the packaging content and drawing the packaging diagram for a user to confirm.
As shown in fig. 1, an automatic drawing system for a chip package diagram includes an integrated information database based on an integrated circuit die, a package type obtaining module, a functional port information obtaining module, a package diagram file generating module, a package diagram drawing module, and a package diagram storing module;
the comprehensive information database comprises the name of each functional port of the integrated circuit bare chip, all use functions corresponding to each functional port, and a plurality of packaging types based on the integrated circuit bare chip, wherein the packaging types comprise packaging modes and the number of pins of the chip, and the comprehensive information database also comprises the connection relationship between each functional port of the integrated circuit bare chip and the pins of the chip of each packaging type;
the package type acquisition module is used for acquiring the package type of a chip needing to be drawn into a package diagram from the comprehensive information database and judging whether the correct package type exists or not;
the function port information acquisition module comprises a name acquisition submodule, an automatic verification submodule and a function acquisition submodule of the function port; the name acquisition submodule is used for acquiring the names of the functional ports correspondingly connected with the pins of the chip in the comprehensive information database and judging whether the pins of the chip are connected with the functional ports or not; the automatic checking submodule is used for confirming the accuracy of the name of the functional port corresponding to each pin of the chip; the function acquisition submodule is used for acquiring all use functions of the function ports connected with the pins of the chip in the comprehensive information database;
the package map file generation module generates a package map file according to the package type, the functional port name corresponding to each pin of the chip and all the use functions of the functional ports; the packaging diagram drawing module automatically draws a chip packaging diagram according to the packaging diagram file;
the packaging drawing module automatically draws a packaging drawing according to the packaging type and the functional port name corresponding to each pin of the chip;
and the package map storage module is used for storing the drawn chip package map.
As shown in fig. 2, based on the automatic drawing system, an automatic drawing process of a chip package diagram is described, which includes the following steps:
(1) Establishing a comprehensive information database based on the integrated circuit bare chip;
generally, an integrated circuit bare chip is provided with a plurality of functional ports, each functional port is named in the step, the use function of the functional port is confirmed, the functional ports are named according to a certain naming rule, the naming rule is determined according to the habit of a designer, for example, the functional port connected with a power supply is named as VCC, and the use function of the functional port is VCC/VSS/EXTEF (power supply pins); for another example, the function port is named as PA12, the using function thereof is ADC9/TMR _ PWM _ OUT/SPIO _ IO1/COMP1_ DOUT _ DIG/UART1, and the functions respectively expressed are: the analog ADC/Timer/bus interface SPI/voltage comparator/serial UART, the specific use function of the function port is not greatly related to the present technical solution, which is not described herein, but it is only clear through the above description that each function port has its own unique name, and each function port can have multiple use functions.
The comprehensive information database comprises the name of each functional port of the integrated circuit bare chip and all the use functions corresponding to each functional port; the integrated information database further includes various package types based on the integrated circuit die, where the package types include a package type and the number of function ports (i.e., the number of chip pins) to be led out, for example, the package type is a chip package type known in the prior art, such as SOP/LQFP/QFN/BGA/DIP, which is not listed here, and it should be understood that the chip package type known in the prior art should be the package type of the present invention; the comprehensive information database also comprises the connection relation between each functional port and the pin of each packaging type chip; the comprehensive information database provides a data source for the subsequent steps; in this embodiment, the comprehensive information database is stored in an excel format, and chip pins of each package type and connection relationships between the chip pins (pin numbers) and the functional ports are conveniently arranged by using the characteristics of the excel.
(2) Obtaining a package type of a chip
The package type in the present invention has been written into the above-mentioned comprehensive information database in advance, the package type is queried through keywords in the package type acquisition module, and the specific implementation manner of this step is described below by taking the package type as SOP16 as an example:
searching a packaging type in the comprehensive information database through keywords, for example, the preset keyword in a program is SOP/LQPF/QFN and the like, and if an "SOP" word is searched in the comprehensive information database (the SOP16 is written in advance), determining that a correct packaging mode is found, determining the found packaging mode as the packaging mode used in the subsequent steps, and simultaneously taking the number "16" behind the "SOP" as the pin number of the chip; if the package type written into the comprehensive information database in advance is wrongly written into the SIP16, the matched package mode cannot be found, and at the moment, error information is prompted and the current step is stopped;
of course, the step (2) may be performed in the following manner: the keywords for searching are set to be the package type (package type + number of pins), such as SOP16/SOP32/LQPF28, and when a matching keyword is found, the package type and the number of pins can be directly determined, and only this keyword is set to be multiple, which may take some time, but can implement the function that the technical solution intends to complete.
In other embodiments, the packaging mode and the number of the functional ports to be led out can be respectively written in the cells at two fixed positions in the comprehensive information database, and at this time, the obtaining mode is to directly obtain the contents of the two fixed cells, so that the method can be easily realized by using a program; of course, the contents of the two cells need to be checked, otherwise, the packaging manner or the number of pins may be wrong, and finally, a correct packaging diagram cannot be drawn;
or, the encapsulation type obtaining module reserves a data input entry, manually inputs the encapsulation mode and the number of the functional ports to be led out at the data input entry, and certainly, the manually input content also needs to be checked, otherwise, the encapsulation mode may be wrong, and finally, a correct encapsulation graph cannot be drawn;
or the package type obtaining module is provided with a window for selecting the package type, and the alternative package types are all the package types stored in the comprehensive information database in advance.
(3) Obtaining the name of each functional port connected with each pin of the chip
Searching the name acquisition submodule of the functional port information acquisition module for the name of the functional port corresponding to the pin of the chip in the packaging type determined in the step (2).
For example, the package type determined in step (2) is SOP16, that is, the number of pins of the chip is determined to be 16, the function port names corresponding to the pins of the SOP16 are recorded in the integrated information database, and the function port names can be obtained by searching the pin numbers of the chip one by one. The packaging type of the SOP16 means that the packaging mode is SOP, and the number of chip pins is 16; the corresponding connection relation between each pin of the chip and the name of the functional port under the packaging type is pin 1-ACC, pin 2-PA 1, \ 8230 \ 8230;, pin 16-PC 0; wherein ACC/PA1/PC0 is the name of the function port; the name of the function port correspondingly connected with the pin can be easily obtained through the number of the pin.
(4) Automatic verification of functional port names
The main purpose of the step is to prevent the wrong lead, the missing lead and the like of the functional port; for example, a functional port is missed, a functional port named VCC needs to be led out from a general chip, and if the functional port is missed, the chip cannot be powered on and cannot work, and the port is prevented from being missed as long as the port is set in an automatic drawing system as an item to be checked; for example, the names of the two functional ports are the same, which is not allowed in practical application; compared with manual verification, automatic verification by adopting an automatic drawing system can be quicker and has higher accuracy
The step is carried out in an automatic check submodule of the functional port information acquisition module, and the step specifically comprises the following steps:
a1, checking a functional port which needs to be checked, and if a checking result is correct, continuing to execute the next step; if the functional port which needs to be checked is not checked, the step is stopped and an error is reported, the comprehensive information database needs to be modified, and the step (2) is executed after the modification;
a2, comparing the names of the led-out functional ports one by one, confirming whether a functional port with a repeated name exists, and if the functional port with the same name is not detected, continuing to execute the next step; if functional ports with the same name are detected, and the functional ports lead out errors, stopping the step and reporting the errors, needing to modify the comprehensive information database, and executing the step (2) after modification;
preferably, the error notification is to prompt what kind of error is in the corresponding error notification (for example, the name of the missing item or the duplicate name, and the notification information may be specific to the name of the missing item or the duplicate functional port), so as to facilitate the modification by the designer.
For example, in the case that the package type is SOP16, the functional port name of the pin connection of the chip acquired in step (3) is: pin 1-PA 0, pin 11-PA 0, and at this time, both pins are connected to the port PA0, and the connection relationship is considered to be an erroneous connection relationship, and the designer needs to re-confirm the design of the chip. If manual confirmation is adopted, the verification personnel can not find the verification result due to carelessness, so that the step ensures the accuracy of the functional port connected with each pin of the chip.
(5) Collecting all use functions of the led-out function ports;
the comprehensive information database pre-stores the use functions corresponding to all the function ports of the integrated circuit bare chip, and the step collects all the used functions of the function ports through the names of the function ports connected with the pins of the chip;
for example, the specific search manner in this step is to search one by one through each function keyword (the function keyword is ADC/TMR/SPIO/COMP/UART/ACC, etc., and is also determined according to the naming rule of the function port), after the name of the function port is confirmed as PA12, the function unit corresponding to the function port PA12 is determined, the function unit of the function port PA12 includes all the use functions of the function port PA12, for example, the use function is ADC9/TMR _ PWM _ OUT/SPIO _ IO1/COMP1_ DOUT _ DIG/UART1, and each use function is respectively stored in one cell. When the keyword "COMP" is used for searching, a corresponding word is found in the functional unit of the functional port PA12, and the content "COMP1_ DOUT _ DIG" of the cell where the word is located is recorded as a function of the PA 12. All the use functions of the function port PA12 can be obtained by searching the keywords one by one (all the keywords are searched once and are also designed in the program in advance); the searching mode of other functional ports is the same.
It should be clear that this is only one embodiment of the present invention, and the present invention may also use other manners to search for the functional port, for example, each function of the functional unit of each functional port is correspondingly stored in a cell at a different fixed position, and the contents of the cell may also be directly obtained.
(6) Generating a package graph file
Generating a packaging diagram file by the packaging diagram file generating module according to the data acquired in the steps, wherein the packaging diagram file comprises the packaging mode and the number of the chip pins confirmed in the step (2), the corresponding relation between the chip pins and the functional ports acquired in the step (3), and all the use functions corresponding to the functional ports collected in the step (5);
the package map file in this step may be an Excel file generated separately; or a Sheet newly added to the Excel file of the integrated information database, preferably, the generated Excel file or the newly added Sheet name is automatically changed to a package type such as "SOP16"; the packaging diagram file provides basis for drawing the packaging diagram in the subsequent steps.
(7) Automatic drawing of package drawings and preservation of package drawings
Automatically drawing a packaging diagram through a packaging diagram drawing module of the automatic drawing system, wherein data on which the packaging diagram is drawn is the generated packaging diagram file in the step (6); preferably, in order to facilitate the use of the drawn package diagram, the drawn package diagram is saved in a jpg format or transferred to word for saving (realized by a package diagram saving module);
in other embodiments, step (6) may not be included, and in this case, the data on which the package diagram is drawn in step (7) is the various data determined in steps (2), (3), and (5); the setting of the step (6) can reserve a basis file for drawing the packaging diagram.
Fig. 3 to 5 are actually drawn packaging diagrams of chips in different application scenarios based on a certain integrated circuit die. The packaging diagram comprises a packaging type, the number of each pin of the chip, the name of a function port correspondingly connected with each pin of the chip and all use functions corresponding to each function port.
For example, in fig. 3, the package type of the chip is SOP28, the numbers of the pins of the chip are 1 to 28, the name of the functional port of the integrated circuit die corresponding to pin 1 of the chip is PA2, and the use functions corresponding to the functional port PA2 are:
ADC3/AMP_VOUT3_RC/TMR4_CAP_PIN2/COMP0_DOUT_DIG/SPI0_IO0/PORT_WKUP_IN1。
the program applied by the automatic drawing system is compiled by adopting an object-oriented programming language, for example, VBA and Excel (mainly used for storing an integrated information database, the package diagram file and the like) adopted in the embodiment are combined to realize automatic drawing of the package diagram.
In other embodiments, other programming language control methods may be used, such as VB/C + + in combination with excel, or other combinations. There is no enumeration here, and it should be understood that all that is required for implementing the functionality of the present invention based on object oriented programming languages known in the art is the subject of the present invention.
According to the embodiment, compared with the manual completion work efficiency, the automatic drawing method of the packaging diagram is high in accuracy, chip development is greatly shortened, and a large amount of labor cost is saved; when the name of the functional port of the integrated circuit bare chip or the function of the functional port is changed or the function of the pin of the chip is changed in the development process, the packaging diagram can be drawn again according to the steps, or the changed pin is only modified and then verified and drawn again, so that the method is convenient and fast, and high in practicability.
The invention also provides a computer system, which comprises a memory and a processor, wherein the memory stores a program used for supporting the automatic drawing method of the chip package diagram, and the processor is configured to execute the program stored in the memory.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (8)
1. An automatic drawing system of a chip packaging diagram is characterized by comprising a comprehensive information database of an integrated circuit bare chip, a packaging type acquisition module, a functional port information acquisition module, a packaging diagram file generation module and a packaging diagram drawing module;
the comprehensive information database comprises the name of each functional port of the integrated circuit bare chip, all use functions corresponding to each functional port and a plurality of packaging types based on the integrated circuit bare chip, wherein the packaging types comprise packaging modes and the number of pins of a chip, and the comprehensive information database also comprises the connection relation between each functional port of the integrated circuit bare chip and the pins of the chip of each packaging type;
the package type acquisition module is used for acquiring the package type of the chip needing to be drawn in the package diagram from the comprehensive information database;
the function port information acquisition module comprises a name acquisition submodule of a function port and a function acquisition submodule, wherein the name acquisition submodule is used for acquiring the corresponding connection relation between the chip pins and the function port and the names of the function ports correspondingly connected with the pins of the chip in the comprehensive information database; the function acquisition submodule is used for acquiring all use functions of the function port connected with each pin of the chip in the comprehensive information database;
the package image file generating module generates a package image file according to the package type, the functional port name corresponding to each pin of the chip and all the use functions of the functional ports;
the packaging drawing module automatically draws a packaging drawing according to the packaging drawing file; the packaging diagram comprises a packaging type, the number of each pin of the chip, the name of a function port correspondingly connected with each pin of the chip and all use functions corresponding to each function port.
2. The automatic drawing system of claim 1, wherein the functional port information obtaining module further includes an automatic check submodule configured to confirm accuracy of names of the functional ports corresponding to the pins of the chip.
3. The automatic drawing system of claim 2, wherein the confirming of the accuracy of the functional port name includes confirming whether each pin of the chip has a missing-function port, and if the missing-function port is found, prompting;
or, the determining the accuracy of the functional port name includes determining whether the functional port corresponding to each pin of the chip has a duplicate name, and if the functional port has the duplicate name, prompting.
4. The automatic drawing system of claim 1, further comprising a package map saving module for saving the drawn chip package map.
5. The automatic drawing system according to any one of claims 1 to 4, wherein the automatic drawing system is programmed by using an object-oriented programming language.
6. The automatic drawing system according to any one of claims 1 to 4, wherein the packaging mode is SOP, LQPF, QFN, BGA or DIP.
7. The automatic drawing system according to any one of claims 1 to 4, wherein the encapsulation type obtaining module is further configured to determine whether a correct encapsulation type exists.
8. A computer system comprising a memory storing a program supporting the automatic drawing system of any one of claims 1 to 7 and a processor configured to execute the program stored in the memory.
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| CN112989744B (en) * | 2021-02-08 | 2023-11-17 | 泰凌微电子(上海)股份有限公司 | Packaging design method and device for semiconductor chip |
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| JPH07160747A (en) * | 1993-12-13 | 1995-06-23 | Nec Corp | Actual chip pin assignment system |
| JP2003297870A (en) * | 2002-04-04 | 2003-10-17 | Mitsubishi Electric Corp | Design support device for semiconductor device |
| CN101063985A (en) * | 2006-04-29 | 2007-10-31 | 英业达股份有限公司 | Wire laying data generating system and method |
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