CN110212912B - Multiple delay phase-locked loop with high-precision time-to-digital converter - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention discloses a multiple delay phase-locked loop with a high-precision time-to-digital converter, which comprises a time-to-digital converter processing module, a digital-to-analog converter, a voltage-controlled oscillator, a frequency divider, a digital control circuit and a data selector, wherein the time-to-digital converter processing module is provided with a coarse-tuning time-to-digital converter, a digital-to-time converter, a subtracter and a pulse reduction time-to-digital converter which are sequentially connected. The invention applies the high-precision time-to-digital converter module to the multiple delay phase-locked loop, and improves the precision of the time-to-digital converter to improve the quantization noise in a sampling-extraction-sampling mode; the pulse reduction type time-to-digital converter can omit the use of a time amplifier and the capture of rising edges and falling edges, directly inputs the phase difference into the pulse reduction type time-to-digital converter for second sampling, does not need to additionally use the time amplifier to amplify the phase difference, and improves the linearity of the time-to-digital conversion module and the input range of the time-to-digital conversion module.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a multiple delay phase-locked loop with a high-precision time-to-digital converter.
Background
Since the multiple delay-locked loop is a module related to the whole chip clock in the chip, many studies are still conducted to reduce jitter (jitter) and low spurs (spurs) of the multiple delay-locked loop to maintain the random error of the whole chip clock within an acceptable reasonable range. In the design of the multiple delay phase locked loop, the jitter generated by the voltage controlled oscillator is accumulated along with the loop, so the multiple delay phase locked loop re-inputs a new clock signal to the oscillator at intervals to reduce the jitter of the oscillator, but after the new clock signal is input, the detected phase difference is the largest, and thus the multiple delay phase locked loop can reduce the jitter, but can also generate a very large spur.
The output jitter of the analog multiple delay phase-locked loop in the early stage is influenced by the nonlinearity caused by the charge pump and the phase discriminator, so the digital multiple delay phase-locked loop tends to be digitalized, and the digital multiple delay phase-locked loop replaces the charge pump and the phase discriminator by the time-to-digital converter to improve the defect of the analog multiple delay phase-locked loop.
In order to improve the noise suppression capability, reference 1(Helal et al, "a high precision Digital MDLL-Based Clock thin drivers a Self-screening Time-to-Digital converter to interference sub-gated converter Performance", IEEE j.solid-statec _ programs, vol.43, No.4, pp.855-863, apr.2008) proposes to use a gated ring oscillator-Based Time-to-Digital converter, which is a high-precision Digital converter That has low quantization noise but consumes a large amount of power.
Reference 2(p.chen et al, "a CMOS Pulse-reducing Delay Element for time Interval Measurement", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.47, No.9, pp.954-958, sep.2000) proposes a Pulse reducing time-to-Digital converter (Pulse reducing TDC) which is one of Vernier time-to-Digital converters (Vernier TDCs) and is also a high precision time-to-Digital converter, which is advantageous in terms of area and power consumption compared to the Vernier time-to-Digital converter, and the deviation generated by the Pulse reducing time-to-Digital converter is also small.
Based on the above, it is necessary to provide a multiple delay phase locked loop with a high precision time-to-digital converter, which improves the precision of the time-to-digital converter to improve the quantization noise and simultaneously improves the linearity of the time-to-digital conversion module and the input range thereof.
Disclosure of Invention
The invention aims to provide a multiple delay phase-locked loop with a high-precision time-to-digital converter, wherein a pulse reduction type time-to-digital converter is used as the high-precision time-to-digital converter to be applied to the multiple delay phase-locked loop; the pulse reduction type time-to-digital converter can simplify the circuit complexity of the time-to-digital converter module; in the conventional two-step time-to-digital converter, a digital signal sampled by the time-to-digital converter is reduced by the digital-to-time converter and then subtracted to obtain a phase difference, then a time amplifier is used for amplifying the phase difference to perform second sampling, and at this time, a rising edge and a falling edge of the phase difference need to be captured before amplification and then input into the time amplifier; the present invention can omit the use of time amplifier and the capture of rising edge and falling edge by using the pulse-reduction time-to-digital converter, and directly input the phase difference to the pulse-reduction time-to-digital converter for the second sampling.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a multiple delay phase-locked loop with a high-precision time-to-digital converter comprises a time-to-digital converter processing module, a digital-to-analog converter, a voltage-controlled oscillator, a frequency divider, a digital control circuit and a data selector, wherein the time-to-digital converter processing module is provided with a coarse tuning time-to-digital converter, a digital time converter, a subtracter and a pulse reduction time-to-digital converter which are sequentially connected; wherein, the coarse tuning time digital converter inputs a reference clock signal of a multiple delay phase-locked loop and an output signal fed back last time of the multiple delay phase-locked loop, converting the time difference between the reference clock signal and the output signal into corresponding digital signal and outputting to the digital-to-time converter to convert the digital signal into time domain signal, the digital-to-time converter outputs the restored time domain signal to the subtracter and subtracts the restored time domain signal from the reference clock signal to obtain a phase difference of the coarse tuning time-to-digital converter, and the subtracter sends the obtained phase difference to the pulse reduction type time-to-digital converter to obtain a pulse output signal, and finally sends the digital signal and the pulse output signal to the digital-to-analog converter to obtain an analog output signal which is used for controlling the frequency of an output signal of a voltage-controlled oscillator connected with the digital-to-analog converter.
Preferably, the analog output signal is a voltage signal.
Preferably, the input range of the coarse time-to-digital converter is larger than the input range of the pulse-reduction time-to-digital converter with the same number of bits.
Preferably, the coarse time to digital converter is a flash time to digital converter.
Preferably, the pulse-reduction-type time-to-digital converter includes:
a delay chain comprising a plurality of buffers, each buffer comprising two inverters with different delays; the input end of the delay chain inputs the phase difference of the subtracter of the previous stage, and the phase difference is gradually reduced through the delay of each stage of buffer in the delay chain until the last stage of buffer is reached;
and the input end of the D-type trigger is connected with the output end of the delay chain, and the D-type trigger collects pulse signals output by each stage of buffer of the delay chain and finally obtains pulse output signals output by the pulse reduction type time-to-digital converter.
Preferably, the formula calculated by the pulse-reduction time-to-digital converter is T ═ N × dt + error, where T represents the phase difference, N represents the number of D-flip-flop outputs of 1, dt is the precision of the pulse-reduction time-to-digital converter, and error is the quantization error of the pulse-reduction time-to-digital converter.
Compared with the prior art, the invention has the beneficial effects that: (1) the high-precision time-to-digital converter module is applied to a multiple delay phase-locked loop, and improves the precision of the time-to-digital converter to improve the quantization noise in a sampling-extraction-sampling mode; (2) the invention can omit the use of a time amplifier and the capture of rising and falling edges by using the pulse reduction type time-to-digital converter, directly inputs the phase difference into the pulse reduction type time-to-digital converter for second sampling, does not need to additionally use the time amplifier to amplify the phase difference, improves the linearity of a time-to-digital conversion module and the input range thereof, and can avoid the nonlinear characteristic caused by using the time amplifier.
Drawings
FIG. 1 is a diagram of a multiple delay PLL architecture with a high precision time-to-digital converter according to the present invention;
FIG. 2 is a schematic diagram of a pulse reduction type time-to-digital converter according to the present invention.
In the figure, 11, a time-to-digital converter processing module; 111. a coarse tuning time-to-digital converter; 112. a digital-to-time converter; 114. a pulse reduction type time-to-digital converter; 12. a digital-to-analog converter; 13. a voltage controlled oscillator; 14. a digital control circuit; 15. a data selector; 16. a frequency divider; 21. a buffer (a buffer composed of two inverters of different delays); a D-type flip-flop.
Detailed Description
The features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of the non-limiting embodiments made with reference to fig. 1-2. The present invention will be described in more detail below with reference to fig. 1-2, which illustrate embodiments of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
As shown in fig. 1-2, the multiple delay phase locked loop with high precision time-to-digital converter according to the present invention comprises a time-to-digital converter processing module 11, a digital-to-analog converter 12, a data selector 15, a voltage-controlled oscillator 13, a frequency divider 16, and a digital control circuit 14.
The time-to-digital converter processing module 11 is connected to the digital-to-analog converter 12, and the digital-to-analog converter 12 is connected to the voltage-controlled oscillator 13. The time-to-digital converter processing module 11 obtains a digital signal of a time difference of signal input through a first sampling in a sampling-extraction-sampling manner, extracts quantization noise on the time-to-digital converter, performs a second sampling on the quantization noise, and outputs a corresponding digital signal to the digital-to-analog converter 12 to obtain an analog output signal (for example, a signal in a voltage form) for adjusting a frequency of an output signal of the voltage-controlled oscillator 13 and reducing an error between the frequency of the output signal of the voltage-controlled oscillator 13 and a frequency of an input reference signal.
The voltage-controlled oscillator 13 outputs to the feedback branch of the time-to-digital converter processing module 11, and the frequency divider 16 is inserted, so as to obtain the frequency-doubling delay phase-locked loop of the invention, wherein the frequency-doubling times are equal to the frequency-dividing times of the frequency divider 16. The advantages of phase-locked frequency multiplication are that the spectral purity is very pure and the frequency multiplication times can be made very high.
As shown in fig. 1, the time-to-digital converter processing module 11 includes a coarse time-to-digital converter 111, a digital-to-time converter 112, a subtractor 113, and a pulse-reduction time-to-digital converter 114, which are connected in sequence.
The multiple delay phase-locked loop of the invention inputs a reference clock signal REF and an output signal OUT, the reference clock signal REF and the output signal OUT are simultaneously input into a coarse time digital converter 111 of a time digital converter processing module 11, the coarse time digital converter 111 converts the time difference input by the reference clock signal REF and the output signal OUT into a digital signal Cout and outputs the digital signal Cout to a digital time converter 112, the digital signal Cout is reduced into a time domain signal, the digital time converter 112 continuously outputs the reduced time domain signal to a subtracter 113 and subtracts the time domain signal Cout from the reference clock signal REF to obtain the phase difference (namely quantization noise) of the coarse time digital converter 111, the subtracter 113 sends the obtained phase difference to a pulse reduction type time digital converter 114 to obtain an output signal PSout, and finally sends the output signal PSout and the output signal PSt to a digital-to-analog converter Coou 12 to obtain an analog output signal DACsum, for controlling the frequency of the output signal OUT of the voltage controlled oscillator 13 (VCO).
Sel in fig. 1 is an input signal of the data selector 15, and is mainly used to determine whether the reference clock signal REF or the output signal OUT is used for the output of the data selector 15. The function of the multiple delay phase-locked loop is to inject a new reference clock signal to the voltage-controlled oscillator 13 in a fixed period, and this mechanism is mainly used to reduce the jitter generated by the whole multiple delay phase-locked loop, because if a new reference clock is not input, the jitter generated by the voltage-controlled oscillator 13 will be accumulated all the time, causing the jitter generated by the whole circuit to be larger and larger. According to the above mechanism, the digital control circuit 14 is mainly used to generate a sel signal to control the data selector 15, and the control data selector 15 determines whether the output is the REF or OUT signal according to the sel signal.
The pulse-reduction-type time-to-digital converter 114 of the present invention mainly determines the precision of the time-to-digital converter processing module 11, and the coarse time-to-digital converter 111 mainly increases the input range of the time-to-digital converter module 11. The precision of the pulse-down-type time-to-digital converter 114 is higher than that of the coarse time-to-digital converter 111, so that the input range of the pulse-down-type time-to-digital converter 114 is smaller than that of the coarse time-to-digital converter 111 when the coarse time-to-digital converter 111 and the pulse-down-type time-to-digital converter 114 have the same number of bits, and therefore the input range of the whole time-to-digital converter processing module 11 is ensured by the coarse time-to-digital converter 111.
Coarse time to digital converter 111 is preferably a flash time to digital converter and thus can be used to increase the input range of the time to digital converter of the multiple delay locked loop of the present invention.
FIG. 2 is a diagram of a pulse-down time-to-digital converter according to the present invention. The pulse reduction time-to-digital converter 114 of the present invention is a high precision time-to-digital converter comprising a delay chain and a D-type flip-flop 22. The delay chain includes multiple stages of buffers 21, each stage of buffer 21 includes two inverters with different delays, and the delays of the two inverters are t1 and t2, respectively. Since td is t1-t2, td is the precision of the pulse reduction time-to-digital converter, the precision required by the present invention can be obtained by designing two inverters in the delay chain. Meanwhile, the delay error caused by the mismatching of the phase inverters is lower than that of a typical vernier time-to-digital converter, and the power consumption and the area consumption are also lower.
As shown in fig. 2, the input signal din of the pulse reduction-type time-to-digital converter 114 is the output pulse of the subtractor 113 composed of an XOR gate at the previous stage, and the output pulse represents the phase difference obtained by the output of the coarse time-to-digital converter 111 being restored by the digital-to-time converter 112 and subtracted from the reference clock signal REF, and also represents the quantization error (i.e., quantization noise) of the coarse time-to-digital converter 111. The delay of the input signal din of the pulse-down time-to-digital converter 114 through each stage of buffer in the delay chain is gradually decreased (for example, PS0> PS1> PS2> … … > PSn), and the resulting pulse down from each stage of buffer is sampled by the D-type flip-flop 22, so as to obtain the digital output signal PSout of the pulse-down time-to-digital converter 114, where PSout refers to a plurality of outputs, namely, PS0, PS1, PS2, … …, and PSn.
The formula calculated by the pulse-reduction time-to-digital converter 114 is T ═ N × dt + error, where T represents the phase difference, N represents the number of D flip-flop outputs of 1, dt represents the accuracy of the pulse-reduction time-to-digital converter 114, and error represents the quantization error of the pulse-reduction time-to-digital converter, and for example, assuming that the input phase difference is approximately 23PS, and the accuracy dt of the pulse-reduction time-to-digital converter 114 is 5PS, it can be known from the formula that N is 4, error is 3PS, that is, it represents that the output PS0-PS3 of the pulse-reduction time-to-digital converter 114 is 1, and the other PS4-PSn is 0, and the quantization error is 3 PS.
To sum up, in the design of the digital multiple delay phase locked loop, the noise mainly comes from the quantization noise of the time-to-digital conversion, the time-to-digital converter processing module in the multiple delay phase locked loop proposed by the present invention improves the precision of the time-to-digital converter to improve the quantization noise by sampling (i.e. the coarse tuning time-to-digital converter 111 converts the time difference between the reference clock signal REF and the output signal OUT into the digital signal Cout) -extracting (i.e. the digital time converter 112 reduces the digital signal Cout into the time domain signal, the digital time converter 112 continuously outputs the reduced time domain signal to the subtractor 113 and subtracts the reference clock signal REF to obtain the phase difference of the coarse tuning time-to-digital converter 111) -sampling (i.e. the phase difference is sent to the pulse-down time-to-digital converter 114 to obtain the output signal PSout), in addition, the invention uses the pulse reduction type time-to-digital converter, does not need to additionally use a time amplifier to amplify the phase difference, increases the linearity of a processing module of the time-to-digital converter, and can enlarge the input range, namely the invention replaces the time amplifier, and can avoid the nonlinear characteristic caused by using the time amplifier.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (6)
1. A multiple delay phase-locked loop with a high-precision time-to-digital converter comprises a time-to-digital converter processing module (11), a digital-to-analog converter (12), a voltage-controlled oscillator (13), a frequency divider (16), a digital control circuit (14) and a data selector (15), and is characterized in that the time-to-digital converter processing module (11) is provided with a coarse-tuning time-to-digital converter (111), a digital-to-time converter (112), a subtracter (113) and a pulse reduction time-to-digital converter (114) which are sequentially connected; the coarse-tuning time digital converter (111) inputs a reference clock signal (REF) with a multiple delay phase-locked loop and an output signal (OUT) fed back last time of the multiple delay phase-locked loop, converts a time difference input by the reference clock signal (REF) and the output signal (OUT) into a corresponding digital signal (Cout) and outputs the digital signal (Cout) to the digital time converter (112), reduces the digital signal (Cout) into a time domain signal, the digital time converter (112) outputs the reduced time domain signal to the subtracter (113) and subtracts the time domain signal from the reference clock signal (REF) to obtain a phase difference of the coarse-tuning time digital converter (111), the subtracter (113) sends the obtained phase difference to the pulse reduction time digital converter (114) to obtain a pulse output signal (PSout), and finally sends the digital signal (Cout) and the pulse output signal (PSout) to the digital-to-analog converter (12) to obtain an analog time digital converter (D/A) -an output signal (DACsum) for controlling the frequency of the output signal of a voltage controlled oscillator (13) connected to the digital to analog converter (12).
2. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1,
the analog output signal is a voltage signal.
3. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1,
the input range of the coarse time-to-digital converter (111) is larger than the input range of the pulse reduction time-to-digital converter (114) under the same number of bits.
4. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1 or 3,
the coarse time-to-digital converter (111) is a flash time-to-digital converter.
5. The multiple delay phase locked loop with high precision time-to-digital converter of claim 1,
the pulse-reduction time-to-digital converter (114) comprises:
a delay chain comprising a plurality of buffers, each buffer comprising two inverters with different delays; the input end of the delay chain inputs the phase difference of the subtracter (113) of the previous stage, and the phase difference is gradually reduced through the delay of each stage of buffer in the delay chain until the last stage of buffer is reached;
and the input end of the D-type flip-flop is connected with the output end of the delay chain, and the D-type flip-flop collects pulse signals output by each stage of buffer of the delay chain and finally obtains pulse output signals (PSout) output by the pulse reduction type time-to-digital converter (114).
6. The multiple delay locked loop with high precision time-to-digital converter of claim 5,
the formula calculated by the pulse reduction time-to-digital converter (114) is T-N-dt + error, wherein T represents the phase difference, N represents the number of D-type flip-flop outputs as 1, dt is the precision of the pulse reduction time-to-digital converter, and error is the quantization error of the pulse reduction time-to-digital converter.
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