CN110188477B - Bit synchronization method for high-speed ADC data transmission - Google Patents
Bit synchronization method for high-speed ADC data transmission Download PDFInfo
- Publication number
- CN110188477B CN110188477B CN201910470499.5A CN201910470499A CN110188477B CN 110188477 B CN110188477 B CN 110188477B CN 201910470499 A CN201910470499 A CN 201910470499A CN 110188477 B CN110188477 B CN 110188477B
- Authority
- CN
- China
- Prior art keywords
- time sequence
- state
- data
- adjusting
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/35—Delay-insensitive circuit design, e.g. asynchronous or self-timed
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a bit synchronization method for high-speed ADC data transmission, and belongs to the technical field of SoC. A phase adjusting circuit, a time sequence detection circuit and a time sequence control circuit are sequentially inserted after the differential circuit is converted into the single-ended circuit; the time sequence state and the state type of the detected signal are fed back through the time sequence detection circuit, and the time delay of the phase adjusting circuit is adjusted through the time sequence control circuit so as to determine the optimal sampling position. The bit synchronization method for high-speed ADC data transmission provided by the invention is online and configurable, can be adjusted in a self-adaptive manner, and can reduce the risk of data transmission errors.
Description
Technical Field
The invention relates to the technical field of SoC, in particular to a bit synchronization method for high-speed ADC data transmission.
Background
With the collaborative development of electronic technology and cross-domain technology, multi-user detection, multi-target capture tracking and other technologies are widely applied, and a multi-channel sampling processing system is more and more important in a modern electronic structure system. In order to meet the system requirements of wider frequency band coverage and higher sensitivity and adapt to the development trend of miniaturization and low power consumption of electronic equipment, a multichannel sampling processing platform designed based on a multichannel high-speed ADC becomes a commonly adopted solution. Source synchronous transmission, which transmits data synchronously with a clock, is widely used in high-speed ADC data paths. Under the condition that the data transmission rate is continuously improved, the effective data window is continuously reduced, and how to acquire correct data at the receiving end becomes a hard requirement for the design of the receiving end interface.
In a high transmission rate multi-channel sampling processing system, the high-speed interface design is influenced by various factors. Taking a system composed of an ADC and an FPGA as an example, signal integrity of a high-speed transmission line is considered in designing a printed circuit board, impedance continuity and crosstalk reduction are considered in laying out and wiring, and wiring rules are considered in the FPGA. At a sending end, the ADC output clock and data may have jitter; on the printed board, high-speed data can generate jitter due to reasons such as wiring in the transmission process; at the receiving end, the relative phase relationship may change when the sampling clock, the frame clock, and the data pass through the internal clock network and the data path, respectively. Although the serial data of each channel of the ADC is strictly guaranteed to be equal to the trace of the sampling clock, stable reception of the data cannot be realized by using a common data interface and deserializing logic. The design of the interface at the receiving end of the ADC becomes the key for determining the performance of the multi-channel processing system.
In order to realize reliable transmission of high-speed data, the verinex corporation Vertex5 series FPGA adopts a chip synchronization technology to ensure data synchronization after a differential signal is converted into a single-ended signal. The chip synchronization technology realizes bit alignment by adjusting IO delay locking optimal sampling positions, and is also called bit synchronization; byte alignment, also known as byte synchronization, is achieved by continuously checking data and adjusting timing through bit sliding. The technology takes the comparison result of received data and a transmitted training sequence as a judgment basis, and the influence of training bytes on the search effect needs to be noticed when the training sequence is set.
Similar problems are encountered in SoC applications, which are considered well in the early design stage. The SoC design is different from the FPGA design, and the design method is quite different. If the ADC and SoC are in SIP package form, jitter may be introduced in the data transmission due to BUMP and wiring. Jitter on the data path is constantly changing under the influence of environmental factors such as power supply voltage, temperature, process, etc.
Disclosure of Invention
The invention aims to provide a bit synchronization method for high-speed ADC data transmission, which has the functions of online configuration, self-adaptive adjustment and capability of reducing the error risk of data transmission.
To solve the above technical problem, the present invention provides a bit synchronization method for high-speed ADC data transmission, including:
a phase adjusting circuit, a time sequence detection circuit and a time sequence control circuit are sequentially inserted after the differential circuit is converted into the single-ended circuit;
the time sequence state and the state type of the detected signal are fed back through the time sequence detection circuit, and the time delay of the phase adjusting circuit is adjusted through the time sequence control circuit so as to determine the optimal sampling position.
Optionally, the phase adjusting circuit is configured to delay the detected signal, and a delay time of the phase adjusting circuit is determined by an adjusting step size and an adjusting value output by the timing control circuit; the product of the maximum adjusting value and the adjusting step length is smaller than the data time width, and the phase adjusting circuit of the clock signal additionally increases the phase locking function.
Optionally, the timing detection circuit samples the clock and the DATA at a stage subsequent to the phase adjustment circuit, and outputs the timing state and the state type according to a phase relationship between the clock CLK and the DATA.
Optionally, the method for detecting the sampling clock and the data of the timing detection circuit includes:
establishing a detection window for the clock CLK, wherein a plurality of detection points exist in the detection window, the middle position of the detection window is set as a main detection point, two sides of the middle position are provided with equal number of side detection points, the left side of the main detection point is a left side detection point, and the right side of the main detection point is a right side detection point; in each detection point position, when the sampled data are all equal, the sequence state is normal; and when the sampled data are not completely equal, selecting the data with the most occurrence times as correct data, wherein the state type is SETUP if the error detection point of the sampled data is a left detection point, and the state type is HOLD if the error detection point of the sampled data is a right detection point.
Optionally, the timing control circuit performs timing search and timing adjustment processes to complete timing control, communicates with the CPU through a universal bus interface, configures basic parameters on line by the CPU, performs timing search and timing adjustment according to a timing state and a state type fed back by the timing detection circuit, and performs phase adjustment by adjusting a clock phase and data delay to ensure an optimal sampling timing.
Optionally, the CPU on-line configuration basic parameters specifically include: the time sequence control circuit is communicated with the CPU through a universal bus interface, the CPU sends configuration information, the time sequence control circuit feeds back state information, so that time sequence searching and a time sequence adjusting process can be matched online, and communication contents comprise control information, state information and searching information:
(a) control information: the CPU can select an adjusting means for adjusting the clock phase or the data delay, select an adjusting direction and a maximum adjusting interval for adjusting the clock phase and the data delay, configure monitoring time for acquiring a time sequence state and a state type, configure an error threshold for reporting an error warning, and shield the time sequence state and the state type;
(b) state information: the time sequence control circuit feeds back the time sequence state and the state type collected in the monitoring time to the CPU;
(c) searching information: the CPU participates in the time sequence searching process, has the starting right of clock phase searching and data delay searching, and has the control right of whether the data channel participates in adjustment.
Optionally, the timing search includes clock phase search and data delay search, the CPU configures whether two search modes are enabled, whether a data channel participates in the timing search process, and when both search modes are enabled, the clock phase search is completed first:
(a) searching the clock phase: the clock phase is located at the middle position of an adjustable range under the default condition, the timing sequence state and the state type of each data path are counted after clock phase searching is carried out, when the timing sequence state is abnormal, the state type of each abnormal state data path is analyzed, when the state type SETUP occupies most, the clock phase is increased by one step length, when the state type HOLD occupies most, the clock phase is decreased by one step length, when the clock state is normal or the clock phase is fixed between two phase jumps, the clock phase searching process is finished, and when the searching process occurs between the two clock phase jumps, the clock phase close to the default clock phase is selected;
(b) data delay searching: the data delay is in the middle position of the adjustable range in the default condition, the time sequence state and the state type of the data delay are analyzed after the data delay search is carried out, when the time sequence state is abnormal, the adjustment is carried out according to the state type, when the state type is SETUP, the data delay is reduced by one step length, when the state type is HOLD, the data delay is increased by one step length, when the time sequence state is normal, the data delay search is ended.
Optionally, the timing adjustment is used for processing a timing state exception occurring after the timing search, and performing the timing adjustment according to control information configured by the CPU; when the abnormal times of the time sequence state exceed the error threshold, the time sequence control circuit reports an error warning to the CPU, and operates according to the adjusting means, the adjusting direction, the maximum adjusting interval and the monitoring time configured by the CPU:
(a) when the adjusting means is a clock phase, the time sequence control circuit counts data channels with abnormal time sequence states and analyzes the state types, selects the state types with more occurrence times, increases or decreases an adjusting value according to the adjusting direction configured by the CPU, collects the time sequence states again after waiting for a period of monitoring time, finishes the adjusting process when the time sequence states are all normal in the maximum adjusting interval, or reports the time sequence states to the CPU;
(b) when the adjusting means is data delay, the time sequence control circuit increases or decreases the adjusting value according to the feedback state type and the configured adjusting direction, waits for a period of monitoring time, acquires the time sequence state again, finishes the adjusting process when the time sequence state is normal in the maximum adjusting interval, and reports the time sequence state to the CPU if the time sequence state is normal;
the monitoring time is realized by a counter and is determined by the working frequency of the circuit and the configured register value of the monitoring time.
The invention provides a bit synchronization method for high-speed ADC data transmission, which is characterized in that a phase adjusting circuit, a time sequence detection circuit and a time sequence control circuit are sequentially inserted after a differential-to-single-ended circuit is converted; the time sequence state and the state type of the detected signal are fed back through the time sequence detection circuit, and the time delay of the phase adjusting circuit is adjusted through the time sequence control circuit so as to determine the optimal sampling position.
The invention has the following beneficial effects:
(1) the timing state is reflected by using the SETUP/HOLD violation caused by the error of the phase relation between data and a clock, and the timing control circuit carries out self-adaptive adjustment according to the phase change relation to realize bit synchronization;
(2) the control process is enabled to be online and configurable through the communication between the universal bus interface and the CPU, and the adjustment process is controlled in a software and hardware cooperation mode.
Drawings
FIG. 1 is a general schematic diagram of a bit synchronization method for high-speed ADC data transmission according to the present invention;
FIG. 2 is a schematic diagram of the detection method of the timing detection circuit.
Detailed Description
The bit synchronization method for high-speed ADC data transmission according to the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The present invention provides a bit synchronization method for high speed ADC DATA transmission, as shown in fig. 1, the signal output by the ADC includes clock CLK, DATA (including DATA N0, …, DATA Nn, representing N DATA signals that can be sampled by clock CLK, where FCO signal is treated as one of DATA). A phase adjusting circuit, a time sequence detection circuit and a time sequence control circuit are sequentially inserted after the differential circuit is converted into the single-ended circuit; the time sequence control circuit adjusts the time delay of the phase adjusting circuit according to the time sequence state and the state type fed back by the time sequence detecting circuit so as to determine the optimal sampling position.
Specifically, the phase adjusting circuit is used for delaying the detected signal, and the delay time of the phase adjusting circuit is determined by an adjusting step length and an adjusting value output by the timing control circuit; the product of the maximum adjusting value and the adjusting step length is smaller than the data time width, and the phase adjusting circuit of the clock signal additionally increases the phase locking function.
Please refer to fig. 2, which is a schematic diagram of the method for detecting the sampling clock and data of the timing detecting circuit. The timing sequence detection circuit samples clock and DATA at the stage after the phase adjustment circuit, and outputs a timing sequence state and a state type according to the phase relation of the clock CLK and the DATA DATA, and the detection method comprises the following steps: establishing a detection window for the clock CLK, wherein a plurality of detection points exist in the detection window, the middle position of the detection window is set as a main detection point, two sides of the middle position are provided with equal number of side detection points, the left side of the main detection point is a left side detection point, and the right side of the main detection point is a right side detection point; in each detection point position, when the sampled data are all equal, the sequence state is normal; and when the sampled data are not completely equal, selecting the data with the most occurrence times as correct data, wherein the state type is SETUP if the error detection point of the sampled data is a left detection point, and the state type is HOLD if the error detection point of the sampled data is a right detection point. Under the condition of meeting the requirements of design detection precision and adjustment time, in order to simplify the design, a coarse-grained detection method is adopted, and 3 detection points, namely a main detection point, a left detection point and a right detection point, are arranged in a detection window.
The time sequence control circuit finishes time sequence control through time sequence searching and time sequence adjusting processes, can be communicated with a CPU through a universal bus interface, and is used for configuring basic parameters on line by the CPU, carrying out time sequence searching and time sequence adjusting according to a time sequence state and a state type fed back by the time sequence detection circuit, and carrying out phase adjustment through adjusting clock phases and data delay, thereby ensuring the optimal sampling time sequence.
Specifically, the CPU on-line configuration basic parameters specifically include: the time sequence control circuit is communicated with the CPU through a universal bus interface, the CPU sends configuration information, the time sequence control circuit feeds back state information, so that time sequence searching and a time sequence adjusting process can be matched online, and communication contents comprise control information, state information and searching information:
(a) control information: the CPU can select an adjusting means for adjusting the clock phase or the data delay, can select the adjusting direction and the maximum adjusting interval for adjusting the clock phase and the data delay, can configure the monitoring time for acquiring the time sequence state and the state type, and can configure the error threshold for reporting error warning and can shield the time sequence state and the state type;
(b) state information: the time sequence control circuit feeds back the time sequence state and the state type collected in the monitoring time to the CPU;
(c) searching information: the CPU can participate in the time sequence searching process, has the starting right of clock phase searching and data delay searching, and has the control right of whether the data channel participates in adjustment.
The time sequence search comprises clock phase search and data delay search, a CPU configures whether two search modes are started or not, a data channel participates in the time sequence search process, and when the two search modes are all started, the clock phase search is completed firstly:
(a) searching the clock phase: the clock phase is located in the middle position of an adjustable range under the default condition, after clock phase searching is carried out, the timing sequence state and the state type of each data path are counted, when the timing sequence state is abnormal, the state type of each abnormal state data path is analyzed, when the state type SETUP occupies most, the clock phase is increased by one step length, when the state type HOLD occupies most, the clock phase is reduced by one step length, when the clock state is normal or the clock phase is fixed between two phase jumps, the clock phase searching process is finished, and when the searching process occurs between the two clock phase jumps, the clock phase close to the default clock phase is selected;
(b) data delay searching: the data delay is in the middle position of the adjustable range in the default condition, the time sequence state and the state type of the data delay are analyzed after the data delay search is carried out, when the time sequence state is abnormal, the adjustment is carried out according to the state type, when the state type is SETUP, the data delay is reduced by one step length, when the state type is HOLD, the data delay is increased by one step length, when the time sequence state is normal, the data delay search is ended.
The time sequence adjustment is used for processing the time sequence state abnormity appearing after the time sequence search and carrying out time sequence adjustment according to the control information configured by the CPU; when the time sequence state abnormal frequency exceeds the error threshold value, the time sequence control circuit reports an error warning to the CPU and operates according to the adjusting means, the adjusting direction, the maximum adjusting interval and the monitoring time configured by the CPU:
(a) when the adjusting means is a clock phase, the time sequence control circuit counts data channels with abnormal time sequence states and analyzes the state types, selects the state types with more occurrence times, increases or decreases an adjusting value according to the adjusting direction configured by the CPU, collects the time sequence states again after waiting for a period of monitoring time, finishes the adjusting process when the time sequence states are all normal in the maximum adjusting interval, or reports the time sequence states to the CPU;
(b) when the adjusting means is data delay, the time sequence control circuit increases or decreases the adjusting value according to the feedback state type and the configured adjusting direction, after waiting for a period of monitoring time, the time sequence state is collected again, if the time sequence state is normal in the maximum adjusting interval, the adjusting process is ended, otherwise, the time sequence state is reported to the CPU;
the monitoring time is realized by a counter and is determined by the working frequency of the circuit and the configured register value of the monitoring time.
The bit synchronization method for high-speed ADC data transmission is applied to actual measurement:
the bit synchronization method for high-speed ADC data transmission is applied to an SoC circuit based on a Power PC architecture. The SoC circuit is communicated with the on-chip peripherals based on a local bus, an ADC is configured through an SPI interface, and a multichannel ADC receiving end designed based on the bit synchronization method is used for receiving 800Mbps data. In the design stage, a simulation verification platform based on the SoC verifies a multi-channel ADC receiving end, applies fixed or random DATA to perform function simulation, and applies the phase relation between the fixed or random DATA and the CLK to perform performance simulation. The SoC circuit adopts a 55nm eflash process, and the whole package adopts a SiP package form. Through practical tests, the multichannel ADC receiving end can normally work under a three-temperature experiment, and adaptive adjustment of data and clock phases can be realized.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (4)
1. A bit synchronization method for high-speed ADC data transmission, comprising:
a phase adjusting circuit, a time sequence detection circuit and a time sequence control circuit are sequentially inserted after the differential circuit is converted into the single-ended circuit;
the time sequence state and the state type of the detected signal are fed back through the time sequence detection circuit, and the time delay of the phase adjusting circuit is adjusted through the time sequence control circuit so as to determine the optimal sampling position;
the phase adjusting circuit is used for delaying the detected signal, and the delay time of the phase adjusting circuit is determined by an adjusting step length and an adjusting value output by the time sequence control circuit; the product of the maximum adjusting value and the adjusting step length is smaller than the data time width, and a phase adjusting circuit of the clock signal additionally increases a phase locking function;
the timing sequence detection circuit samples clock and DATA at the stage after the phase adjustment circuit and outputs a timing sequence state and a state type according to the phase relation of the clock CLK and the DATA DATA;
the detection method of the time sequence detection circuit sampling clock and data comprises the following steps: establishing a detection window for the clock CLK, wherein a plurality of detection points exist in the detection window, the middle position of the detection window is set as a main detection point, two sides of the middle position are provided with equal number of side detection points, the left side of the main detection point is a left side detection point, and the right side of the main detection point is a right side detection point; in each detection point position, when the sampled data are all equal, the sequence state is normal; and when the sampled data are not completely equal, selecting the data with the most occurrence times as correct data, wherein the state type is SETUP if the error detection point of the sampled data is a left detection point, and the state type is HOLD if the error detection point of the sampled data is a right detection point.
2. The bit synchronization method for high-speed ADC data transmission according to claim 1, wherein the timing control circuit performs timing control through the processes of timing search and timing adjustment, communicates with the CPU through a universal bus interface, configures basic parameters on line by the CPU, performs timing search and timing adjustment according to the timing state and state type fed back by the timing detection circuit, performs phase adjustment by adjusting clock phase and data delay, and ensures an optimal sampling timing:
the CPU on-line configuration basic parameters specifically comprise: the time sequence control circuit is communicated with the CPU through a universal bus interface, the CPU sends configuration information, the time sequence control circuit feeds back state information, so that time sequence searching and a time sequence adjusting process can be matched online, and communication contents comprise control information, state information and searching information: (a) control information: the CPU can select an adjusting means for adjusting the clock phase or the data delay, select an adjusting direction and a maximum adjusting interval for adjusting the clock phase and the data delay, configure monitoring time for acquiring a time sequence state and a state type, configure an error threshold for reporting an error warning, and shield the time sequence state and the state type;
(b) state information: the time sequence control circuit feeds back the time sequence state and the state type collected in the monitoring time to the CPU;
(c) searching information: the CPU participates in the time sequence searching process, has the starting right of clock phase searching and data delay searching, and has the control right of whether the data channel participates in adjustment.
3. The bit synchronization method for high-speed ADC data transmission according to claim 2, wherein the timing search comprises a clock phase search and a data delay search, the CPU configures whether two search modes are enabled, whether the data channel participates in the timing search process, and when the two search modes are enabled, the clock phase search is firstly completed:
(a) searching the clock phase: the clock phase is located at the middle position of an adjustable range under the default condition, the timing sequence state and the state type of each data path are counted after clock phase searching is carried out, when the timing sequence state is abnormal, the state type of each abnormal state data path is analyzed, when the state type SETUP occupies most, the clock phase is increased by one step length, when the state type HOLD occupies most, the clock phase is decreased by one step length, when the clock state is normal or the clock phase is fixed between two phase jumps, the clock phase searching process is finished, and when the searching process occurs between the two clock phase jumps, the clock phase close to the default clock phase is selected;
(b) data delay searching: the data delay is in the middle position of the adjustable range in the default condition, the time sequence state and the state type of the data delay are analyzed after the data delay search is carried out, when the time sequence state is abnormal, the adjustment is carried out according to the state type, when the state type is SETUP, the data delay is reduced by one step length, when the state type is HOLD, the data delay is increased by one step length, when the time sequence state is normal, the data delay search is ended.
4. The bit synchronization method for high-speed ADC data transmission according to claim 3, wherein the timing adjustment is used for processing the abnormal timing state after the timing search, and the timing adjustment is performed according to the control information configured by the CPU; when the abnormal times of the time sequence state exceed the error threshold, the time sequence control circuit reports an error warning to the CPU, and operates according to the adjusting means, the adjusting direction, the maximum adjusting interval and the monitoring time configured by the CPU:
(a) when the adjusting means is a clock phase, the time sequence control circuit counts data channels with abnormal time sequence states and analyzes the state types, selects the state type with the most occurrence times, increases or decreases an adjusting value according to the adjusting direction configured by the CPU, collects the time sequence state again after waiting for a period of monitoring time, finishes the adjusting process when the time sequence states are all normal in the maximum adjusting interval, or reports the time sequence states to the CPU;
(b) when the adjusting means is data delay, the time sequence control circuit increases or decreases the adjusting value according to the feedback state type and the configured adjusting direction, after waiting for a period of monitoring time, the time sequence state is collected again, if the time sequence state is normal in the maximum adjusting interval, the adjusting process is ended, otherwise, the time sequence state is reported to the CPU;
the monitoring time is realized by a counter and is determined by the working frequency of the circuit and the configured register value of the monitoring time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910470499.5A CN110188477B (en) | 2019-05-31 | 2019-05-31 | Bit synchronization method for high-speed ADC data transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910470499.5A CN110188477B (en) | 2019-05-31 | 2019-05-31 | Bit synchronization method for high-speed ADC data transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110188477A CN110188477A (en) | 2019-08-30 |
| CN110188477B true CN110188477B (en) | 2022-08-02 |
Family
ID=67719530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910470499.5A Active CN110188477B (en) | 2019-05-31 | 2019-05-31 | Bit synchronization method for high-speed ADC data transmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110188477B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112558018B (en) * | 2020-12-08 | 2021-09-03 | 深圳市虹远通信有限责任公司 | Method, processor and system for aligning clock and pulse per second between multiple systems with high precision |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101951313A (en) * | 2010-09-08 | 2011-01-19 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN101989466A (en) * | 2009-08-03 | 2011-03-23 | 凌阳科技股份有限公司 | Device and method for data interception and time sequence drifting detection of interface of synchronous dynamic random access memory |
| CN104378114A (en) * | 2014-10-23 | 2015-02-25 | 西安电子科技大学 | Method for achieving synchronization of multichannel analog-digital converter |
| CN109600560A (en) * | 2018-12-04 | 2019-04-09 | 中国航空工业集团公司洛阳电光设备研究所 | Cmos image sensor exports high speed serialization LVDS signal calibration method and device |
-
2019
- 2019-05-31 CN CN201910470499.5A patent/CN110188477B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989466A (en) * | 2009-08-03 | 2011-03-23 | 凌阳科技股份有限公司 | Device and method for data interception and time sequence drifting detection of interface of synchronous dynamic random access memory |
| CN101951313A (en) * | 2010-09-08 | 2011-01-19 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN104378114A (en) * | 2014-10-23 | 2015-02-25 | 西安电子科技大学 | Method for achieving synchronization of multichannel analog-digital converter |
| CN109600560A (en) * | 2018-12-04 | 2019-04-09 | 中国航空工业集团公司洛阳电光设备研究所 | Cmos image sensor exports high speed serialization LVDS signal calibration method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110188477A (en) | 2019-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9059816B1 (en) | Control loop management and differential delay correction for vector signaling code communications links | |
| EP2321662B1 (en) | Tracker circuit and method for automated test equipment systems | |
| US6904375B1 (en) | Method and circuits for testing high speed devices using low speed ATE testers | |
| US9577818B2 (en) | High speed data transfer using calibrated, single-clock source synchronous serializer-deserializer protocol | |
| TWI681652B (en) | Interface circuit, signal transmission system and signal transmission method thereof | |
| US10797984B1 (en) | Systems and methods for timestamping a data event | |
| CN101119185B (en) | Automatic equalizer and digital eye pattern detecting unit and method | |
| CN110188477B (en) | Bit synchronization method for high-speed ADC data transmission | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| US9015541B2 (en) | Device and method for performing timing analysis | |
| US20080170610A1 (en) | High Speed Serial Test Circuits | |
| US6857089B2 (en) | Differential receiver architecture | |
| CN106961337B (en) | Network connection device and line detection method | |
| US11178036B2 (en) | Systems and methods for measuring latency in a network device | |
| US10680792B1 (en) | Systems and methods for timing a signal | |
| WO2023147732A1 (en) | Timing calibration method and system | |
| US20230006903A1 (en) | Systems and methods for timing a signal | |
| US5436927A (en) | Method and apparatus for testing frequency symmetry of digital signals | |
| US9435840B2 (en) | Determining worst-case bit patterns based upon data-dependent jitter | |
| CN103941105A (en) | Time series analyzing device and time series analyzing method | |
| CN112306943B (en) | Idelay real-time adjustment method based on FPGA high-speed SerDes | |
| Iles | Performance and lessons of the CMS global calorimeter trigger | |
| WO2023087510A1 (en) | Analog measurement apparatus and measurement method based on digital tdr technology | |
| WO2018017292A1 (en) | Apparatus and method for centering clock signal in cumulative data eye of parallel data in clock forwarded links | |
| Yang et al. | High-precision channel synchronization design of PXIe digital integrated circuit test system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |