CN109920454B - Single-end operated sensitive amplifier - Google Patents
Single-end operated sensitive amplifier Download PDFInfo
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- CN109920454B CN109920454B CN201910231209.1A CN201910231209A CN109920454B CN 109920454 B CN109920454 B CN 109920454B CN 201910231209 A CN201910231209 A CN 201910231209A CN 109920454 B CN109920454 B CN 109920454B
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Abstract
The invention discloses a single-end operated sensitive amplifier.A first input end of an amplifier main body circuit is connected with a reference voltage, a second input end of the amplifier main body circuit is connected with a data line, and a comparison signal is output at an output end; the data line is connected with the storage unit, the reference voltage is output by the reference bias network circuit, and the data voltage is input into the reference bias network circuit and dynamically adjusts the reference voltage; in the read 0 operation, the data line discharges through the memory cell and gradually decreases the data voltage, the gradually decreasing data voltage gradually increases the reference voltage, and the read window in the read 0 operation is increased by the increasing reference voltage. The invention can improve the reading window, improve the reading speed and reduce the dynamic power consumption.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a single-ended operation (single-ended operation) Sense Amplifier (SA).
Background
As shown in fig. 1, the structure of a conventional single-ended sense amplifier is schematically illustrated, and the sense amplifier, SA, is also generally translated into a sense amplifier; the SA101 includes two input terminals, a first input terminal is connected to the reference voltage Vref, and a second input terminal is connected to the data voltage DL. The Reference Voltage Vref is provided by a Reference Voltage level network (Reference Voltage level network)102, and the data Voltage DL is provided by a data line (data line) connected to a memory array of the memory, and the data Voltage DL reflects information stored in a memory cell in the memory array during a reading process. In the prior art, the reference voltage Vref is fixed, that is, the reference voltage Vref is fixed during the reading process. The curves of the reference voltage Vref and the data voltage DL are also shown in fig. 1, where the curve 201 corresponds to the curve of the data voltage DL in the read 1 operation, the curve 202 corresponds to the curve of the reference voltage Vref, and the curve 203 corresponds to the curve of the data voltage DL in the read 0 operation. It can be seen that, in the read 1 operation, the data voltage DL is kept at a high level, the data voltage DL is greater than the reference voltage Vref, and the difference between the two voltages is dv 201; in the read 0 operation, the data voltage DL is discharged to a low level, and finally the data voltage DL is smaller than the reference voltage Vref and the voltage difference between the two is dv 202.
In order to obtain a sufficient read window (read margin), dv201 and dv202 need to be enlarged, which makes the low level requirement of the data voltage DL after discharging low enough to ensure the normal read 1 operation and read 0 operation. The increased discharge amount of the data voltage DL reduces the read rate and increases the dynamic power consumption.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a single-ended sense amplifier, which can improve the read window, improve the read rate and reduce the dynamic power consumption.
In order to solve the above technical problem, the single-ended sense amplifier provided in the present invention includes an amplifier main circuit, wherein a first input terminal of the amplifier main circuit is connected to a reference voltage and a second input terminal of the amplifier main circuit is connected to a data line, and an output terminal of the amplifier main circuit outputs a comparison signal between the reference voltage and a data voltage of the data line.
The data line is connected with the storage unit, the reference voltage is output by the output end of the reference bias network circuit, and the data voltage is input into the reference bias network circuit and dynamically adjusts the reference voltage.
Before a read operation, the data voltage is precharged to a first high level, and the reference voltage is preset to a first low level.
The read operation when the information stored in the memory cell is 0 is a read 0 operation, in the read 0 operation, the data line is discharged through the memory cell and the data voltage is gradually reduced from a first high level to a second low level, the second low level is lower than the first low level, the reference voltage is gradually increased to a second high level by the gradually reduced data voltage, the second high level is lower than the first high level, a read window in the read 0 operation is increased by the increased reference voltage, and the read window is a difference value between the reference voltage and the data voltage.
In a further improvement, the read operation when the information stored in the memory cell is 1 is a read 1 operation, in the read 1 operation, the data voltage is maintained at the first high level, the data voltage at the first high level maintains the reference voltage at the first low level, and a read window in the read 1 operation is maintained or increased.
In a further improvement, the amplifier main body circuit comprises a first CMOS circuit formed by connecting a first NMOS transistor and a first PMOS transistor and a second CMOS circuit formed by connecting a second NMOS transistor and a second PMOS transistor, wherein an input terminal of the first CMOS circuit and an output terminal of the second CMOS circuit are both connected to a first node, and an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit are both connected to a second node.
In a further improvement, the first input terminal of the amplifier main body circuit is connected to the reference voltage through a first transmission gate.
And the second input end of the amplifier main body circuit is connected with the reference voltage through a second transmission gate.
In a further improvement, the first transmission gate and the second transmission gate are both CMOS transmission gates.
The positive phase control end of the first transmission gate is connected with a first control signal, and the negative phase control end of the first transmission gate is connected with the negative phase signal of the first control signal; the positive phase control end of the second transmission gate is connected with the first control signal, and the negative phase control end of the second transmission gate is connected with the negative phase signal of the first control signal.
In a further improvement, the reference bias network circuit comprises a comparison circuit composed of a pull-up current source and a pull-down current source, wherein the pull-up current source and the pull-down current source are connected at a third node and form an output end for outputting the reference voltage.
And the control end of the pull-down current source is connected with the data line, and in the reading process, when the data voltage is reduced, the current of the pull-down current source is reduced and the reference voltage is increased, so that the reference voltage is gradually increased in the read 0 operation and is kept in the read 1 operation.
The further improvement is that the pull-up current source is formed by connecting a plurality of pull-up current branches in parallel, and the size of the pull-up current source is adjusted by performing combined control on each pull-up current branch.
In a further improvement, the pull-down current source comprises a first pull-down current branch and a second pull-down current branch, and the magnitude of the current of the second pull-down current branch is controlled by the data voltage.
In a further improvement, the second pull-down current branch includes a plurality of pull-down current sub-branches, a current level of each of the pull-down current sub-branches is controlled by the data voltage, and the current level of the second pull-down current branch is adjusted by performing combined control on each of the pull-down current sub-branches.
In a further improvement, during reading, the first pull-down current branch is turned off, and the second pull-down current branch is turned on; in the pre-charging process, the first pull-down current branch is conducted, and the second pull-down current branch is cut off.
In a further development, the switching on and off of the first pull-down current branch and the second pull-down current branch is controlled by a first digital circuit.
In a further improvement, the second pull-down current branch comprises two pull-down current sub-branches, namely a first pull-down current sub-branch and a second pull-down current sub-branch.
The first pull-down electronic branch comprises a third NMOS transistor, a fourth NMOS transistor and a third transmission gate.
The second pull-down current sub-branch comprises a fifth NMOS tube, a sixth NMOS tube and a fourth transmission gate.
The drain electrode of the third NMOS tube and the drain electrode of the fifth NMOS tube are both connected with the third node, and the source electrode of the third NMOS tube and the source electrode of the fifth NMOS tube are both connected with the drain electrode of the seventh NMOS tube.
The data voltage is connected to the grid electrode of the third NMOS tube through the third transmission gate, and the data voltage is connected to the grid electrode of the fifth NMOS tube through the fourth transmission gate.
The drain electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the drain electrode of the sixth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the source electrode of the sixth NMOS tube is grounded, and the source electrode of the seventh NMOS tube is grounded.
The positive phase control end of the third transmission gate is connected with the reverse phase signal of the second control signal, the reverse phase control end of the third transmission gate is connected with the second control signal, and the grid electrode of the fourth NMOS tube is connected with the second control signal.
The positive phase control end of the fourth transmission gate is connected with the inverted signal of the third control signal, the inverted control end of the fourth transmission gate is connected with the third control signal, and the grid electrode of the sixth NMOS tube is connected with the third control signal.
And the grid electrode of the seventh NMOS tube is connected with a pre-charge control signal.
In a further improvement, the first pull-down current branch comprises an eighth NMOS transistor.
The drain electrode of the eighth NMOS tube is connected with the third node, the source electrode of the eighth NMOS tube is grounded, and the grid electrode of the eighth NMOS tube is connected with the output end of the first digital circuit.
The first digital circuit includes a first inverter, a nand gate, and an exclusive nor gate.
The second control signal and the third control signal are connected to two input ends of the nand gate.
The precharge control signal is connected to an input terminal of the first inverter.
The output end of the first inverter and the output end of the NAND gate are respectively connected to two input ends of the XNOR gate, and the output end of the XNOR gate is used as the output end of the first digital circuit.
In a further improvement, the amplifier main body circuit further comprises a pre-charge circuit, and the pre-charge circuit comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor.
And the source electrode of the third PMOS tube is connected with a power supply voltage, and the drain electrode of the third PMOS tube is connected with the second node.
And the source electrode of the fourth PMOS tube is connected with a power supply voltage, and the drain electrode of the fourth PMOS tube is connected with the first node.
The source electrode of the fifth PMOS tube is connected with the first node, and the drain electrode of the fourth PMOS tube is connected with the second node.
The grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube are all connected with a pre-charging control signal.
In a further improvement, the amplifier main body circuit further comprises an enable circuit, the enable circuit comprises a ninth NMOS transistor, a drain of the ninth NMOS transistor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, the source of the ninth NMOS transistor is grounded, and a gate of the ninth NMOS transistor is connected to an enable signal.
The invention carries on the pointed setting to the reference bias network circuit which provides the reference voltage, sets the reference voltage as the dynamic change according to the data voltage, mainly in reading 0 operation, the reference voltage will increase gradually when the data voltage decreases gradually, in this way, can increase reading 0 operation reference voltage and data voltage between the voltage difference, so does not need to reduce the data voltage after the voltage discharge to increase the reference voltage and data voltage between the voltage difference, so the invention can improve the reading window; the invention can reduce the discharge of data voltage in the 0 reading operation, thereby improving the reading speed and reducing the dynamic power consumption.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art single-ended sense amplifier;
FIG. 2 is a circuit diagram of a sense amplifier with single-ended operation according to an embodiment of the present invention;
FIG. 3 is a signal curve of a sense amplifier operating single-ended according to an embodiment of the present invention during a read process.
Detailed Description
Fig. 2 is a circuit diagram of a sense amplifier with single-ended operation according to an embodiment of the present invention, and fig. 3 is a signal curve of the sense amplifier with single-ended operation according to the embodiment of the present invention during a reading process, the sense amplifier with single-ended operation according to the embodiment of the present invention includes an amplifier main circuit 1, a first input terminal of the amplifier main circuit 1 is connected to a reference voltage Vref, a second input terminal of the amplifier main circuit is connected to a data line, and an output terminal of the amplifier main circuit 1 outputs a comparison signal between the reference voltage Vref and a data voltage DL of the data line.
The data line is connected with the storage unit, the reference voltage Vref is output from the output end of the reference bias network circuit 2, and the data voltage DL is input to the reference bias network circuit 2 and dynamically adjusts the reference voltage Vref.
Before a read operation, the data voltage DL is precharged to a first high level, and the reference voltage Vref is preset to a first low level.
The read operation when the information stored in the memory cell is 0 is a read 0 operation, and in the read 0 operation, as shown by a curve 303 in fig. 3, the data line discharges through the memory cell and gradually decreases the data voltage DL from a first high level to a second low level, where the second low level is lower than the first low level; as shown in a curve 304 of fig. 3, the gradually decreasing data voltage DL may gradually increase the reference voltage Vref to a second high level, which is lower than the first high level, and the read window in the read 0 operation, which is the difference between the reference voltage Vref and the data voltage DL, is increased by the increasing reference voltage Vref. In fig. 3, the read window in the read 0 operation is the sum of dv300 and dv300a, where dv300 is the corresponding voltage difference between curve 302 and curve 303, which is equivalent to dv202 in fig. 1 where the reference voltage is a fixed value; dv300a is an increased value of the voltage difference between the reference voltage Vref and the data voltage DL after the reference voltage Vref increases with the data voltage DL. That is, the present invention can increase the read window of dv300a in a read 0 operation relative to the prior art.
The read operation when the information stored in the memory cell is 1 is a read 1 operation, in the read 1 operation, as shown by a curve 301 in fig. 3, the data voltage DL is maintained at the first high level, the data voltage DL at the first high level maintains the reference voltage Vref at the first low level, a read window in the read 1 operation is maintained or increased, and the read window in the read 1 operation is determined by a voltage difference dv301 between the curve 301 and the curve 302.
Preferably, the amplifier main body circuit 1 comprises a first CMOS circuit formed by a first NMOS transistor MN1 and a first PMOS transistor MP1 connected and a second CMOS circuit formed by a second NMOS transistor MN2 and a second PMOS transistor MP2 connected, wherein an input terminal of the first CMOS circuit and an output terminal of the second CMOS circuit are both connected to the first node OUT1, and an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit are both connected to the second node OUT 2.
The first input terminal of the amplifier body circuit 1 is connected to the reference voltage Vref through a first transmission gate PG 1.
The second input terminal of the amplifier main body circuit 1 is connected to the reference voltage Vref through a second pass gate PG 2.
The first and second pass gates PG1 and PG2 are CMOS pass gates.
A non-inverting control terminal of the first transmission gate PG1 is connected to a first control signal SAPG, and an inverting control terminal of the first transmission gate PG1 is connected to an inverting signal zsubapg of the first control signal SAPG; a non-inverting control terminal of the second pass gate PG2 is connected to the first control signal SAPG, and an inverting control terminal of the second pass gate PG2 is connected to the inverting signal zsubapg of the first control signal SAPG.
The reference bias network circuit 2 comprises a comparison circuit composed of a pull-up current source 3 and a pull-down current source 4, wherein the pull-up current source 3 and the pull-down current source 4 are connected at a third node and form an output end for outputting the reference voltage Vref.
The control terminal of the pull-down current source 4 is connected to the data line, and during the reading process, when the data voltage DL decreases, the current of the pull-down current source 4 decreases and the reference voltage Vref increases, so that the reference voltage Vref is gradually increased in the read 0 operation and the reference voltage Vref is maintained in the read 1 operation.
The pull-up current source 3 is formed by connecting a plurality of pull-up current branches in parallel, and the size of the pull-up current source 3 is adjusted by performing combined control on each pull-up current branch. As shown in fig. 3, the pull-up current source 3 is formed by connecting 4 pull-up current branches in parallel, the first pull-up current branch is formed by connecting PMOS transistors MP6 and MP7 in series, the second pull-up current branch is formed by connecting PMOS transistors MP8, the third pull-up current branch is formed by connecting PMOS transistors MP9, and the fourth pull-up current branch is formed by connecting PMOS transistors MP10 and MP11 in series. The gates of the PMOS transistors MP6 and MP8 are controlled by a control signal OP1, and the gates of the PMOS transistors MP9 and MP10 are controlled by a control signal OP1 after being inverted by an inverter 13. The gates of the PMOS transistors MP7 and MP11 are controlled by a control signal OP 2.
The pull-down current source 4 includes a first pull-down current branch 5 and a second pull-down current branch 6, and a current magnitude of the second pull-down current branch 6 is controlled by the data voltage DL.
The second pull-down current branch 6 includes a plurality of pull-down current sub-branches, the magnitude of the current of each of the pull-down current sub-branches is controlled by the data voltage DL, and the magnitude of the current of the second pull-down current branch 6 is adjusted by performing combined control on each of the pull-down current sub-branches.
During reading, the first pull-down current branch 5 is turned off, and the second pull-down current branch 6 is turned on; during the precharging process, the first pull-down current branch 5 is switched on, and the second pull-down current branch 6 is switched off.
The switching on and off of the first pull-down current branch 5 and the second pull-down current branch 6 is controlled by a first digital circuit 7.
In fig. 2, the second pull-down current branch 6 includes two pull-down current sub-branches, which are a first pull-down current sub-branch and a second pull-down current sub-branch.
The first pull-down current sub-branch comprises a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a third transmission gate PG 3.
The second pull-down current sub-branch comprises a fifth NMOS transistor MN5, a sixth NMOS transistor MN6 and a fourth transmission gate PG 4.
The drain electrode of the third NMOS transistor MN3 and the drain electrode of the fifth NMOS transistor MN5 are both connected to the third node, and the source electrode of the third NMOS transistor MN3 and the source electrode of the fifth NMOS transistor MN5 are both connected to the drain electrode of the seventh NMOS transistor MN 7.
The data voltage DL is connected to the gate of the third NMOS transistor MN3 through the third pass gate PG3, and the data voltage DL is connected to the gate of the fifth NMOS transistor MN5 through the fourth pass gate PG 4.
The drain electrode of the fourth NMOS transistor MN4 is connected to the gate electrode of the third NMOS transistor MN3, the drain electrode of the sixth NMOS transistor MN6 is connected to the gate electrode of the fifth NMOS transistor MN5, the source electrode of the fourth NMOS transistor MN4 is grounded, the source electrode of the sixth NMOS transistor MN6 is grounded, and the source electrode of the seventh NMOS transistor MN7 is grounded.
A non-inverting control terminal of the third pass gate PG3 is connected to an inverting signal of a second control signal OP3, an inverting control terminal of the third pass gate PG3 is connected to a second control signal OP3, and a gate of the fourth NMOS transistor MN4 is connected to the second control signal OP 3.
A non-inverting control terminal of the fourth pass gate PG4 is connected to an inverted signal of a third control signal OP4, an inverting control terminal of the fourth pass gate PG4 is connected to the third control signal OP4, and a gate of the sixth NMOS transistor MN6 is connected to the third control signal OP 4.
The gate of the seventh NMOS transistor MN7 is connected to a precharge control signal pre.
The first pull-down current branch 5 includes an eighth NMOS transistor MN 8.
The drain of the eighth NMOS transistor MN8 is connected to the third node, the source of the eighth NMOS transistor MN8 is grounded, and the gate of the eighth NMOS transistor MN8 is connected to the output terminal of the first digital circuit 7.
The first digital circuit 7 comprises a first inverter 8, a nand gate 9 and an exclusive nor gate 10.
The second control signal OP3 and the third control signal OP4 are connected to two inputs of the nand gate 9.
The precharge control signal pre is connected to an input of the first inverter 8.
The output end of the first inverter 8 and the output end of the nand gate 9 are respectively connected to two input ends of the exclusive nor gate 10, and the output end of the exclusive nor gate 10 serves as the output end of the first digital circuit 7.
The amplifier main body circuit 1 further includes a precharge circuit including a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP 5.
The source of the third PMOS transistor MP3 is connected to a power supply voltage, and the drain of the third PMOS transistor MP3 is connected to the second node OUT 2.
The source of the fourth PMOS transistor MP4 is connected to a power supply voltage, and the drain of the fourth PMOS transistor MP4 is connected to the first node OUT 1.
The source of the fifth PMOS transistor MP5 is connected to the first node OUT1, and the drain of the fourth PMOS transistor MP4 is connected to the second node OUT 2.
The gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, and the gate of the fifth PMOS transistor MP5 are all connected to a precharge control signal pre.
The amplifier main body circuit 1 further comprises an enable circuit, the enable circuit comprises a ninth NMOS transistor MN9, a drain of the ninth NMOS transistor MN9 is connected to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2, the source of the ninth NMOS transistor MN9 is grounded, and a gate of the ninth NMOS transistor MN9 is connected to an enable signal.
The embodiment of the invention carries out targeted setting on the reference bias network circuit 2 providing the reference voltage Vref, the reference voltage Vref is set to be dynamically changed according to the data voltage DL, mainly in the operation of reading 0, the reference voltage Vref is gradually increased when the data voltage DL is gradually reduced, thus the voltage difference between the reference voltage Vref and the data voltage DL in the operation of reading 0 can be increased, and the voltage difference between the reference voltage Vref and the data voltage DL does not need to be increased by reducing the voltage of the data voltage DL after discharging, so the reading window can be improved; the embodiment of the invention can reduce the discharge of the data voltage DL in the read 0 operation, thereby improving the read rate and reducing the dynamic power consumption.
As shown in fig. 3, which is a signal curve of the single-ended sense amplifier of the embodiment of the present invention during the reading process, the curve 301 corresponds to a curve of the data voltage DL in the read 1 operation, the curve 302 corresponds to a curve of the reference voltage Vref in the read 1 operation, the curve 303 corresponds to a curve of the data voltage DL in the read 0 operation, and the curve 304 corresponds to a curve of the reference voltage Vref in the read 0 operation. It can be seen that in the read 1 operation, the data voltage DL is kept at a high level, the data voltage DL is greater than the reference voltage Vref and the difference between the two is dv 301. In the read 0 operation, the data voltage DL is discharged to a low level, but the level of the reference voltage Vref is also increased, and finally the data voltage DL is made smaller than the reference voltage Vref and the voltage difference between the two is dv300+ dv300a, where dv300a is the influence value of the increase of the read voltage difference of the read 0 operation due to the increase of the reference voltage Vref. The invention can improve the reading window of the 0 reading operation; this enables the initial value of the reference voltage Vref, i.e., the first low level, to be maintained or lowered due to the increase of the read window for the read 0 operation, which also enables the read window for the read 1 operation to be maintained or increased.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (11)
1. A single-ended operated sense amplifier, characterized by: the circuit comprises an amplifier main body circuit, wherein a first input end of the amplifier main body circuit is connected with a reference voltage, a second input end of the amplifier main body circuit is connected with a data line, and an output end of the amplifier main body circuit outputs a comparison signal of the reference voltage and the data voltage of the data line;
the data line is connected with the storage unit, the reference voltage is output by the output end of the reference bias network circuit, and the data voltage is input into the reference bias network circuit and dynamically adjusts the reference voltage;
the data voltage is precharged to a first high level and the reference voltage is preset to a first low level before a read operation;
the read operation when the information stored in the memory cell is 0 is a read 0 operation, in the read 0 operation, the data line is discharged through the memory cell and the data voltage is gradually reduced from a first high level to a second low level, the second low level is lower than the first low level, the reference voltage is gradually increased to a second high level by the gradually reduced data voltage, the second high level is lower than the first high level, a read window in the read 0 operation is increased by the increased reference voltage, and the read window is a difference value between the reference voltage and the data voltage;
the reference bias network circuit comprises a comparison circuit consisting of a pull-up current source and a pull-down current source, wherein the pull-up current source and the pull-down current source are connected at a third node and form an output end for outputting the reference voltage;
the control end of the pull-down current source is connected with the data line, and in the reading process, when the data voltage is reduced, the current of the pull-down current source is reduced and the reference voltage is increased, so that the reference voltage is gradually increased in the read 0 operation and is kept in the read 1 operation;
the pull-down current source comprises a first pull-down current branch and a second pull-down current branch, and the current magnitude of the second pull-down current branch is controlled by the data voltage;
the second pull-down current branch comprises a plurality of pull-down current sub-branches, the current magnitude of each pull-down current sub-branch is controlled by the data voltage, and the current magnitude of the second pull-down current branch is adjusted by performing combined control on each pull-down current sub-branch;
in the reading process, the first pull-down current branch is cut off, and the second pull-down current branch is conducted; in the pre-charging process, the first pull-down current branch is conducted, and the second pull-down current branch is cut off.
2. The single-ended operated sense amplifier of claim 1, wherein: the read operation when the information stored in the memory cell is 1 is a read 1 operation, in the read 1 operation, the data voltage is maintained at the first high level, the data voltage at the first high level maintains the reference voltage at the first low level, and a read window in the read 1 operation is maintained or increased.
3. The single-ended operated sense amplifier of claim 2, wherein: the amplifier main body circuit comprises a first CMOS circuit formed by connecting a first NMOS transistor and a first PMOS transistor and a second CMOS circuit formed by connecting a second NMOS transistor and a second PMOS transistor, wherein the input end of the first CMOS circuit and the output end of the second CMOS circuit are both connected to a first node, and the output end of the first CMOS circuit and the input end of the second CMOS circuit are both connected to a second node.
4. The single-ended operated sense amplifier of claim 3, wherein: a first input end of the amplifier main body circuit is connected with the reference voltage through a first transmission gate;
and the second input end of the amplifier main body circuit is connected with the data voltage through a second transmission gate.
5. The single-ended operated sense amplifier of claim 4, wherein: the first transmission gate and the second transmission gate are both CMOS transmission gates;
the positive phase control end of the first transmission gate is connected with a first control signal, and the negative phase control end of the first transmission gate is connected with the negative phase signal of the first control signal; the positive phase control end of the second transmission gate is connected with the first control signal, and the negative phase control end of the second transmission gate is connected with the negative phase signal of the first control signal.
6. The single-ended operated sense amplifier of claim 1, wherein: the pull-up current source is formed by connecting a plurality of pull-up current branches in parallel, and the size of the pull-up current source is adjusted by performing combined control on each pull-up current branch.
7. The single-ended operated sense amplifier of claim 1, wherein: the conduction and the cut-off of the first pull-down current branch and the second pull-down current branch are controlled by a first digital circuit.
8. The single-ended operated sense amplifier of claim 7, wherein: the second pull-down current branch comprises two pull-down current sub-branches which are a first pull-down current sub-branch and a second pull-down current sub-branch respectively;
the first pull-down electronic branch comprises a third NMOS (N-channel metal oxide semiconductor) tube, a fourth NMOS tube and a third transmission gate;
the second pull-down current sub-branch comprises a fifth NMOS tube, a sixth NMOS tube and a fourth transmission gate;
the drain electrode of the third NMOS tube and the drain electrode of the fifth NMOS tube are both connected with the third node, and the source electrode of the third NMOS tube and the source electrode of the fifth NMOS tube are both connected with the drain electrode of a seventh NMOS tube;
the data voltage is connected to the grid electrode of the third NMOS tube through the third transmission gate, and the data voltage is connected to the grid electrode of the fifth NMOS tube through the fourth transmission gate;
the drain electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the drain electrode of the sixth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the source electrode of the sixth NMOS tube is grounded, and the source electrode of the seventh NMOS tube is grounded;
the positive phase control end of the third transmission gate is connected with the reverse phase signal of the second control signal, the reverse phase control end of the third transmission gate is connected with the second control signal, and the grid electrode of the fourth NMOS tube is connected with the second control signal;
the positive phase control end of the fourth transmission gate is connected with the inverted signal of the third control signal, the inverted control end of the fourth transmission gate is connected with the third control signal, and the grid electrode of the sixth NMOS tube is connected with the third control signal;
and the grid electrode of the seventh NMOS tube is connected with a pre-charge control signal.
9. The single-ended operated sense amplifier of claim 8, wherein: the first pull-down current branch comprises an eighth NMOS transistor;
the drain electrode of the eighth NMOS tube is connected with the third node, the source electrode of the eighth NMOS tube is grounded, and the grid electrode of the eighth NMOS tube is connected with the output end of the first digital circuit;
the first digital circuit comprises a first inverter, a NAND gate and an XNOR gate;
the second control signal and the third control signal are connected to two input ends of the NAND gate;
the precharge control signal is connected to an input terminal of the first inverter;
the output end of the first inverter and the output end of the NAND gate are respectively connected to two input ends of the XNOR gate, and the output end of the XNOR gate is used as the output end of the first digital circuit.
10. The single-ended operated sense amplifier of claim 3, wherein: the amplifier main body circuit further comprises a pre-charge circuit, wherein the pre-charge circuit comprises a third PMOS (P-channel metal oxide semiconductor) transistor, a fourth PMOS transistor and a fifth PMOS transistor;
the source electrode of the third PMOS tube is connected with a power supply voltage, and the drain electrode of the third PMOS tube is connected with the second node;
the source electrode of the fourth PMOS tube is connected with a power supply voltage, and the drain electrode of the fourth PMOS tube is connected with the first node;
the source electrode of the fifth PMOS tube is connected with the first node, and the drain electrode of the fifth PMOS tube is connected with the second node;
the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube are all connected with a pre-charging control signal.
11. The single-ended operated sense amplifier of claim 3, wherein: the amplifier main body circuit further comprises an enabling circuit, the enabling circuit comprises a ninth NMOS tube, the drain electrode of the ninth NMOS tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube, the source electrode of the ninth NMOS tube is grounded, and the grid electrode of the ninth NMOS tube is connected with an enabling signal.
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| KR102282401B1 (en) * | 2015-01-02 | 2021-07-26 | 삼성전자주식회사 | Device and Method for training reference voltage |
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