JPH01235094A - I/o line load circuit - Google Patents

Abstract

PURPOSE:To speed up access by controlling the potentials of 1st and 2nd I/O lines via a potential control means based on 1st and 2nd reference voltage levels that vary in accordance with the action mode of a semiconductor memory. CONSTITUTION:A potential control means 13 contains 1st and 2nd N channel MOS transistors TR1001 and TR1003 which are connected between the I/O line pairs 1 and 2 and a 1st power supply 11 having a potential higher than the precharge potentials of the line pairs 1 and 2. At the same time, the control 13 also includes 3rd and 4th P channel MOS TR1002 and TR1004 which are connected between the line pairs 1 and 2 and a 2nd power supply 12 having a potential lower than the line pairs 1 and 2. The output voltage of the power supply 11 is applied to the gates of both TR1001 and TR1003; while the output voltage of the power supply 12 is given to the gates of both TR1002 and TR1004 respectively. As a result, the potential of each I/O line is always controlled in an optimum state and the access speed is increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an I/O line load circuit, and particularly to a circuit for controlling an I/O line pair potential in a semiconductor memory device to a predetermined potential according to its operation cycle. This article relates to an engineering/O line load circuit for

[Prior Art] FIG. 9 is a circuit diagram showing an example of a conventional dynamic semiconductor memory device. In the figure, this semiconductor memory device has a memory cell pair 1.04,/O4 each including one transistor, one capacitor type memory cell for 2 bits.
. . . and a sense amplifier/O5 . . . which amplifies the potential difference between bit lines BL and n. /O5..., bit line BL and I/O line 1. I/O switches /O6, /O6... for connecting bit IBL and l/O412, and each I/O
Column decoder /O7. for controlling switch /O6. /
O7..., a precharge/equalization circuit /O1 for precharging and equalizing I/O line pairs 1 and 2, and amplifying the information on I/O line pairs 1 and 2 and transmitting the information to the read data bus RD. Information is written to the memory cell via the preamplifier/O2 and write data bus WD to the I/O line pair 1 and 2 via the I/O switch/O6, bit lines BL and BL, and sense amplifier/O5. It is equipped with a write buffer /O3 for reading data.

Next, the operation of the above conventional device will be explained.

First, one word line among a large number of word lines WLI, WL2... becomes active, so that each bit line pair BL
A 1-bit memory cell is selected for each of the bit lines BL and BL, and the information thereof is read onto the bit line BL or BL. When sense amplifier activation signals φSN and φSP are activated in this state, the potential difference between bit line pair BL and BL is amplified and latched by sense amplifier /O5, and the selected memory cell is read and refreshed. On the other hand, at this time, the I/O line equalize signal l0EQ is in the active state, and the I/O line equalize signal l0EQ is activated by the precharge circuit /O1.
/O line pair 1 and 2 are precharged to power supply voltage Vcc. Next, when the sensing operation is completed, only one column decoder /O7 becomes selected, and the I/O gate /O6 connected to it becomes conductive to connect the selected bit line BL and I/O gate.
O/O line 1 selection bit line BL and I/O line 2 are respectively connected.

Note that at this time, the I/O line equalize signal l0EQ is inactive. Therefore, the potential of the I/O line pair 1 and 2 becomes the “H” level power supply potential Vcc, and the “L° level becomes the ground potential OV.
By activating the preamplifier activation signal PAE, the information is output to the read data bus RD via the preamplifier/O2 composed of a current mirror amplifier and a 3-state buffer.

As mentioned above, in the conventional device shown in FIG. 9, the level of I/O line 1 or I/O line 2 changes from Vcc to Ov when reading information.
However, this amplitude is excessive considering the gain of the current mirror amplifier. Therefore, this excessive amplitude requires that, for example, in the page mode cycle of a dynamic semiconductor memory device, I/O line 1 is initially at "Ho" or Vcc, but then changes to "L" or OV when the next signal is applied. In some cases, the time required for the I/O line potential to change becomes longer.Also, if the I/O line equalization signal /OEQ is activated in each cycle, the time required for equalization becomes longer, and in any case, However, this may cause delays in access time.

A conventional example that improves the above-mentioned drawbacks is shown in FIG. The conventional device shown in FIG. 10 is obtained by adding clamping transistors 200 for I/O line pairs 1 and 2 to the conventional device shown in FIG. That is, by keeping the I/O line clamp signal /OCL active during the read cycle, the "L" level of I/O line 1 or I/O line 2 is approximately VCCVTN-α (VTM is the threshold of transistor 200). voltage).

This eliminates the access time delay due to the causes described in connection with the device of FIG. However, since the current mirror amplifier has a characteristic that its gain decreases when the input voltage is near VCC, this causes an access delay. Also, P channel MO3 of precharge circuit/O1
If the FET is omitted, the I/O line precharge potential can be lowered, but when there is a negative bump in the power supply voltage, that is, when the power supply voltage drops during operation, a high voltage remains on the I/O line pair 1 and 2. access delay occurs.

Note that during writing, by inactivating the I/O line clamp signal IOCL, the clamp circuit 200 can operate the write buffer/
I try not to put a load on O3.

[Problem to be solved by the invention H As described above, in conventional semiconductor memory devices, the amplitude of the I/O line pair is too large, and the preamplifier is operated in the lowest gain region of the current mirror amplifier, so access Time slows down. Furthermore, in the conventional example in which the /O line is clamped to Vcc-V, )1, an access delay occurs when a negative bump is received.

This invention was made to solve the above problems, and aims to provide an I/O/O line load that can speed up access time without causing access delays due to negative bumps. purpose.

[Means for Solving the Problems] The I/O/O line load according to the present invention includes first and second reference voltage generation means that generate a plurality of different reference voltages depending on the operation mode of a semiconductor memory device. and potential control means for controlling the potentials of the first and second I/O lines based on the respective output voltages of the first and second reference voltage generation means, the potential control means is a first power supply whose potential is higher than the precharge potential of the I/O line pair;
and a second I/O line, respectively, and a second N-channel MOS transistor whose potential is lower than the precharge potential of the I/O line pair. third and fourth P-channel type M connected between the power supply and the first I/O line and the second I/O line, respectively;
The output voltage of the first reference voltage generating means is supplied to the first and second N-channel type MOS transistors.
The output voltage of the second reference voltage generating means is applied to each gate of the transistor, and the output voltage of the second reference voltage generating means is applied to the third and fourth P-channel type MO
Provided to each gate of the S transistor.

[Operation] In the present invention, the potential control means controls the potentials of the first and second I/O lines based on the first and second reference voltages whose values change depending on the operation mode of the semiconductor memory device. By controlling this, the potential of the I/O line pair is always kept at an optimal value for speeding up access.

[Example] This invention is based on Japanese Patent Application Laid-Open No. 62-3, which was previously proposed by the applicant.
The internal power supply voltage generation circuit of a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-open No. 6848 and Japanese Patent Application Laid-open No. 119613/1982 is
/O/O line load. FIG. 11 is a circuit shown as FIG. 1 in Japanese Patent Application Laid-Open No. 62-36848. Its characteristics are the above-mentioned Japanese Patent Application Laid-Open No. 62-368.
As described in detail in Publication No. 48, the voltage applied from the reference voltage generation circuit 3 to the gate of the transistor Q5 is set higher than the desired output voltage Vo by the threshold voltage of the transistor Q5, and then the output voltage VO is set higher than the desired output voltage Vo. The transistor Q5 is made conductive only when the voltage drops, and the voltage applied from the reference voltage generation circuit 6 to the gate of the transistor Q6 is lowered by the threshold voltage of the transistor Q6 than the output voltage Vo. By making the transistor Q6 conductive only when the voltage rises, the output voltage Vo delivered to the node N7 is kept at a constant value.

FIG. 1 is a circuit diagram showing an embodiment of the I/O/O line load according to the present invention. Such a 1/O line load circuit/O0
replaces the conventional precharge/equalize circuit /O1 and clamping transistor 200 with an I/O line pair 1
and 2 (see Figure 2). In FIG. 1, the i/O/O line load /O0 schematically includes a first reference voltage generation circuit 11, a second reference voltage generation circuit 12,
The voltage control circuit 13 is also provided. The first reference voltage generation circuit 11 and the second reference voltage generation circuit 12 each generate a plurality of types of reference voltages according to each operation mode of the semiconductor memory device shown in FIG. This is what is output. The voltage control circuit 13 is the first
Based on the reference voltages provided from the reference voltage generation circuit 11 and the second reference voltage generation circuit 12,
and 2 to control the potentials to predetermined values.

The first reference voltage generation circuit 11 includes a resistor 1113, a MOS transistor 1111, and a MOS transistor connected between the power supply and the ground.
It includes a series circuit in which a transistor 1112 and a resistor 1114 are connected in that order.

Note that the drain and gate of the MOS transistor 1111 are both connected to the node N11, and the MOS transistor 1111 has its drain and gate connected to the node N11.
Transistor 1112 has its drain and gate both connected to node N12. This series circuit corresponds to the reference voltage generation circuit 3 in FIG. Further, the first reference voltage generation circuit 11 has nodes Nll and N
It includes a MOS transistor /O11 inserted between the node N12 and the NOI, and a MOS transistor /O12 inserted between the node N12 and the NOI. Control signals φA and φB are applied to the gates of these MO3I-transistors /O11 and /O12, respectively.

These MOS transistors /O11 and /O12 are
A selection circuit is formed that selects one of the potentials of nodes Nll and N12 and transmits it to node NOI. Further, a MOS transistor /O13 is inserted between the node NOI and the ground, and this MOS transistor /O1
A control signal φC is applied to the gate of No. 3. This MOS
Transistor /O13 is a pull-down transistor for forcibly lowering the potential of node NOI to the ground potential. Note that each MOS transistor used in the first reference voltage generation circuit 11 includes an enhancement type N
A channel MOS transistor is used.

Next, the second reference voltage generation circuit 12 connects a resistor 1124 and a MOS transistor 1]22 and a MOSFET between the power supply and ground.
It includes a series circuit in which an S transistor 1121 and a resistor 1123 are connected in that order.

Note that the source and gate of MOS transistor 1122 are both connected to node N14, and the source and gate of MOS transistor 1121 are both connected to node N1B. This series circuit corresponds to the reference voltage generation circuit 6 in FIG. Further, the second reference voltage generation circuit 12 connects the node N14 and the node N
MOS transistor /O22 inserted between node N13 and NO2, and MOS transistor /O21 inserted between node N13 and NO2. Control signals φB and φA are applied to the gates of these MOS transistors /O22 and /O21, respectively. These MOS transistors /O22 and /O21 form a selection circuit that selects one of the potentials of nodes N14 and N13 and transmits it to node NO2. Furthermore, node NO.
A MOS transistor /O23 is inserted between MO3I-transistor /O23 and the power supply, and a control signal φC is applied to the gate of this MO3I-transistor /O23. This MO8I-transistor/O23 is a pull amplifier transistor for forcibly raising the potential of the node NO2 to the power supply voltage. Note that each MO3 used in the second reference voltage generation circuit 12
The transistor is an enhancement type P channel type M
OS transistors are used.

Next, the voltage control circuit 13 includes an N-channel MO8 transistor /O01 and a P-channel MO8! transistor connected in series between the power supply and ground. - N-channel type MOS transistor /O03 and P-channel type MO3, which are also connected in series between the transistor /O02 and the power supply and ground.
Contains two series circuits with transistor /O04. These two series circuits correspond to the internal power supply voltage output stage 7 in FIG. 11, respectively. Therefore, the output voltage of the first reference voltage generation circuit 11, that is, the potential of the node NOI is applied to each gate of the MOS transistors /O01 and /O03, and the MO3I-transistors /O02 and
The output voltage of the second reference voltage generation circuit]2, that is, the potential of the node NO2 is applied to each gate of O04. Further, an N-channel type MOS transistor /O05 is inserted between I/O line 1 and I/O line 2, and the gate of this MOS transistor /O05 is connected to the precharge/equalize circuit /O1 shown in FIG. I/O similar to that given to
A line equalization signal IOEQ is provided. This MOS
Transistor /O05 is an equalization transistor for shorting I/O line pair 1 and 2 before reading data from the semiconductor memory device.

Next, a control signal generation circuit for each control used in the circuit of FIG. 1 using the I/O line equalize signal /OEQ and the I/O line clamp signal l0CL as shown in FIG. An example is shown in FIG. As shown in the figure, this control signal generation circuit is comprised of five inverters 13-17 and two AND gates 18 and 19.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the generation mechanism of the base voltage in the first reference voltage generation circuit 11 and the second reference voltage generation circuit 12 will be explained. In the first reference voltage generation circuit 11,
If the resistance values of resistors 1113 and 1114 are made equal and transistors with the same characteristics are used as MOS transistors 1111 and 1112, the node Nil
The potential of the node N12 becomes (Vc c/2)+VT N and the potential of the node N12 becomes Vcc. Note that VTN is the threshold voltage of an N-channel type MOS transistor.

On the other hand, in the second reference voltage generation circuit 12, if the resistance values of the resistors 124 and 1123 are made equal, and transistors having the same characteristics are used as the MOS transistors 1122 and 1121, the potential of the node N14 becomes Vcc/
2, and the potential of node N13 is (Vc c/2)-1
VT p l.

Note that %Vp is the threshold voltage of the P-channel MOS transistor.

Next, the operation of the embodiment shown in FIG. 1 will be explained for each operation mode in the semiconductor memory device shown in FIG. 2.

■Operation during precharging of I/O line pairs 1 and 2 In this case, each control signal in FIG.
, φB-φC-“L”, φA-“L”.

φB-φC-"H". Therefore, the node NOI
, NO2 potential is (Vcc/2) +VT
N , (Vcc/2) IVTP l, so when the potential of I/O line 1 rises above Vcc/2, the potential is lowered by transistor /O02, and I
When the potential of the /O line 1 falls below V c c /2, the potential is raised by the transistor /O01.

As a result, the potential of the I/O line 1 is kept constant at Vcc/2. At this time, the power supply voltage changes from Vcc to Vcc.
' , the potentials of nodes NOI and NO2 are respectively (V c c' / 2) +VT N .

(Vcc'/2) IVTPI, so ■/O
The potential of the line 1 becomes Vcc'/2, and a high potential does not remain on the I/O line 1 due to the negative bump as described in the conventional example. Similarly to the above, the potential of I/O line 2 is kept constant at Vc c / 2 by the switching action of MOS transistors /O03 and /O04, and the potential also follows fluctuations in the power supply voltage. I will do it. Furthermore, by turning on MOS transistor /O05 at this time, I/O line 1 and
Short-circuit the O wires 2 to make them have the same potential.

■Operation in data read mode In this case, each control signal shown in FIG.
φA=φC-“L”, φB=“L”, φA-φC-“H
It is said to be #. Therefore, both nodes N01 and NO2 are at V
c c / 2, so the potential of ■/O line 1 is (V
cc/2)-VT When the voltage becomes lower than N, the potential of I/O line 1 is raised by MOS transistor /O01, and the I/O
When the potential of line 1 exceeds (Vcc/2) +1VTP 1, MOS transistor /O02 connects I/O line 1.
Since the potential of I/O line 1 is lowered, the amplitude of I/O line 1 is V c
Centered around c/2, it becomes VTN+1VTPl+α. However, α is the MOS transistor /O01, /O02
and sense amplifier/O5. This value is determined by the size of the MOS transistor that constitutes the I/O switch /O6. At this time, if the power supply voltage fluctuates from Vcc to Vcc', both nodes NOI and NO2 become Vcc'/2, so the amplitude of I/O line 1 is centered around CC'/2 and Lte Vy. N + l VT PI + α. Therefore, even if a negative bump occurs, no high potential remains on the I/O line 1. Similarly, the center potential and amplitude of I/O line 2 are regulated by the action of MOS transistors /O03 and /O04, and the potential fluctuates in accordance with fluctuations in the power supply voltage.

■Operation in data write mode In this case, each control signal shown in FIG.
”, φA-φB-”L”, φC-“L”.

φA−φB− is set to “H”. Therefore, node N01
is Ov and node NO2 is vCC, so I/O line 1
When the potential of is in the range of Vcc to Ov, the MOS transistor/
O01. /O02 remains non-conductive. In addition, for I/O line 2, MOS l-ranjisk /O03 and /O
The same voltage control as above is performed by the action of 04.

Figure 4(a) shows the operating states of MOS transistors /O01 and /O02 in the three operating modes explained above.
It is shown below. In addition, in FIG. 4(a), the shaded area is M.
This indicates that the OS transistor is off.

As mentioned above, in the embodiment shown in FIG.
In the high gain region of the current mirror amplifier in
Since the amplitude of the O line pair 1 and 2 is kept constant, high-speed access is possible.

This is shown in FIG. 5 in comparison with a conventional device. Note that FIG. 5(a) shows the case of the embodiment shown in FIG. 1, and FIG. 5(b) shows the case of the conventional device shown in FIG.

Furthermore, in the embodiment shown in FIG. 1, even when the power supply voltage fluctuates, the potentials of the I/O line pair 1 and 2 are changed accordingly, making it possible to eliminate access delays caused by negative bumps. can.

FIG. 6 is a circuit diagram showing another embodiment of the invention.

In the figure, this embodiment differs from the embodiment shown in FIG. 1 in first and second reference voltage generating circuits 11 and 12. That is, the first reference voltage generation circuit 11 includes two series circuits for generating a reference voltage. One series circuit includes a resistor 1213 and an N-channel MOS transistor 1211 inserted in series between the power supply and ground.
It is composed of an N-channel type MOS transistor 1212 and a resistor 1214. Also, the other series circuit is
A resistor 1216 inserted in series between the power supply and ground. N
Channel type MOS transistor 1215 and resistor 12
It consists of 17.

On the other hand, similarly in the second reference voltage generation circuit 12,
Two series circuits are provided for reference voltage generation. One series circuit includes a resistor 1224. P channel type MOS transistor 1
222. It is composed of a P-channel type MOS transistor 1221 and a resistor 1223. The other series circuit is
A resistor 1226 inserted in series between the power supply and ground. P
Channel type MoS transistor 1225 and resistor 12
It consists of 27.

Next, the operation of the embodiment shown in FIG. 6 will be explained with reference to FIG. 4(b). First, when I/O line pairs 1 and 2 are precharged and in data write mode, the circuit operates in the same way as the circuit shown in FIG. Further, in the data read mode, the nodes NOI and NO2 are respectively connected to the nodes N
22. Same potential as N24, i.e. (VCC+VTN)
/2°(Vcc-IVTP +)/2, so the potential of I/O line 1 becomes (Vcc-IVTP +)/2, as shown in Figure 4(b).
VTN)/2 or less, transistor/O01 becomes (
When the voltage exceeds VCC+1VTP l)/2, transistor /O02 turns on, so the amplitude of I/O line 1 becomes 1(V
TN +1VTP l)/21 +α. In addition,
The same applies to I/O line 2.

FIG. 7 is a circuit diagram showing another embodiment of the invention. In the figure, the first reference voltage generation circuit 11 includes a resistor 131
3 and 1314. A series circuit for generating a reference voltage including N-channel type MO5I transistors 1311 and 1312, an N-channel type MO1 transistor /O14 inserted between the output end node N31 of this series circuit and node NOI, and node NOI and an inverter /O16 for inverting the I/O line clamp signal l0CL applied to the gate of the transistor /O14 and applying it to the gate of the transistor /O15. Consisted of. Further, the second reference voltage generation circuit 12 includes a resistor 1323
and 1324°P channel type MoS transistor 13
A series circuit for generating a reference voltage including 21 and 1322, and an output terminal node N32 and a node NO of this series circuit.
P-channel MOS transistor inserted between 2 and
O24, a P-channel MOSh transistor /O25 inserted between the node NO2 and the power supply, and an I/O line clamp signal /O25 applied to the gate of the transistor /O25.
It is constituted by an inverter /O26 for inverting OCL and applying it to the gate of a transistor /O24. The other configurations are similar to the embodiment shown in FIG.

Next, the operation of the embodiment shown in FIG. 7 will be explained.

In the data write mode, that is, when I0CL is “L”, the potentials of nodes NOI and NO2 are QV and V, respectively.
cc, so the potential of I/O line 1 becomes 0V-Vcc (7
) between transistor/O01. /O02 does not turn on.

In other cases, the potentials of nodes N01 and N02 (7) are unstable, (VCC/2)+VT N , (Vc
c/2) -l Vv F I Ni na Runo, 1st
The same operation as in the I/O line precharge in the illustrated embodiment is performed. At this time, the column decoder /O7 shown in FIG. 2 is activated, and the sense amplifier /O5 is activated as shown in FIG.
6 to I/O line pair 1 and 2, I
/Ot! The potential difference between jl vs. 1 and 2 is determined by the sense amplifier, I
/O switch and transistor /O01. It becomes a constant value determined by the size of /O02.

FIG. 8 is a circuit diagram showing still another embodiment of the present invention. In the figure, this embodiment has transistors 1312 and 1322 removed from the embodiment shown in FIG. Therefore, a series circuit for generating a reference voltage in the first reference voltage generating circuit 11 is constituted by resistors 1412 and 1413 and an N-channel MOS transistor 1411. Further, the second reference voltage generation circuit 1
The series circuit for generating the reference voltage in 2 includes a resistor 14
22 and 1423, and a P-channel type MOS transistor 1421.

Next, the operation of the embodiment shown in FIG. 8 will be explained.

In the data write mode, that is, when l0CL-“L”, the same operation as in the embodiment shown in FIG. 7 is performed.

That is, during I/O line precharging and data read mode, the potential of I/O line pair 1 and 2 is (Vc
When it becomes less than C-VT N ) /2, the transistor /O
01 and /O03, the potential increases and becomes (VCC+
When it becomes 1VTP l)/2 or more, the transistor/O0
2 and /O04 lower the potential. therefore,
The precharge potential of I/O line pair 1 and 2 is (Vc
c+ l VT F I )/2~(Vc C-VT
y )/2. However, if the sensitivity of the preamplifier/O2 is high and the fluctuation of the precharge potential within this range does not affect data reading,
The power consumption during I/O line precharging can be reduced compared to the three embodiments described above. As stated in the above-mentioned Japanese Patent Application Laid-open No. 119613/1983,
In the three embodiments mentioned above, even if the I/O line potential is Vcc/2, Vcc-+) Rangemetal/O01-I/O
This is because a small current flows through the path from line 1 to transistor/O02 to ground.

In addition, dynamic random access memory RAS
During a period such as a precharge period when data is not read or written through the I/O line pair, node NO1 is turned off.
By setting the node NO2 to VcC, the current flowing by the I/O line load circuit during this period is only that of the reference voltage generating circuit. Furthermore, by providing a transistor in series with the base L$ voltage generation circuit and making the transistor non-conductive during this period, the current flowing through the I/O line load circuit can be almost completely eliminated.

Note that, as disclosed in the above-mentioned two published applications, MOS diodes may be used in place of the resistors used in the first and second reference voltage generation circuits 11 and 12.

Further, in the embodiment described above, the precharge potential of the I/O line pair 1 and 2 is set to Vcc/2, but the resistance ratio of the first and second reference voltage generation circuits and the MO
By changing the number of stages of S diodes, the precharge potential can be changed arbitrarily.

Furthermore, although the above embodiments have been described as examples applied to dynamic type semiconductor memory devices, the same effects as described above can be obtained when applied to static type semiconductor memory devices.

[Effects of the Invention] As explained above, according to the present invention, the potential of each 1/O line can always be controlled to the optimum state according to the operation mode of the semiconductor memory device, so that access delay due to negative bumps is not caused. The access speed can be increased without any problems.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an I/O line load circuit according to the present invention. FIG. 2 is a diagram showing the configuration of a dynamic semiconductor memory device using the I/O line load circuit of the present invention. FIG. 3 is a logic circuit diagram showing an example of the configuration of each control signal generating circuit used in the embodiment shown in FIG. 1. FIGS. 4(a) and 4(b) are schematic diagrams for explaining the operations of the embodiment shown in FIG. 1 and the embodiment shown in FIG. 6, respectively. FIG. 5 is a waveform diagram for explaining the difference in access speed between the embodiment shown in FIG. 1 and the conventional example shown in FIG. FIG. 6 is a circuit diagram showing the configuration of another embodiment of the invention. FIG. 7 is a circuit diagram showing the configuration of still another embodiment of the invention. FIG. 8 is a circuit diagram showing the configuration of still another embodiment of the present invention. FIG. 9 is a circuit diagram showing an example of a conventional dynamic semiconductor memory device. FIG. 2 is a circuit diagram showing another example of a conventional dynamic semiconductor memory device. FIG. 11 is a diagram showing a circuit disclosed in the specification filed by the applicant of the present invention, which is the premise of this invention. In the figure, 1 is the I/O line, 2 is the I/O line, and 11 is the first
12 is a second reference voltage generation circuit,
13 is a voltage control circuit, /O01° /O03 and /O0
Reference numeral 5 indicates an N-channel type MOS transistor, and /O02 and /O04 indicate P-channel type MOS transistors.

Claims (1)

[Scope of Claims] I/O provided in a semiconductor memory device having a plurality of memory cells for transmitting write information to the memory cells and read information from the memory cells to/from an external circuit.
an I/O line load circuit for setting a potential of a line pair to a predetermined potential according to an operation cycle of the semiconductor memory device, the I/O line pair being set to a predetermined potential when writing information to a memory cell; It includes a first I/O line and a second I/O line that are driven complementary to each other when reading information from the memory cell, and there are a plurality of types depending on the operation mode of the semiconductor memory device. a first reference voltage generating means that generates different reference voltages; a second reference voltage generating means that generates a plurality of different reference voltages according to the operation mode of the semiconductor memory device; A potential control means is provided for controlling the potential of the first and second I/O lines based on each output voltage of the reference voltage generation means, and the potential control means is configured to control the potential of the I/O line pair. The first one has a higher potential than the charge potential.
first and second N-channel type MOS transistors connected between the power supply of the first I/O line and the second I/O line, respectively; and precharging of the I/O line pair. the second with a lower potential than the potential
third and fourth P-channel type MOS transistors connected between the power source of the power source and the first I/O line and the second I/O line, respectively, the first reference voltage generation The output voltage of the means is applied to each gate of the first and second N-channel MOS transistors, and the output voltage of the second reference voltage generating means is applied to each gate of the third and fourth P-channel MOS transistors. I/O line load circuit applied to the gate.